Revision 538ddf65
| b/hw/mpcore.c | ||
|---|---|---|
| 36 | 36 |
|
| 37 | 37 |
/* Per-CPU private memory mapped IO. */ |
| 38 | 38 |
|
| 39 |
static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset,
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| 40 |
unsigned size)
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| 39 |
static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
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| 40 |
unsigned size) |
|
| 41 | 41 |
{
|
| 42 | 42 |
mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
| 43 | 43 |
int id; |
| 44 | 44 |
offset &= 0xff; |
| 45 |
if (offset < 0x100) {
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| 46 |
/* SCU */ |
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switch (offset) {
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| 48 |
case 0x00: /* Control. */ |
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| 49 |
return s->scu_control; |
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| 50 |
case 0x04: /* Configuration. */ |
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id = ((1 << s->num_cpu) - 1) << 4; |
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return id | (s->num_cpu - 1); |
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| 53 |
case 0x08: /* CPU status. */ |
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return 0; |
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case 0x0c: /* Invalidate all. */ |
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return 0; |
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default: |
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goto bad_reg; |
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} |
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| 45 |
/* SCU */ |
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switch (offset) {
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| 47 |
case 0x00: /* Control. */ |
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return s->scu_control; |
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case 0x04: /* Configuration. */ |
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id = ((1 << s->num_cpu) - 1) << 4; |
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return id | (s->num_cpu - 1); |
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case 0x08: /* CPU status. */ |
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return 0; |
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case 0x0c: /* Invalidate all. */ |
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return 0; |
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default: |
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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| 60 | 58 |
} |
| 61 |
bad_reg: |
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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return 0; |
|
| 64 | 59 |
} |
| 65 | 60 |
|
| 66 |
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
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| 67 |
uint64_t value, unsigned size)
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| 61 |
static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size) |
|
| 68 | 63 |
{
|
| 69 | 64 |
mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
| 70 | 65 |
offset &= 0xff; |
| 71 |
if (offset < 0x100) {
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/* SCU */ |
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switch (offset) {
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case 0: /* Control register. */ |
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s->scu_control = value & 1; |
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break; |
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case 0x0c: /* Invalidate all. */ |
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/* This is a no-op as cache is not emulated. */ |
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break; |
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default: |
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goto bad_reg; |
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} |
|
| 66 |
/* SCU */ |
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switch (offset) {
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case 0: /* Control register. */ |
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s->scu_control = value & 1; |
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break; |
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case 0x0c: /* Invalidate all. */ |
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/* This is a no-op as cache is not emulated. */ |
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break; |
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| 74 |
default: |
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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| 83 | 76 |
} |
| 84 |
return; |
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bad_reg: |
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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| 87 | 77 |
} |
| 88 | 78 |
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| 89 |
static const MemoryRegionOps mpcore_priv_ops = {
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.read = mpcore_priv_read,
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.write = mpcore_priv_write,
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| 79 |
static const MemoryRegionOps mpcore_scu_ops = {
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.read = mpcore_scu_read,
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.write = mpcore_scu_write,
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| 92 | 82 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 93 | 83 |
}; |
| 94 | 84 |
|
| ... | ... | |
| 106 | 96 |
int i; |
| 107 | 97 |
SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); |
| 108 | 98 |
memory_region_init(&s->container, "mpcode-priv-container", 0x2000); |
| 109 |
memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", |
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0x100); |
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| 99 |
memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); |
|
| 111 | 100 |
memory_region_add_subregion(&s->container, 0, &s->iomem); |
| 112 | 101 |
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs |
| 113 | 102 |
* at 0x200, 0x300... |
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