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1 | dbda808a | bellard | /*
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2 | dbda808a | bellard | * OpenPIC emulation
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3 | 5fafdf24 | ths | *
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4 | dbda808a | bellard | * Copyright (c) 2004 Jocelyn Mayer
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5 | 704c7e5d | Alexander Graf | * 2011 Alexander Graf
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6 | 5fafdf24 | ths | *
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7 | dbda808a | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | dbda808a | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | dbda808a | bellard | * in the Software without restriction, including without limitation the rights
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10 | dbda808a | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | dbda808a | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | dbda808a | bellard | * furnished to do so, subject to the following conditions:
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13 | dbda808a | bellard | *
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14 | dbda808a | bellard | * The above copyright notice and this permission notice shall be included in
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15 | dbda808a | bellard | * all copies or substantial portions of the Software.
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16 | dbda808a | bellard | *
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17 | dbda808a | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | dbda808a | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | dbda808a | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | dbda808a | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | dbda808a | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | dbda808a | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | dbda808a | bellard | * THE SOFTWARE.
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24 | dbda808a | bellard | */
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25 | dbda808a | bellard | /*
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26 | dbda808a | bellard | *
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27 | dbda808a | bellard | * Based on OpenPic implementations:
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28 | 67b55785 | blueswir1 | * - Intel GW80314 I/O companion chip developer's manual
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29 | dbda808a | bellard | * - Motorola MPC8245 & MPC8540 user manuals.
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30 | dbda808a | bellard | * - Motorola MCP750 (aka Raven) programmer manual.
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31 | dbda808a | bellard | * - Motorola Harrier programmer manuel
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32 | dbda808a | bellard | *
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33 | dbda808a | bellard | * Serial interrupts, as implemented in Raven chipset are not supported yet.
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34 | 5fafdf24 | ths | *
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35 | dbda808a | bellard | */
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36 | 87ecb68b | pbrook | #include "hw.h" |
37 | 87ecb68b | pbrook | #include "ppc_mac.h" |
38 | 87ecb68b | pbrook | #include "pci.h" |
39 | b7169916 | aurel32 | #include "openpic.h" |
40 | dbda808a | bellard | |
41 | 611493d9 | bellard | //#define DEBUG_OPENPIC
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42 | dbda808a | bellard | |
43 | dbda808a | bellard | #ifdef DEBUG_OPENPIC
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44 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
45 | dbda808a | bellard | #else
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46 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
47 | dbda808a | bellard | #endif
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48 | dbda808a | bellard | |
49 | dbda808a | bellard | #define USE_MPCxxx /* Intel model is broken, for now */ |
50 | dbda808a | bellard | |
51 | dbda808a | bellard | #if defined (USE_INTEL_GW80314)
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52 | dbda808a | bellard | /* Intel GW80314 I/O Companion chip */
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53 | dbda808a | bellard | |
54 | dbda808a | bellard | #define MAX_CPU 4 |
55 | dbda808a | bellard | #define MAX_IRQ 32 |
56 | dbda808a | bellard | #define MAX_DBL 4 |
57 | dbda808a | bellard | #define MAX_MBX 4 |
58 | dbda808a | bellard | #define MAX_TMR 4 |
59 | dbda808a | bellard | #define VECTOR_BITS 8 |
60 | a675155e | Alexander Graf | #define MAX_IPI 4 |
61 | dbda808a | bellard | |
62 | dbda808a | bellard | #define VID (0x00000000) |
63 | dbda808a | bellard | |
64 | dbda808a | bellard | #elif defined(USE_MPCxxx)
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65 | dbda808a | bellard | |
66 | bbc58422 | Alexander Graf | #define MAX_CPU 15 |
67 | b7169916 | aurel32 | #define MAX_IRQ 128 |
68 | dbda808a | bellard | #define MAX_DBL 0 |
69 | dbda808a | bellard | #define MAX_MBX 0 |
70 | dbda808a | bellard | #define MAX_TMR 4 |
71 | dbda808a | bellard | #define VECTOR_BITS 8 |
72 | dbda808a | bellard | #define MAX_IPI 4 |
73 | dbda808a | bellard | #define VID 0x03 /* MPIC version ID */ |
74 | dbda808a | bellard | #define VENI 0x00000000 /* Vendor ID */ |
75 | dbda808a | bellard | |
76 | dbda808a | bellard | enum {
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77 | dbda808a | bellard | IRQ_IPVP = 0,
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78 | dbda808a | bellard | IRQ_IDE, |
79 | dbda808a | bellard | }; |
80 | dbda808a | bellard | |
81 | b7169916 | aurel32 | /* OpenPIC */
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82 | b7169916 | aurel32 | #define OPENPIC_MAX_CPU 2 |
83 | b7169916 | aurel32 | #define OPENPIC_MAX_IRQ 64 |
84 | b7169916 | aurel32 | #define OPENPIC_EXT_IRQ 48 |
85 | b7169916 | aurel32 | #define OPENPIC_MAX_TMR MAX_TMR
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86 | b7169916 | aurel32 | #define OPENPIC_MAX_IPI MAX_IPI
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87 | dbda808a | bellard | |
88 | b7169916 | aurel32 | /* Interrupt definitions */
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89 | b7169916 | aurel32 | #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */ |
90 | b7169916 | aurel32 | #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */ |
91 | b7169916 | aurel32 | #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */ |
92 | b7169916 | aurel32 | #if OPENPIC_MAX_IPI > 0 |
93 | b7169916 | aurel32 | #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */ |
94 | b7169916 | aurel32 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */ |
95 | dbda808a | bellard | #else
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96 | b7169916 | aurel32 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */ |
97 | b7169916 | aurel32 | #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */ |
98 | dbda808a | bellard | #endif
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99 | dbda808a | bellard | |
100 | b7169916 | aurel32 | /* MPIC */
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101 | b7169916 | aurel32 | #define MPIC_MAX_CPU 1 |
102 | b7169916 | aurel32 | #define MPIC_MAX_EXT 12 |
103 | b7169916 | aurel32 | #define MPIC_MAX_INT 64 |
104 | b7169916 | aurel32 | #define MPIC_MAX_MSG 4 |
105 | b7169916 | aurel32 | #define MPIC_MAX_MSI 8 |
106 | b7169916 | aurel32 | #define MPIC_MAX_TMR MAX_TMR
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107 | b7169916 | aurel32 | #define MPIC_MAX_IPI MAX_IPI
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108 | b7169916 | aurel32 | #define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
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109 | dbda808a | bellard | |
110 | dbda808a | bellard | /* Interrupt definitions */
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111 | b7169916 | aurel32 | #define MPIC_EXT_IRQ 0 |
112 | b7169916 | aurel32 | #define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
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113 | b7169916 | aurel32 | #define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
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114 | b7169916 | aurel32 | #define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
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115 | b7169916 | aurel32 | #define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
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116 | b7169916 | aurel32 | #define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
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117 | b7169916 | aurel32 | |
118 | b7169916 | aurel32 | #define MPIC_GLB_REG_START 0x0 |
119 | b7169916 | aurel32 | #define MPIC_GLB_REG_SIZE 0x10F0 |
120 | b7169916 | aurel32 | #define MPIC_TMR_REG_START 0x10F0 |
121 | b7169916 | aurel32 | #define MPIC_TMR_REG_SIZE 0x220 |
122 | b7169916 | aurel32 | #define MPIC_EXT_REG_START 0x10000 |
123 | b7169916 | aurel32 | #define MPIC_EXT_REG_SIZE 0x180 |
124 | b7169916 | aurel32 | #define MPIC_INT_REG_START 0x10200 |
125 | b7169916 | aurel32 | #define MPIC_INT_REG_SIZE 0x800 |
126 | b7169916 | aurel32 | #define MPIC_MSG_REG_START 0x11600 |
127 | b7169916 | aurel32 | #define MPIC_MSG_REG_SIZE 0x100 |
128 | b7169916 | aurel32 | #define MPIC_MSI_REG_START 0x11C00 |
129 | b7169916 | aurel32 | #define MPIC_MSI_REG_SIZE 0x100 |
130 | b7169916 | aurel32 | #define MPIC_CPU_REG_START 0x20000 |
131 | bc59d9c9 | Alexander Graf | #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) |
132 | b7169916 | aurel32 | |
133 | b7169916 | aurel32 | enum mpic_ide_bits {
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134 | 0d33defb | Alexander Graf | IDR_EP = 31,
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135 | 0d33defb | Alexander Graf | IDR_CI0 = 30,
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136 | 0d33defb | Alexander Graf | IDR_CI1 = 29,
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137 | 0d33defb | Alexander Graf | IDR_P1 = 1,
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138 | 0d33defb | Alexander Graf | IDR_P0 = 0,
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139 | b7169916 | aurel32 | }; |
140 | b7169916 | aurel32 | |
141 | dbda808a | bellard | #else
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142 | b7169916 | aurel32 | #error "Please select which OpenPic implementation is to be emulated" |
143 | dbda808a | bellard | #endif
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144 | dbda808a | bellard | |
145 | 5c4532ee | Blue Swirl | #define OPENPIC_PAGE_SIZE 4096 |
146 | 5c4532ee | Blue Swirl | |
147 | dbda808a | bellard | #define BF_WIDTH(_bits_) \
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148 | dbda808a | bellard | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
149 | dbda808a | bellard | |
150 | dbda808a | bellard | static inline void set_bit (uint32_t *field, int bit) |
151 | dbda808a | bellard | { |
152 | dbda808a | bellard | field[bit >> 5] |= 1 << (bit & 0x1F); |
153 | dbda808a | bellard | } |
154 | dbda808a | bellard | |
155 | dbda808a | bellard | static inline void reset_bit (uint32_t *field, int bit) |
156 | dbda808a | bellard | { |
157 | dbda808a | bellard | field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
158 | dbda808a | bellard | } |
159 | dbda808a | bellard | |
160 | dbda808a | bellard | static inline int test_bit (uint32_t *field, int bit) |
161 | dbda808a | bellard | { |
162 | dbda808a | bellard | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
163 | dbda808a | bellard | } |
164 | dbda808a | bellard | |
165 | 704c7e5d | Alexander Graf | static int get_current_cpu(void) |
166 | 704c7e5d | Alexander Graf | { |
167 | 704c7e5d | Alexander Graf | return cpu_single_env->cpu_index;
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168 | 704c7e5d | Alexander Graf | } |
169 | 704c7e5d | Alexander Graf | |
170 | 704c7e5d | Alexander Graf | static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr, |
171 | 704c7e5d | Alexander Graf | int idx);
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172 | 704c7e5d | Alexander Graf | static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr, |
173 | 704c7e5d | Alexander Graf | uint32_t val, int idx);
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174 | 704c7e5d | Alexander Graf | |
175 | dbda808a | bellard | enum {
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176 | dbda808a | bellard | IRQ_EXTERNAL = 0x01,
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177 | dbda808a | bellard | IRQ_INTERNAL = 0x02,
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178 | dbda808a | bellard | IRQ_TIMER = 0x04,
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179 | dbda808a | bellard | IRQ_SPECIAL = 0x08,
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180 | b1d8e52e | blueswir1 | }; |
181 | dbda808a | bellard | |
182 | c227f099 | Anthony Liguori | typedef struct IRQ_queue_t { |
183 | dbda808a | bellard | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
184 | dbda808a | bellard | int next;
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185 | dbda808a | bellard | int priority;
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186 | c227f099 | Anthony Liguori | } IRQ_queue_t; |
187 | dbda808a | bellard | |
188 | c227f099 | Anthony Liguori | typedef struct IRQ_src_t { |
189 | dbda808a | bellard | uint32_t ipvp; /* IRQ vector/priority register */
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190 | dbda808a | bellard | uint32_t ide; /* IRQ destination register */
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191 | dbda808a | bellard | int type;
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192 | dbda808a | bellard | int last_cpu;
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193 | 611493d9 | bellard | int pending; /* TRUE if IRQ is pending */ |
194 | c227f099 | Anthony Liguori | } IRQ_src_t; |
195 | dbda808a | bellard | |
196 | dbda808a | bellard | enum IPVP_bits {
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197 | dbda808a | bellard | IPVP_MASK = 31,
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198 | dbda808a | bellard | IPVP_ACTIVITY = 30,
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199 | dbda808a | bellard | IPVP_MODE = 29,
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200 | dbda808a | bellard | IPVP_POLARITY = 23,
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201 | dbda808a | bellard | IPVP_SENSE = 22,
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202 | dbda808a | bellard | }; |
203 | dbda808a | bellard | #define IPVP_PRIORITY_MASK (0x1F << 16) |
204 | 611493d9 | bellard | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
205 | dbda808a | bellard | #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
206 | dbda808a | bellard | #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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207 | dbda808a | bellard | |
208 | c227f099 | Anthony Liguori | typedef struct IRQ_dst_t { |
209 | b7169916 | aurel32 | uint32_t tfrr; |
210 | dbda808a | bellard | uint32_t pctp; /* CPU current task priority */
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211 | dbda808a | bellard | uint32_t pcsr; /* CPU sensitivity register */
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212 | c227f099 | Anthony Liguori | IRQ_queue_t raised; |
213 | c227f099 | Anthony Liguori | IRQ_queue_t servicing; |
214 | e9df014c | j_mayer | qemu_irq *irqs; |
215 | c227f099 | Anthony Liguori | } IRQ_dst_t; |
216 | dbda808a | bellard | |
217 | c227f099 | Anthony Liguori | typedef struct openpic_t { |
218 | dbda808a | bellard | PCIDevice pci_dev; |
219 | 23c5e4ca | Avi Kivity | MemoryRegion mem; |
220 | 71cf9e62 | Fabien Chouteau | |
221 | 71cf9e62 | Fabien Chouteau | /* Sub-regions */
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222 | 71cf9e62 | Fabien Chouteau | MemoryRegion sub_io_mem[7];
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223 | 71cf9e62 | Fabien Chouteau | |
224 | dbda808a | bellard | /* Global registers */
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225 | dbda808a | bellard | uint32_t frep; /* Feature reporting register */
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226 | dbda808a | bellard | uint32_t glbc; /* Global configuration register */
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227 | dbda808a | bellard | uint32_t micr; /* MPIC interrupt configuration register */
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228 | dbda808a | bellard | uint32_t veni; /* Vendor identification register */
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229 | e9df014c | j_mayer | uint32_t pint; /* Processor initialization register */
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230 | dbda808a | bellard | uint32_t spve; /* Spurious vector register */
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231 | dbda808a | bellard | uint32_t tifr; /* Timer frequency reporting register */
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232 | dbda808a | bellard | /* Source registers */
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233 | c227f099 | Anthony Liguori | IRQ_src_t src[MAX_IRQ]; |
234 | dbda808a | bellard | /* Local registers per output pin */
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235 | c227f099 | Anthony Liguori | IRQ_dst_t dst[MAX_CPU]; |
236 | dbda808a | bellard | int nb_cpus;
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237 | dbda808a | bellard | /* Timer registers */
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238 | dbda808a | bellard | struct {
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239 | 060fbfe1 | Aurelien Jarno | uint32_t ticc; /* Global timer current count register */
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240 | 060fbfe1 | Aurelien Jarno | uint32_t tibc; /* Global timer base count register */
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241 | dbda808a | bellard | } timers[MAX_TMR]; |
242 | dbda808a | bellard | #if MAX_DBL > 0 |
243 | dbda808a | bellard | /* Doorbell registers */
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244 | dbda808a | bellard | uint32_t dar; /* Doorbell activate register */
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245 | dbda808a | bellard | struct {
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246 | 060fbfe1 | Aurelien Jarno | uint32_t dmr; /* Doorbell messaging register */
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247 | dbda808a | bellard | } doorbells[MAX_DBL]; |
248 | dbda808a | bellard | #endif
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249 | dbda808a | bellard | #if MAX_MBX > 0 |
250 | dbda808a | bellard | /* Mailbox registers */
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251 | dbda808a | bellard | struct {
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252 | 060fbfe1 | Aurelien Jarno | uint32_t mbr; /* Mailbox register */
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253 | dbda808a | bellard | } mailboxes[MAX_MAILBOXES]; |
254 | dbda808a | bellard | #endif
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255 | e9df014c | j_mayer | /* IRQ out is used when in bypass mode (not implemented) */
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256 | e9df014c | j_mayer | qemu_irq irq_out; |
257 | b7169916 | aurel32 | int max_irq;
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258 | b7169916 | aurel32 | int irq_ipi0;
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259 | b7169916 | aurel32 | int irq_tim0;
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260 | b7169916 | aurel32 | void (*reset) (void *); |
261 | c227f099 | Anthony Liguori | void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); |
262 | c227f099 | Anthony Liguori | } openpic_t; |
263 | dbda808a | bellard | |
264 | c227f099 | Anthony Liguori | static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
265 | dbda808a | bellard | { |
266 | dbda808a | bellard | set_bit(q->queue, n_IRQ); |
267 | dbda808a | bellard | } |
268 | dbda808a | bellard | |
269 | c227f099 | Anthony Liguori | static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
270 | dbda808a | bellard | { |
271 | dbda808a | bellard | reset_bit(q->queue, n_IRQ); |
272 | dbda808a | bellard | } |
273 | dbda808a | bellard | |
274 | c227f099 | Anthony Liguori | static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
275 | dbda808a | bellard | { |
276 | dbda808a | bellard | return test_bit(q->queue, n_IRQ);
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277 | dbda808a | bellard | } |
278 | dbda808a | bellard | |
279 | c227f099 | Anthony Liguori | static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
280 | dbda808a | bellard | { |
281 | dbda808a | bellard | int next, i;
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282 | dbda808a | bellard | int priority;
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283 | dbda808a | bellard | |
284 | dbda808a | bellard | next = -1;
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285 | dbda808a | bellard | priority = -1;
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286 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
287 | 060fbfe1 | Aurelien Jarno | if (IRQ_testbit(q, i)) {
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288 | 5fafdf24 | ths | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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289 | 611493d9 | bellard | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
290 | 060fbfe1 | Aurelien Jarno | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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291 | 060fbfe1 | Aurelien Jarno | next = i; |
292 | 060fbfe1 | Aurelien Jarno | priority = IPVP_PRIORITY(opp->src[i].ipvp); |
293 | 060fbfe1 | Aurelien Jarno | } |
294 | 060fbfe1 | Aurelien Jarno | } |
295 | dbda808a | bellard | } |
296 | dbda808a | bellard | q->next = next; |
297 | dbda808a | bellard | q->priority = priority; |
298 | dbda808a | bellard | } |
299 | dbda808a | bellard | |
300 | c227f099 | Anthony Liguori | static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
301 | dbda808a | bellard | { |
302 | dbda808a | bellard | if (q->next == -1) { |
303 | 611493d9 | bellard | /* XXX: optimize */
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304 | 060fbfe1 | Aurelien Jarno | IRQ_check(opp, q); |
305 | dbda808a | bellard | } |
306 | dbda808a | bellard | |
307 | dbda808a | bellard | return q->next;
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308 | dbda808a | bellard | } |
309 | dbda808a | bellard | |
310 | c227f099 | Anthony Liguori | static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
311 | dbda808a | bellard | { |
312 | c227f099 | Anthony Liguori | IRQ_dst_t *dst; |
313 | c227f099 | Anthony Liguori | IRQ_src_t *src; |
314 | dbda808a | bellard | int priority;
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315 | dbda808a | bellard | |
316 | dbda808a | bellard | dst = &opp->dst[n_CPU]; |
317 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
318 | dbda808a | bellard | priority = IPVP_PRIORITY(src->ipvp); |
319 | dbda808a | bellard | if (priority <= dst->pctp) {
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320 | 060fbfe1 | Aurelien Jarno | /* Too low priority */
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321 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
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322 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
323 | 060fbfe1 | Aurelien Jarno | return;
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324 | dbda808a | bellard | } |
325 | dbda808a | bellard | if (IRQ_testbit(&dst->raised, n_IRQ)) {
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326 | 060fbfe1 | Aurelien Jarno | /* Interrupt miss */
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327 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d was missed on CPU %d\n",
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328 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
329 | 060fbfe1 | Aurelien Jarno | return;
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330 | dbda808a | bellard | } |
331 | dbda808a | bellard | set_bit(&src->ipvp, IPVP_ACTIVITY); |
332 | dbda808a | bellard | IRQ_setbit(&dst->raised, n_IRQ); |
333 | e9df014c | j_mayer | if (priority < dst->raised.priority) {
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334 | e9df014c | j_mayer | /* An higher priority IRQ is already raised */
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335 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
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336 | e9df014c | j_mayer | __func__, n_IRQ, dst->raised.next, n_CPU); |
337 | e9df014c | j_mayer | return;
|
338 | e9df014c | j_mayer | } |
339 | e9df014c | j_mayer | IRQ_get_next(opp, &dst->raised); |
340 | e9df014c | j_mayer | if (IRQ_get_next(opp, &dst->servicing) != -1 && |
341 | 24865167 | aliguori | priority <= dst->servicing.priority) { |
342 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
|
343 | e9df014c | j_mayer | __func__, n_IRQ, dst->servicing.next, n_CPU); |
344 | e9df014c | j_mayer | /* Already servicing a higher priority IRQ */
|
345 | e9df014c | j_mayer | return;
|
346 | dbda808a | bellard | } |
347 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
|
348 | b7169916 | aurel32 | opp->irq_raise(opp, n_CPU, src); |
349 | dbda808a | bellard | } |
350 | dbda808a | bellard | |
351 | 611493d9 | bellard | /* update pic state because registers for n_IRQ have changed value */
|
352 | c227f099 | Anthony Liguori | static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
353 | dbda808a | bellard | { |
354 | c227f099 | Anthony Liguori | IRQ_src_t *src; |
355 | dbda808a | bellard | int i;
|
356 | dbda808a | bellard | |
357 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
358 | 611493d9 | bellard | |
359 | 611493d9 | bellard | if (!src->pending) {
|
360 | 611493d9 | bellard | /* no irq pending */
|
361 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
|
362 | 611493d9 | bellard | return;
|
363 | 611493d9 | bellard | } |
364 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_MASK)) {
|
365 | 060fbfe1 | Aurelien Jarno | /* Interrupt source is disabled */
|
366 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
|
367 | 060fbfe1 | Aurelien Jarno | return;
|
368 | dbda808a | bellard | } |
369 | dbda808a | bellard | if (IPVP_PRIORITY(src->ipvp) == 0) { |
370 | 060fbfe1 | Aurelien Jarno | /* Priority set to zero */
|
371 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
|
372 | 060fbfe1 | Aurelien Jarno | return;
|
373 | dbda808a | bellard | } |
374 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
|
375 | 611493d9 | bellard | /* IRQ already active */
|
376 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
|
377 | 611493d9 | bellard | return;
|
378 | 611493d9 | bellard | } |
379 | dbda808a | bellard | if (src->ide == 0x00000000) { |
380 | 060fbfe1 | Aurelien Jarno | /* No target */
|
381 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
|
382 | 060fbfe1 | Aurelien Jarno | return;
|
383 | dbda808a | bellard | } |
384 | 611493d9 | bellard | |
385 | e9df014c | j_mayer | if (src->ide == (1 << src->last_cpu)) { |
386 | e9df014c | j_mayer | /* Only one CPU is allowed to receive this IRQ */
|
387 | e9df014c | j_mayer | IRQ_local_pipe(opp, src->last_cpu, n_IRQ); |
388 | e9df014c | j_mayer | } else if (!test_bit(&src->ipvp, IPVP_MODE)) { |
389 | 611493d9 | bellard | /* Directed delivery mode */
|
390 | 611493d9 | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
391 | 611493d9 | bellard | if (test_bit(&src->ide, i))
|
392 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
393 | 611493d9 | bellard | } |
394 | dbda808a | bellard | } else {
|
395 | 611493d9 | bellard | /* Distributed delivery mode */
|
396 | e9df014c | j_mayer | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
397 | e9df014c | j_mayer | if (i == opp->nb_cpus)
|
398 | 611493d9 | bellard | i = 0;
|
399 | 611493d9 | bellard | if (test_bit(&src->ide, i)) {
|
400 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
401 | 611493d9 | bellard | src->last_cpu = i; |
402 | 611493d9 | bellard | break;
|
403 | 611493d9 | bellard | } |
404 | 611493d9 | bellard | } |
405 | 611493d9 | bellard | } |
406 | 611493d9 | bellard | } |
407 | 611493d9 | bellard | |
408 | d537cf6c | pbrook | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
409 | 611493d9 | bellard | { |
410 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
411 | c227f099 | Anthony Liguori | IRQ_src_t *src; |
412 | 611493d9 | bellard | |
413 | 611493d9 | bellard | src = &opp->src[n_IRQ]; |
414 | 5fafdf24 | ths | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
|
415 | 611493d9 | bellard | n_IRQ, level, src->ipvp); |
416 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_SENSE)) {
|
417 | 611493d9 | bellard | /* level-sensitive irq */
|
418 | 611493d9 | bellard | src->pending = level; |
419 | 611493d9 | bellard | if (!level)
|
420 | 611493d9 | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
421 | 611493d9 | bellard | } else {
|
422 | 611493d9 | bellard | /* edge-sensitive irq */
|
423 | 611493d9 | bellard | if (level)
|
424 | 611493d9 | bellard | src->pending = 1;
|
425 | dbda808a | bellard | } |
426 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
427 | dbda808a | bellard | } |
428 | dbda808a | bellard | |
429 | 67b55785 | blueswir1 | static void openpic_reset (void *opaque) |
430 | dbda808a | bellard | { |
431 | c227f099 | Anthony Liguori | openpic_t *opp = (openpic_t *)opaque; |
432 | dbda808a | bellard | int i;
|
433 | dbda808a | bellard | |
434 | dbda808a | bellard | opp->glbc = 0x80000000;
|
435 | f8407028 | bellard | /* Initialise controller registers */
|
436 | b7169916 | aurel32 | opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
437 | dbda808a | bellard | opp->veni = VENI; |
438 | e9df014c | j_mayer | opp->pint = 0x00000000;
|
439 | dbda808a | bellard | opp->spve = 0x000000FF;
|
440 | dbda808a | bellard | opp->tifr = 0x003F7A00;
|
441 | dbda808a | bellard | /* ? */
|
442 | dbda808a | bellard | opp->micr = 0x00000000;
|
443 | dbda808a | bellard | /* Initialise IRQ sources */
|
444 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
445 | 060fbfe1 | Aurelien Jarno | opp->src[i].ipvp = 0xA0000000;
|
446 | 060fbfe1 | Aurelien Jarno | opp->src[i].ide = 0x00000000;
|
447 | dbda808a | bellard | } |
448 | dbda808a | bellard | /* Initialise IRQ destinations */
|
449 | e9df014c | j_mayer | for (i = 0; i < MAX_CPU; i++) { |
450 | 060fbfe1 | Aurelien Jarno | opp->dst[i].pctp = 0x0000000F;
|
451 | 060fbfe1 | Aurelien Jarno | opp->dst[i].pcsr = 0x00000000;
|
452 | 060fbfe1 | Aurelien Jarno | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
453 | d14ed254 | Alexander Graf | opp->dst[i].raised.next = -1;
|
454 | 060fbfe1 | Aurelien Jarno | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
455 | d14ed254 | Alexander Graf | opp->dst[i].servicing.next = -1;
|
456 | dbda808a | bellard | } |
457 | dbda808a | bellard | /* Initialise timers */
|
458 | dbda808a | bellard | for (i = 0; i < MAX_TMR; i++) { |
459 | 060fbfe1 | Aurelien Jarno | opp->timers[i].ticc = 0x00000000;
|
460 | 060fbfe1 | Aurelien Jarno | opp->timers[i].tibc = 0x80000000;
|
461 | dbda808a | bellard | } |
462 | dbda808a | bellard | /* Initialise doorbells */
|
463 | dbda808a | bellard | #if MAX_DBL > 0 |
464 | dbda808a | bellard | opp->dar = 0x00000000;
|
465 | dbda808a | bellard | for (i = 0; i < MAX_DBL; i++) { |
466 | 060fbfe1 | Aurelien Jarno | opp->doorbells[i].dmr = 0x00000000;
|
467 | dbda808a | bellard | } |
468 | dbda808a | bellard | #endif
|
469 | dbda808a | bellard | /* Initialise mailboxes */
|
470 | dbda808a | bellard | #if MAX_MBX > 0 |
471 | dbda808a | bellard | for (i = 0; i < MAX_MBX; i++) { /* ? */ |
472 | 060fbfe1 | Aurelien Jarno | opp->mailboxes[i].mbr = 0x00000000;
|
473 | dbda808a | bellard | } |
474 | dbda808a | bellard | #endif
|
475 | dbda808a | bellard | /* Go out of RESET state */
|
476 | dbda808a | bellard | opp->glbc = 0x00000000;
|
477 | dbda808a | bellard | } |
478 | dbda808a | bellard | |
479 | 8d3a8c1e | Alexander Graf | static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ) |
480 | dbda808a | bellard | { |
481 | 8d3a8c1e | Alexander Graf | return opp->src[n_IRQ].ide;
|
482 | 8d3a8c1e | Alexander Graf | } |
483 | dbda808a | bellard | |
484 | 8d3a8c1e | Alexander Graf | static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ) |
485 | 8d3a8c1e | Alexander Graf | { |
486 | 8d3a8c1e | Alexander Graf | return opp->src[n_IRQ].ipvp;
|
487 | dbda808a | bellard | } |
488 | dbda808a | bellard | |
489 | 11de8b71 | Alexander Graf | static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val) |
490 | dbda808a | bellard | { |
491 | dbda808a | bellard | uint32_t tmp; |
492 | dbda808a | bellard | |
493 | 11de8b71 | Alexander Graf | tmp = val & 0xC0000000;
|
494 | 11de8b71 | Alexander Graf | tmp |= val & ((1ULL << MAX_CPU) - 1); |
495 | 11de8b71 | Alexander Graf | opp->src[n_IRQ].ide = tmp; |
496 | 11de8b71 | Alexander Graf | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
497 | 11de8b71 | Alexander Graf | } |
498 | 11de8b71 | Alexander Graf | |
499 | 11de8b71 | Alexander Graf | static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val) |
500 | 11de8b71 | Alexander Graf | { |
501 | 11de8b71 | Alexander Graf | /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
|
502 | 11de8b71 | Alexander Graf | /* ACTIVITY bit is read-only */
|
503 | 11de8b71 | Alexander Graf | opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000)
|
504 | 11de8b71 | Alexander Graf | | (val & 0x800F00FF);
|
505 | 11de8b71 | Alexander Graf | openpic_update_irq(opp, n_IRQ); |
506 | 11de8b71 | Alexander Graf | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
|
507 | 11de8b71 | Alexander Graf | opp->src[n_IRQ].ipvp); |
508 | dbda808a | bellard | } |
509 | dbda808a | bellard | |
510 | dbda808a | bellard | #if 0 // Code provision for Intel model
|
511 | dbda808a | bellard | #if MAX_DBL > 0
|
512 | c227f099 | Anthony Liguori | static uint32_t read_doorbell_register (openpic_t *opp,
|
513 | 060fbfe1 | Aurelien Jarno | int n_dbl, uint32_t offset)
|
514 | dbda808a | bellard | {
|
515 | dbda808a | bellard | uint32_t retval;
|
516 | dbda808a | bellard | |
517 | dbda808a | bellard | switch (offset) {
|
518 | dbda808a | bellard | case DBL_IPVP_OFFSET:
|
519 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
|
520 | 060fbfe1 | Aurelien Jarno | break;
|
521 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
522 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
|
523 | 060fbfe1 | Aurelien Jarno | break;
|
524 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
525 | 060fbfe1 | Aurelien Jarno | retval = opp->doorbells[n_dbl].dmr;
|
526 | 060fbfe1 | Aurelien Jarno | break;
|
527 | dbda808a | bellard | }
|
528 | dbda808a | bellard | |
529 | dbda808a | bellard | return retval;
|
530 | dbda808a | bellard | }
|
531 | 3b46e624 | ths | |
532 | dbda808a | bellard | static void write_doorbell_register (penpic_t *opp, int n_dbl,
|
533 | 060fbfe1 | Aurelien Jarno | uint32_t offset, uint32_t value)
|
534 | dbda808a | bellard | {
|
535 | dbda808a | bellard | switch (offset) {
|
536 | dbda808a | bellard | case DBL_IVPR_OFFSET:
|
537 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
|
538 | 060fbfe1 | Aurelien Jarno | break;
|
539 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
540 | 11de8b71 | Alexander Graf | write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
|
541 | 060fbfe1 | Aurelien Jarno | break;
|
542 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
543 | 060fbfe1 | Aurelien Jarno | opp->doorbells[n_dbl].dmr = value;
|
544 | 060fbfe1 | Aurelien Jarno | break;
|
545 | dbda808a | bellard | }
|
546 | dbda808a | bellard | }
|
547 | dbda808a | bellard | #endif
|
548 | dbda808a | bellard | |
549 | dbda808a | bellard | #if MAX_MBX > 0 |
550 | c227f099 | Anthony Liguori | static uint32_t read_mailbox_register (openpic_t *opp,
|
551 | 060fbfe1 | Aurelien Jarno | int n_mbx, uint32_t offset)
|
552 | dbda808a | bellard | { |
553 | dbda808a | bellard | uint32_t retval; |
554 | dbda808a | bellard | |
555 | dbda808a | bellard | switch (offset) {
|
556 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
557 | 060fbfe1 | Aurelien Jarno | retval = opp->mailboxes[n_mbx].mbr; |
558 | 060fbfe1 | Aurelien Jarno | break;
|
559 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
560 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx); |
561 | 060fbfe1 | Aurelien Jarno | break;
|
562 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
563 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx); |
564 | 060fbfe1 | Aurelien Jarno | break;
|
565 | dbda808a | bellard | } |
566 | dbda808a | bellard | |
567 | dbda808a | bellard | return retval;
|
568 | dbda808a | bellard | } |
569 | dbda808a | bellard | |
570 | c227f099 | Anthony Liguori | static void write_mailbox_register (openpic_t *opp, int n_mbx, |
571 | 060fbfe1 | Aurelien Jarno | uint32_t address, uint32_t value) |
572 | dbda808a | bellard | { |
573 | dbda808a | bellard | switch (offset) {
|
574 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
575 | 060fbfe1 | Aurelien Jarno | opp->mailboxes[n_mbx].mbr = value; |
576 | 060fbfe1 | Aurelien Jarno | break;
|
577 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
578 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value); |
579 | 060fbfe1 | Aurelien Jarno | break;
|
580 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
581 | 11de8b71 | Alexander Graf | write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value); |
582 | 060fbfe1 | Aurelien Jarno | break;
|
583 | dbda808a | bellard | } |
584 | dbda808a | bellard | } |
585 | dbda808a | bellard | #endif
|
586 | dbda808a | bellard | #endif /* 0 : Code provision for Intel model */ |
587 | dbda808a | bellard | |
588 | c227f099 | Anthony Liguori | static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
589 | dbda808a | bellard | { |
590 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
591 | c227f099 | Anthony Liguori | IRQ_dst_t *dst; |
592 | e9df014c | j_mayer | int idx;
|
593 | dbda808a | bellard | |
594 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
595 | dbda808a | bellard | if (addr & 0xF) |
596 | dbda808a | bellard | return;
|
597 | dbda808a | bellard | switch (addr) {
|
598 | 704c7e5d | Alexander Graf | case 0x40: |
599 | 704c7e5d | Alexander Graf | case 0x50: |
600 | 704c7e5d | Alexander Graf | case 0x60: |
601 | 704c7e5d | Alexander Graf | case 0x70: |
602 | 704c7e5d | Alexander Graf | case 0x80: |
603 | 704c7e5d | Alexander Graf | case 0x90: |
604 | 704c7e5d | Alexander Graf | case 0xA0: |
605 | 704c7e5d | Alexander Graf | case 0xB0: |
606 | 704c7e5d | Alexander Graf | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); |
607 | dbda808a | bellard | break;
|
608 | 704c7e5d | Alexander Graf | case 0x1000: /* FREP */ |
609 | dbda808a | bellard | break;
|
610 | 704c7e5d | Alexander Graf | case 0x1020: /* GLBC */ |
611 | b7169916 | aurel32 | if (val & 0x80000000 && opp->reset) |
612 | b7169916 | aurel32 | opp->reset(opp); |
613 | dbda808a | bellard | opp->glbc = val & ~0x80000000;
|
614 | 060fbfe1 | Aurelien Jarno | break;
|
615 | 704c7e5d | Alexander Graf | case 0x1080: /* VENI */ |
616 | 060fbfe1 | Aurelien Jarno | break;
|
617 | 704c7e5d | Alexander Graf | case 0x1090: /* PINT */ |
618 | e9df014c | j_mayer | for (idx = 0; idx < opp->nb_cpus; idx++) { |
619 | e9df014c | j_mayer | if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { |
620 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
|
621 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
622 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
623 | e9df014c | j_mayer | } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { |
624 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
|
625 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
626 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
627 | e9df014c | j_mayer | } |
628 | dbda808a | bellard | } |
629 | e9df014c | j_mayer | opp->pint = val; |
630 | 060fbfe1 | Aurelien Jarno | break;
|
631 | 704c7e5d | Alexander Graf | case 0x10A0: /* IPI_IPVP */ |
632 | 704c7e5d | Alexander Graf | case 0x10B0: |
633 | 704c7e5d | Alexander Graf | case 0x10C0: |
634 | 704c7e5d | Alexander Graf | case 0x10D0: |
635 | dbda808a | bellard | { |
636 | dbda808a | bellard | int idx;
|
637 | 704c7e5d | Alexander Graf | idx = (addr - 0x10A0) >> 4; |
638 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val); |
639 | dbda808a | bellard | } |
640 | dbda808a | bellard | break;
|
641 | 704c7e5d | Alexander Graf | case 0x10E0: /* SPVE */ |
642 | dbda808a | bellard | opp->spve = val & 0x000000FF;
|
643 | dbda808a | bellard | break;
|
644 | 704c7e5d | Alexander Graf | case 0x10F0: /* TIFR */ |
645 | dbda808a | bellard | opp->tifr = val; |
646 | 060fbfe1 | Aurelien Jarno | break;
|
647 | dbda808a | bellard | default:
|
648 | dbda808a | bellard | break;
|
649 | dbda808a | bellard | } |
650 | dbda808a | bellard | } |
651 | dbda808a | bellard | |
652 | c227f099 | Anthony Liguori | static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr) |
653 | dbda808a | bellard | { |
654 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
655 | dbda808a | bellard | uint32_t retval; |
656 | dbda808a | bellard | |
657 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
658 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
659 | dbda808a | bellard | if (addr & 0xF) |
660 | dbda808a | bellard | return retval;
|
661 | dbda808a | bellard | switch (addr) {
|
662 | 704c7e5d | Alexander Graf | case 0x1000: /* FREP */ |
663 | dbda808a | bellard | retval = opp->frep; |
664 | dbda808a | bellard | break;
|
665 | 704c7e5d | Alexander Graf | case 0x1020: /* GLBC */ |
666 | dbda808a | bellard | retval = opp->glbc; |
667 | 060fbfe1 | Aurelien Jarno | break;
|
668 | 704c7e5d | Alexander Graf | case 0x1080: /* VENI */ |
669 | dbda808a | bellard | retval = opp->veni; |
670 | 060fbfe1 | Aurelien Jarno | break;
|
671 | 704c7e5d | Alexander Graf | case 0x1090: /* PINT */ |
672 | dbda808a | bellard | retval = 0x00000000;
|
673 | 060fbfe1 | Aurelien Jarno | break;
|
674 | 704c7e5d | Alexander Graf | case 0x40: |
675 | 704c7e5d | Alexander Graf | case 0x50: |
676 | 704c7e5d | Alexander Graf | case 0x60: |
677 | 704c7e5d | Alexander Graf | case 0x70: |
678 | 704c7e5d | Alexander Graf | case 0x80: |
679 | 704c7e5d | Alexander Graf | case 0x90: |
680 | 704c7e5d | Alexander Graf | case 0xA0: |
681 | dbda808a | bellard | case 0xB0: |
682 | 704c7e5d | Alexander Graf | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
683 | 704c7e5d | Alexander Graf | break;
|
684 | 704c7e5d | Alexander Graf | case 0x10A0: /* IPI_IPVP */ |
685 | 704c7e5d | Alexander Graf | case 0x10B0: |
686 | 704c7e5d | Alexander Graf | case 0x10C0: |
687 | 704c7e5d | Alexander Graf | case 0x10D0: |
688 | dbda808a | bellard | { |
689 | dbda808a | bellard | int idx;
|
690 | 704c7e5d | Alexander Graf | idx = (addr - 0x10A0) >> 4; |
691 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx); |
692 | dbda808a | bellard | } |
693 | 060fbfe1 | Aurelien Jarno | break;
|
694 | 704c7e5d | Alexander Graf | case 0x10E0: /* SPVE */ |
695 | dbda808a | bellard | retval = opp->spve; |
696 | dbda808a | bellard | break;
|
697 | 704c7e5d | Alexander Graf | case 0x10F0: /* TIFR */ |
698 | dbda808a | bellard | retval = opp->tifr; |
699 | 060fbfe1 | Aurelien Jarno | break;
|
700 | dbda808a | bellard | default:
|
701 | dbda808a | bellard | break;
|
702 | dbda808a | bellard | } |
703 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
704 | dbda808a | bellard | |
705 | dbda808a | bellard | return retval;
|
706 | dbda808a | bellard | } |
707 | dbda808a | bellard | |
708 | dbda808a | bellard | static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
709 | dbda808a | bellard | { |
710 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
711 | dbda808a | bellard | int idx;
|
712 | dbda808a | bellard | |
713 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
714 | dbda808a | bellard | if (addr & 0xF) |
715 | dbda808a | bellard | return;
|
716 | 38ae51a8 | Alexander Graf | addr -= 0x10;
|
717 | dbda808a | bellard | addr &= 0xFFFF;
|
718 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
719 | dbda808a | bellard | addr = addr & 0x30;
|
720 | dbda808a | bellard | switch (addr) {
|
721 | dbda808a | bellard | case 0x00: /* TICC */ |
722 | dbda808a | bellard | break;
|
723 | dbda808a | bellard | case 0x10: /* TIBC */ |
724 | 060fbfe1 | Aurelien Jarno | if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
725 | 060fbfe1 | Aurelien Jarno | (val & 0x80000000) == 0 && |
726 | dbda808a | bellard | (opp->timers[idx].tibc & 0x80000000) != 0) |
727 | 060fbfe1 | Aurelien Jarno | opp->timers[idx].ticc &= ~0x80000000;
|
728 | 060fbfe1 | Aurelien Jarno | opp->timers[idx].tibc = val; |
729 | 060fbfe1 | Aurelien Jarno | break;
|
730 | dbda808a | bellard | case 0x20: /* TIVP */ |
731 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val); |
732 | 060fbfe1 | Aurelien Jarno | break;
|
733 | dbda808a | bellard | case 0x30: /* TIDE */ |
734 | 11de8b71 | Alexander Graf | write_IRQreg_ide(opp, opp->irq_tim0 + idx, val); |
735 | 060fbfe1 | Aurelien Jarno | break;
|
736 | dbda808a | bellard | } |
737 | dbda808a | bellard | } |
738 | dbda808a | bellard | |
739 | dbda808a | bellard | static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
740 | dbda808a | bellard | { |
741 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
742 | dbda808a | bellard | uint32_t retval; |
743 | dbda808a | bellard | int idx;
|
744 | dbda808a | bellard | |
745 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
746 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
747 | dbda808a | bellard | if (addr & 0xF) |
748 | dbda808a | bellard | return retval;
|
749 | 38ae51a8 | Alexander Graf | addr -= 0x10;
|
750 | dbda808a | bellard | addr &= 0xFFFF;
|
751 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
752 | dbda808a | bellard | addr = addr & 0x30;
|
753 | dbda808a | bellard | switch (addr) {
|
754 | dbda808a | bellard | case 0x00: /* TICC */ |
755 | 060fbfe1 | Aurelien Jarno | retval = opp->timers[idx].ticc; |
756 | dbda808a | bellard | break;
|
757 | dbda808a | bellard | case 0x10: /* TIBC */ |
758 | 060fbfe1 | Aurelien Jarno | retval = opp->timers[idx].tibc; |
759 | 060fbfe1 | Aurelien Jarno | break;
|
760 | dbda808a | bellard | case 0x20: /* TIPV */ |
761 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx); |
762 | 060fbfe1 | Aurelien Jarno | break;
|
763 | dbda808a | bellard | case 0x30: /* TIDE */ |
764 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx); |
765 | 060fbfe1 | Aurelien Jarno | break;
|
766 | dbda808a | bellard | } |
767 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
768 | dbda808a | bellard | |
769 | dbda808a | bellard | return retval;
|
770 | dbda808a | bellard | } |
771 | dbda808a | bellard | |
772 | dbda808a | bellard | static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
773 | dbda808a | bellard | { |
774 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
775 | dbda808a | bellard | int idx;
|
776 | dbda808a | bellard | |
777 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
778 | dbda808a | bellard | if (addr & 0xF) |
779 | dbda808a | bellard | return;
|
780 | dbda808a | bellard | addr = addr & 0xFFF0;
|
781 | dbda808a | bellard | idx = addr >> 5;
|
782 | dbda808a | bellard | if (addr & 0x10) { |
783 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
784 | 11de8b71 | Alexander Graf | write_IRQreg_ide(opp, idx, val); |
785 | dbda808a | bellard | } else {
|
786 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
787 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(opp, idx, val); |
788 | dbda808a | bellard | } |
789 | dbda808a | bellard | } |
790 | dbda808a | bellard | |
791 | dbda808a | bellard | static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
792 | dbda808a | bellard | { |
793 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
794 | dbda808a | bellard | uint32_t retval; |
795 | dbda808a | bellard | int idx;
|
796 | dbda808a | bellard | |
797 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
798 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
799 | dbda808a | bellard | if (addr & 0xF) |
800 | dbda808a | bellard | return retval;
|
801 | dbda808a | bellard | addr = addr & 0xFFF0;
|
802 | dbda808a | bellard | idx = addr >> 5;
|
803 | dbda808a | bellard | if (addr & 0x10) { |
804 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
805 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(opp, idx); |
806 | dbda808a | bellard | } else {
|
807 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
808 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(opp, idx); |
809 | dbda808a | bellard | } |
810 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
811 | dbda808a | bellard | |
812 | dbda808a | bellard | return retval;
|
813 | dbda808a | bellard | } |
814 | dbda808a | bellard | |
815 | 704c7e5d | Alexander Graf | static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr, |
816 | 704c7e5d | Alexander Graf | uint32_t val, int idx)
|
817 | dbda808a | bellard | { |
818 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
819 | c227f099 | Anthony Liguori | IRQ_src_t *src; |
820 | c227f099 | Anthony Liguori | IRQ_dst_t *dst; |
821 | 704c7e5d | Alexander Graf | int s_IRQ, n_IRQ;
|
822 | dbda808a | bellard | |
823 | 704c7e5d | Alexander Graf | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx, |
824 | 704c7e5d | Alexander Graf | addr, val); |
825 | dbda808a | bellard | if (addr & 0xF) |
826 | dbda808a | bellard | return;
|
827 | dbda808a | bellard | dst = &opp->dst[idx]; |
828 | dbda808a | bellard | addr &= 0xFF0;
|
829 | dbda808a | bellard | switch (addr) {
|
830 | dbda808a | bellard | #if MAX_IPI > 0 |
831 | 704c7e5d | Alexander Graf | case 0x40: /* IPIDR */ |
832 | dbda808a | bellard | case 0x50: |
833 | dbda808a | bellard | case 0x60: |
834 | dbda808a | bellard | case 0x70: |
835 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
836 | a675155e | Alexander Graf | /* we use IDE as mask which CPUs to deliver the IPI to still. */
|
837 | 11de8b71 | Alexander Graf | write_IRQreg_ide(opp, opp->irq_ipi0 + idx, |
838 | 11de8b71 | Alexander Graf | opp->src[opp->irq_ipi0 + idx].ide | val); |
839 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
|
840 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
|
841 | dbda808a | bellard | break;
|
842 | dbda808a | bellard | #endif
|
843 | dbda808a | bellard | case 0x80: /* PCTP */ |
844 | 060fbfe1 | Aurelien Jarno | dst->pctp = val & 0x0000000F;
|
845 | 060fbfe1 | Aurelien Jarno | break;
|
846 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
847 | 060fbfe1 | Aurelien Jarno | /* Read-only register */
|
848 | 060fbfe1 | Aurelien Jarno | break;
|
849 | dbda808a | bellard | case 0xA0: /* PIAC */ |
850 | 060fbfe1 | Aurelien Jarno | /* Read-only register */
|
851 | 060fbfe1 | Aurelien Jarno | break;
|
852 | dbda808a | bellard | case 0xB0: /* PEOI */ |
853 | dbda808a | bellard | DPRINTF("PEOI\n");
|
854 | 060fbfe1 | Aurelien Jarno | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
855 | 060fbfe1 | Aurelien Jarno | IRQ_resetbit(&dst->servicing, s_IRQ); |
856 | 060fbfe1 | Aurelien Jarno | dst->servicing.next = -1;
|
857 | 060fbfe1 | Aurelien Jarno | /* Set up next servicing IRQ */
|
858 | 060fbfe1 | Aurelien Jarno | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
859 | e9df014c | j_mayer | /* Check queued interrupts. */
|
860 | e9df014c | j_mayer | n_IRQ = IRQ_get_next(opp, &dst->raised); |
861 | e9df014c | j_mayer | src = &opp->src[n_IRQ]; |
862 | e9df014c | j_mayer | if (n_IRQ != -1 && |
863 | e9df014c | j_mayer | (s_IRQ == -1 ||
|
864 | e9df014c | j_mayer | IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { |
865 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
866 | e9df014c | j_mayer | idx, n_IRQ); |
867 | b7169916 | aurel32 | opp->irq_raise(opp, idx, src); |
868 | e9df014c | j_mayer | } |
869 | 060fbfe1 | Aurelien Jarno | break;
|
870 | dbda808a | bellard | default:
|
871 | dbda808a | bellard | break;
|
872 | dbda808a | bellard | } |
873 | dbda808a | bellard | } |
874 | dbda808a | bellard | |
875 | 704c7e5d | Alexander Graf | static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val) |
876 | 704c7e5d | Alexander Graf | { |
877 | 704c7e5d | Alexander Graf | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); |
878 | 704c7e5d | Alexander Graf | } |
879 | 704c7e5d | Alexander Graf | |
880 | 704c7e5d | Alexander Graf | static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr, |
881 | 704c7e5d | Alexander Graf | int idx)
|
882 | dbda808a | bellard | { |
883 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
884 | c227f099 | Anthony Liguori | IRQ_src_t *src; |
885 | c227f099 | Anthony Liguori | IRQ_dst_t *dst; |
886 | dbda808a | bellard | uint32_t retval; |
887 | 704c7e5d | Alexander Graf | int n_IRQ;
|
888 | 3b46e624 | ths | |
889 | 704c7e5d | Alexander Graf | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr); |
890 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
891 | dbda808a | bellard | if (addr & 0xF) |
892 | dbda808a | bellard | return retval;
|
893 | dbda808a | bellard | dst = &opp->dst[idx]; |
894 | dbda808a | bellard | addr &= 0xFF0;
|
895 | dbda808a | bellard | switch (addr) {
|
896 | dbda808a | bellard | case 0x80: /* PCTP */ |
897 | 060fbfe1 | Aurelien Jarno | retval = dst->pctp; |
898 | 060fbfe1 | Aurelien Jarno | break;
|
899 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
900 | 060fbfe1 | Aurelien Jarno | retval = idx; |
901 | 060fbfe1 | Aurelien Jarno | break;
|
902 | dbda808a | bellard | case 0xA0: /* PIAC */ |
903 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC INT output\n");
|
904 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
905 | 060fbfe1 | Aurelien Jarno | n_IRQ = IRQ_get_next(opp, &dst->raised); |
906 | dbda808a | bellard | DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
907 | 060fbfe1 | Aurelien Jarno | if (n_IRQ == -1) { |
908 | 060fbfe1 | Aurelien Jarno | /* No more interrupt pending */
|
909 | e9df014c | j_mayer | retval = IPVP_VECTOR(opp->spve); |
910 | 060fbfe1 | Aurelien Jarno | } else {
|
911 | 060fbfe1 | Aurelien Jarno | src = &opp->src[n_IRQ]; |
912 | 060fbfe1 | Aurelien Jarno | if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
913 | 060fbfe1 | Aurelien Jarno | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
914 | 060fbfe1 | Aurelien Jarno | /* - Spurious level-sensitive IRQ
|
915 | 060fbfe1 | Aurelien Jarno | * - Priorities has been changed
|
916 | 060fbfe1 | Aurelien Jarno | * and the pending IRQ isn't allowed anymore
|
917 | 060fbfe1 | Aurelien Jarno | */
|
918 | 060fbfe1 | Aurelien Jarno | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
919 | 060fbfe1 | Aurelien Jarno | retval = IPVP_VECTOR(opp->spve); |
920 | 060fbfe1 | Aurelien Jarno | } else {
|
921 | 060fbfe1 | Aurelien Jarno | /* IRQ enter servicing state */
|
922 | 060fbfe1 | Aurelien Jarno | IRQ_setbit(&dst->servicing, n_IRQ); |
923 | 060fbfe1 | Aurelien Jarno | retval = IPVP_VECTOR(src->ipvp); |
924 | 060fbfe1 | Aurelien Jarno | } |
925 | 060fbfe1 | Aurelien Jarno | IRQ_resetbit(&dst->raised, n_IRQ); |
926 | 060fbfe1 | Aurelien Jarno | dst->raised.next = -1;
|
927 | 060fbfe1 | Aurelien Jarno | if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
928 | 611493d9 | bellard | /* edge-sensitive IRQ */
|
929 | 060fbfe1 | Aurelien Jarno | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
930 | 611493d9 | bellard | src->pending = 0;
|
931 | 611493d9 | bellard | } |
932 | a675155e | Alexander Graf | |
933 | a675155e | Alexander Graf | if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) {
|
934 | a675155e | Alexander Graf | src->ide &= ~(1 << idx);
|
935 | a675155e | Alexander Graf | if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
|
936 | a675155e | Alexander Graf | /* trigger on CPUs that didn't know about it yet */
|
937 | a675155e | Alexander Graf | openpic_set_irq(opp, n_IRQ, 1);
|
938 | a675155e | Alexander Graf | openpic_set_irq(opp, n_IRQ, 0);
|
939 | a675155e | Alexander Graf | /* if all CPUs knew about it, set active bit again */
|
940 | a675155e | Alexander Graf | set_bit(&src->ipvp, IPVP_ACTIVITY); |
941 | a675155e | Alexander Graf | } |
942 | a675155e | Alexander Graf | } |
943 | 060fbfe1 | Aurelien Jarno | } |
944 | 060fbfe1 | Aurelien Jarno | break;
|
945 | dbda808a | bellard | case 0xB0: /* PEOI */ |
946 | 060fbfe1 | Aurelien Jarno | retval = 0;
|
947 | 060fbfe1 | Aurelien Jarno | break;
|
948 | dbda808a | bellard | default:
|
949 | dbda808a | bellard | break;
|
950 | dbda808a | bellard | } |
951 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
952 | dbda808a | bellard | |
953 | dbda808a | bellard | return retval;
|
954 | dbda808a | bellard | } |
955 | dbda808a | bellard | |
956 | 704c7e5d | Alexander Graf | static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr) |
957 | 704c7e5d | Alexander Graf | { |
958 | 704c7e5d | Alexander Graf | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); |
959 | 704c7e5d | Alexander Graf | } |
960 | 704c7e5d | Alexander Graf | |
961 | dbda808a | bellard | static void openpic_buggy_write (void *opaque, |
962 | c227f099 | Anthony Liguori | target_phys_addr_t addr, uint32_t val) |
963 | dbda808a | bellard | { |
964 | dbda808a | bellard | printf("Invalid OPENPIC write access !\n");
|
965 | dbda808a | bellard | } |
966 | dbda808a | bellard | |
967 | c227f099 | Anthony Liguori | static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
968 | dbda808a | bellard | { |
969 | dbda808a | bellard | printf("Invalid OPENPIC read access !\n");
|
970 | dbda808a | bellard | |
971 | dbda808a | bellard | return -1; |
972 | dbda808a | bellard | } |
973 | dbda808a | bellard | |
974 | dbda808a | bellard | static void openpic_writel (void *opaque, |
975 | c227f099 | Anthony Liguori | target_phys_addr_t addr, uint32_t val) |
976 | dbda808a | bellard | { |
977 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
978 | dbda808a | bellard | |
979 | dbda808a | bellard | addr &= 0x3FFFF;
|
980 | 611493d9 | bellard | DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
981 | dbda808a | bellard | if (addr < 0x1100) { |
982 | dbda808a | bellard | /* Global registers */
|
983 | dbda808a | bellard | openpic_gbl_write(opp, addr, val); |
984 | dbda808a | bellard | } else if (addr < 0x10000) { |
985 | dbda808a | bellard | /* Timers registers */
|
986 | dbda808a | bellard | openpic_timer_write(opp, addr, val); |
987 | dbda808a | bellard | } else if (addr < 0x20000) { |
988 | dbda808a | bellard | /* Source registers */
|
989 | dbda808a | bellard | openpic_src_write(opp, addr, val); |
990 | dbda808a | bellard | } else {
|
991 | dbda808a | bellard | /* CPU registers */
|
992 | dbda808a | bellard | openpic_cpu_write(opp, addr, val); |
993 | dbda808a | bellard | } |
994 | dbda808a | bellard | } |
995 | dbda808a | bellard | |
996 | c227f099 | Anthony Liguori | static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
997 | dbda808a | bellard | { |
998 | c227f099 | Anthony Liguori | openpic_t *opp = opaque; |
999 | dbda808a | bellard | uint32_t retval; |
1000 | dbda808a | bellard | |
1001 | dbda808a | bellard | addr &= 0x3FFFF;
|
1002 | 611493d9 | bellard | DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
1003 | dbda808a | bellard | if (addr < 0x1100) { |
1004 | dbda808a | bellard | /* Global registers */
|
1005 | dbda808a | bellard | retval = openpic_gbl_read(opp, addr); |
1006 | dbda808a | bellard | } else if (addr < 0x10000) { |
1007 | dbda808a | bellard | /* Timers registers */
|
1008 | dbda808a | bellard | retval = openpic_timer_read(opp, addr); |
1009 | dbda808a | bellard | } else if (addr < 0x20000) { |
1010 | dbda808a | bellard | /* Source registers */
|
1011 | dbda808a | bellard | retval = openpic_src_read(opp, addr); |
1012 | dbda808a | bellard | } else {
|
1013 | dbda808a | bellard | /* CPU registers */
|
1014 | dbda808a | bellard | retval = openpic_cpu_read(opp, addr); |
1015 | dbda808a | bellard | } |
1016 | dbda808a | bellard | |
1017 | dbda808a | bellard | return retval;
|
1018 | dbda808a | bellard | } |
1019 | dbda808a | bellard | |
1020 | 23c5e4ca | Avi Kivity | static uint64_t openpic_read(void *opaque, target_phys_addr_t addr, |
1021 | 23c5e4ca | Avi Kivity | unsigned size)
|
1022 | 23c5e4ca | Avi Kivity | { |
1023 | 23c5e4ca | Avi Kivity | openpic_t *opp = opaque; |
1024 | dbda808a | bellard | |
1025 | 23c5e4ca | Avi Kivity | switch (size) {
|
1026 | 23c5e4ca | Avi Kivity | case 4: return openpic_readl(opp, addr); |
1027 | 23c5e4ca | Avi Kivity | default: return openpic_buggy_read(opp, addr); |
1028 | 23c5e4ca | Avi Kivity | } |
1029 | 23c5e4ca | Avi Kivity | } |
1030 | dbda808a | bellard | |
1031 | 23c5e4ca | Avi Kivity | static void openpic_write(void *opaque, target_phys_addr_t addr, |
1032 | 23c5e4ca | Avi Kivity | uint64_t data, unsigned size)
|
1033 | dbda808a | bellard | { |
1034 | 23c5e4ca | Avi Kivity | openpic_t *opp = opaque; |
1035 | dbda808a | bellard | |
1036 | 23c5e4ca | Avi Kivity | switch (size) {
|
1037 | 23c5e4ca | Avi Kivity | case 4: return openpic_writel(opp, addr, data); |
1038 | 23c5e4ca | Avi Kivity | default: return openpic_buggy_write(opp, addr, data); |
1039 | 23c5e4ca | Avi Kivity | } |
1040 | dbda808a | bellard | } |
1041 | dbda808a | bellard | |
1042 | 23c5e4ca | Avi Kivity | static const MemoryRegionOps openpic_ops = { |
1043 | 23c5e4ca | Avi Kivity | .read = openpic_read, |
1044 | 23c5e4ca | Avi Kivity | .write = openpic_write, |
1045 | 23c5e4ca | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
1046 | 23c5e4ca | Avi Kivity | }; |
1047 | 23c5e4ca | Avi Kivity | |
1048 | c227f099 | Anthony Liguori | static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1049 | 67b55785 | blueswir1 | { |
1050 | 67b55785 | blueswir1 | unsigned int i; |
1051 | 67b55785 | blueswir1 | |
1052 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1053 | 67b55785 | blueswir1 | qemu_put_be32s(f, &q->queue[i]); |
1054 | 67b55785 | blueswir1 | |
1055 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->next); |
1056 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->priority); |
1057 | 67b55785 | blueswir1 | } |
1058 | 67b55785 | blueswir1 | |
1059 | 67b55785 | blueswir1 | static void openpic_save(QEMUFile* f, void *opaque) |
1060 | 67b55785 | blueswir1 | { |
1061 | c227f099 | Anthony Liguori | openpic_t *opp = (openpic_t *)opaque; |
1062 | 67b55785 | blueswir1 | unsigned int i; |
1063 | 67b55785 | blueswir1 | |
1064 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->frep); |
1065 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->glbc); |
1066 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->micr); |
1067 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->veni); |
1068 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->pint); |
1069 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->spve); |
1070 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->tifr); |
1071 | 67b55785 | blueswir1 | |
1072 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
1073 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ipvp); |
1074 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ide); |
1075 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].type); |
1076 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1077 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].pending); |
1078 | 67b55785 | blueswir1 | } |
1079 | 67b55785 | blueswir1 | |
1080 | b7169916 | aurel32 | qemu_put_sbe32s(f, &opp->nb_cpus); |
1081 | b7169916 | aurel32 | |
1082 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1083 | b7169916 | aurel32 | qemu_put_be32s(f, &opp->dst[i].tfrr); |
1084 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pctp); |
1085 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pcsr); |
1086 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1087 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); |
1088 | 67b55785 | blueswir1 | } |
1089 | 67b55785 | blueswir1 | |
1090 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1091 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].ticc); |
1092 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].tibc); |
1093 | 67b55785 | blueswir1 | } |
1094 | 67b55785 | blueswir1 | |
1095 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1096 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dar); |
1097 | 67b55785 | blueswir1 | |
1098 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1099 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->doorbells[i].dmr); |
1100 | 67b55785 | blueswir1 | } |
1101 | 67b55785 | blueswir1 | #endif
|
1102 | 67b55785 | blueswir1 | |
1103 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1104 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1105 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->mailboxes[i].mbr); |
1106 | 67b55785 | blueswir1 | } |
1107 | 67b55785 | blueswir1 | #endif
|
1108 | 67b55785 | blueswir1 | |
1109 | 67b55785 | blueswir1 | pci_device_save(&opp->pci_dev, f); |
1110 | 67b55785 | blueswir1 | } |
1111 | 67b55785 | blueswir1 | |
1112 | c227f099 | Anthony Liguori | static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1113 | 67b55785 | blueswir1 | { |
1114 | 67b55785 | blueswir1 | unsigned int i; |
1115 | 67b55785 | blueswir1 | |
1116 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1117 | 67b55785 | blueswir1 | qemu_get_be32s(f, &q->queue[i]); |
1118 | 67b55785 | blueswir1 | |
1119 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->next); |
1120 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->priority); |
1121 | 67b55785 | blueswir1 | } |
1122 | 67b55785 | blueswir1 | |
1123 | 67b55785 | blueswir1 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
1124 | 67b55785 | blueswir1 | { |
1125 | c227f099 | Anthony Liguori | openpic_t *opp = (openpic_t *)opaque; |
1126 | 67b55785 | blueswir1 | unsigned int i; |
1127 | 67b55785 | blueswir1 | |
1128 | 67b55785 | blueswir1 | if (version_id != 1) |
1129 | 67b55785 | blueswir1 | return -EINVAL;
|
1130 | 67b55785 | blueswir1 | |
1131 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->frep); |
1132 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->glbc); |
1133 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->micr); |
1134 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->veni); |
1135 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->pint); |
1136 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->spve); |
1137 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->tifr); |
1138 | 67b55785 | blueswir1 | |
1139 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
1140 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ipvp); |
1141 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ide); |
1142 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].type); |
1143 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1144 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].pending); |
1145 | 67b55785 | blueswir1 | } |
1146 | 67b55785 | blueswir1 | |
1147 | b7169916 | aurel32 | qemu_get_sbe32s(f, &opp->nb_cpus); |
1148 | b7169916 | aurel32 | |
1149 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1150 | b7169916 | aurel32 | qemu_get_be32s(f, &opp->dst[i].tfrr); |
1151 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pctp); |
1152 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pcsr); |
1153 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1154 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); |
1155 | 67b55785 | blueswir1 | } |
1156 | 67b55785 | blueswir1 | |
1157 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1158 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].ticc); |
1159 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].tibc); |
1160 | 67b55785 | blueswir1 | } |
1161 | 67b55785 | blueswir1 | |
1162 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1163 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dar); |
1164 | 67b55785 | blueswir1 | |
1165 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1166 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->doorbells[i].dmr); |
1167 | 67b55785 | blueswir1 | } |
1168 | 67b55785 | blueswir1 | #endif
|
1169 | 67b55785 | blueswir1 | |
1170 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1171 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1172 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->mailboxes[i].mbr); |
1173 | 67b55785 | blueswir1 | } |
1174 | 67b55785 | blueswir1 | #endif
|
1175 | 67b55785 | blueswir1 | |
1176 | 67b55785 | blueswir1 | return pci_device_load(&opp->pci_dev, f);
|
1177 | 67b55785 | blueswir1 | } |
1178 | 67b55785 | blueswir1 | |
1179 | c227f099 | Anthony Liguori | static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) |
1180 | b7169916 | aurel32 | { |
1181 | b7169916 | aurel32 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1182 | b7169916 | aurel32 | } |
1183 | b7169916 | aurel32 | |
1184 | 8a5faa1d | Anthony Liguori | qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
|
1185 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out) |
1186 | dbda808a | bellard | { |
1187 | c227f099 | Anthony Liguori | openpic_t *opp; |
1188 | dbda808a | bellard | int i, m;
|
1189 | 3b46e624 | ths | |
1190 | dbda808a | bellard | /* XXX: for now, only one CPU is supported */
|
1191 | dbda808a | bellard | if (nb_cpus != 1) |
1192 | dbda808a | bellard | return NULL; |
1193 | 8a5faa1d | Anthony Liguori | opp = g_malloc0(sizeof(openpic_t));
|
1194 | 8a5faa1d | Anthony Liguori | memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000); |
1195 | 3b46e624 | ths | |
1196 | 91d848eb | bellard | // isu_base &= 0xFFFC0000;
|
1197 | dbda808a | bellard | opp->nb_cpus = nb_cpus; |
1198 | b7169916 | aurel32 | opp->max_irq = OPENPIC_MAX_IRQ; |
1199 | b7169916 | aurel32 | opp->irq_ipi0 = OPENPIC_IRQ_IPI0; |
1200 | b7169916 | aurel32 | opp->irq_tim0 = OPENPIC_IRQ_TIM0; |
1201 | dbda808a | bellard | /* Set IRQ types */
|
1202 | b7169916 | aurel32 | for (i = 0; i < OPENPIC_EXT_IRQ; i++) { |
1203 | dbda808a | bellard | opp->src[i].type = IRQ_EXTERNAL; |
1204 | dbda808a | bellard | } |
1205 | b7169916 | aurel32 | for (; i < OPENPIC_IRQ_TIM0; i++) {
|
1206 | dbda808a | bellard | opp->src[i].type = IRQ_SPECIAL; |
1207 | dbda808a | bellard | } |
1208 | dbda808a | bellard | #if MAX_IPI > 0 |
1209 | b7169916 | aurel32 | m = OPENPIC_IRQ_IPI0; |
1210 | dbda808a | bellard | #else
|
1211 | b7169916 | aurel32 | m = OPENPIC_IRQ_DBL0; |
1212 | dbda808a | bellard | #endif
|
1213 | dbda808a | bellard | for (; i < m; i++) {
|
1214 | dbda808a | bellard | opp->src[i].type = IRQ_TIMER; |
1215 | dbda808a | bellard | } |
1216 | b7169916 | aurel32 | for (; i < OPENPIC_MAX_IRQ; i++) {
|
1217 | dbda808a | bellard | opp->src[i].type = IRQ_INTERNAL; |
1218 | dbda808a | bellard | } |
1219 | 7668a27f | bellard | for (i = 0; i < nb_cpus; i++) |
1220 | e9df014c | j_mayer | opp->dst[i].irqs = irqs[i]; |
1221 | e9df014c | j_mayer | opp->irq_out = irq_out; |
1222 | 67b55785 | blueswir1 | |
1223 | 0be71e32 | Alex Williamson | register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2, |
1224 | 0be71e32 | Alex Williamson | openpic_save, openpic_load, opp); |
1225 | a08d4367 | Jan Kiszka | qemu_register_reset(openpic_reset, opp); |
1226 | b7169916 | aurel32 | |
1227 | b7169916 | aurel32 | opp->irq_raise = openpic_irq_raise; |
1228 | b7169916 | aurel32 | opp->reset = openpic_reset; |
1229 | b7169916 | aurel32 | |
1230 | 23c5e4ca | Avi Kivity | if (pmem)
|
1231 | 23c5e4ca | Avi Kivity | *pmem = &opp->mem; |
1232 | e9df014c | j_mayer | |
1233 | b7169916 | aurel32 | return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
|
1234 | b7169916 | aurel32 | } |
1235 | b7169916 | aurel32 | |
1236 | c227f099 | Anthony Liguori | static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) |
1237 | b7169916 | aurel32 | { |
1238 | b7169916 | aurel32 | int n_ci = IDR_CI0 - n_CPU;
|
1239 | 0bf9e31a | Blue Swirl | |
1240 | b7169916 | aurel32 | if(test_bit(&src->ide, n_ci)) {
|
1241 | b7169916 | aurel32 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); |
1242 | b7169916 | aurel32 | } |
1243 | b7169916 | aurel32 | else {
|
1244 | b7169916 | aurel32 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1245 | b7169916 | aurel32 | } |
1246 | b7169916 | aurel32 | } |
1247 | b7169916 | aurel32 | |
1248 | b7169916 | aurel32 | static void mpic_reset (void *opaque) |
1249 | b7169916 | aurel32 | { |
1250 | c227f099 | Anthony Liguori | openpic_t *mpp = (openpic_t *)opaque; |
1251 | b7169916 | aurel32 | int i;
|
1252 | b7169916 | aurel32 | |
1253 | b7169916 | aurel32 | mpp->glbc = 0x80000000;
|
1254 | b7169916 | aurel32 | /* Initialise controller registers */
|
1255 | bbc58422 | Alexander Graf | mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8); |
1256 | b7169916 | aurel32 | mpp->veni = VENI; |
1257 | b7169916 | aurel32 | mpp->pint = 0x00000000;
|
1258 | b7169916 | aurel32 | mpp->spve = 0x0000FFFF;
|
1259 | b7169916 | aurel32 | /* Initialise IRQ sources */
|
1260 | b7169916 | aurel32 | for (i = 0; i < mpp->max_irq; i++) { |
1261 | b7169916 | aurel32 | mpp->src[i].ipvp = 0x80800000;
|
1262 | b7169916 | aurel32 | mpp->src[i].ide = 0x00000001;
|
1263 | b7169916 | aurel32 | } |
1264 | 9250fd24 | Alexander Graf | /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
|
1265 | 9250fd24 | Alexander Graf | for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) {
|
1266 | 9250fd24 | Alexander Graf | mpp->src[i].ide = 0;
|
1267 | 9250fd24 | Alexander Graf | } |
1268 | b7169916 | aurel32 | /* Initialise IRQ destinations */
|
1269 | b7169916 | aurel32 | for (i = 0; i < MAX_CPU; i++) { |
1270 | b7169916 | aurel32 | mpp->dst[i].pctp = 0x0000000F;
|
1271 | b7169916 | aurel32 | mpp->dst[i].tfrr = 0x00000000;
|
1272 | c227f099 | Anthony Liguori | memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
1273 | b7169916 | aurel32 | mpp->dst[i].raised.next = -1;
|
1274 | c227f099 | Anthony Liguori | memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
1275 | b7169916 | aurel32 | mpp->dst[i].servicing.next = -1;
|
1276 | b7169916 | aurel32 | } |
1277 | b7169916 | aurel32 | /* Initialise timers */
|
1278 | b7169916 | aurel32 | for (i = 0; i < MAX_TMR; i++) { |
1279 | b7169916 | aurel32 | mpp->timers[i].ticc = 0x00000000;
|
1280 | b7169916 | aurel32 | mpp->timers[i].tibc = 0x80000000;
|
1281 | b7169916 | aurel32 | } |
1282 | b7169916 | aurel32 | /* Go out of RESET state */
|
1283 | b7169916 | aurel32 | mpp->glbc = 0x00000000;
|
1284 | b7169916 | aurel32 | } |
1285 | b7169916 | aurel32 | |
1286 | c227f099 | Anthony Liguori | static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
1287 | b7169916 | aurel32 | { |
1288 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1289 | b7169916 | aurel32 | int idx, cpu;
|
1290 | b7169916 | aurel32 | |
1291 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1292 | b7169916 | aurel32 | if (addr & 0xF) |
1293 | b7169916 | aurel32 | return;
|
1294 | b7169916 | aurel32 | addr &= 0xFFFF;
|
1295 | b7169916 | aurel32 | cpu = addr >> 12;
|
1296 | b7169916 | aurel32 | idx = (addr >> 6) & 0x3; |
1297 | b7169916 | aurel32 | switch (addr & 0x30) { |
1298 | b7169916 | aurel32 | case 0x00: /* gtccr */ |
1299 | b7169916 | aurel32 | break;
|
1300 | b7169916 | aurel32 | case 0x10: /* gtbcr */ |
1301 | b7169916 | aurel32 | if ((mpp->timers[idx].ticc & 0x80000000) != 0 && |
1302 | b7169916 | aurel32 | (val & 0x80000000) == 0 && |
1303 | b7169916 | aurel32 | (mpp->timers[idx].tibc & 0x80000000) != 0) |
1304 | b7169916 | aurel32 | mpp->timers[idx].ticc &= ~0x80000000;
|
1305 | b7169916 | aurel32 | mpp->timers[idx].tibc = val; |
1306 | b7169916 | aurel32 | break;
|
1307 | b7169916 | aurel32 | case 0x20: /* GTIVPR */ |
1308 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val); |
1309 | b7169916 | aurel32 | break;
|
1310 | b7169916 | aurel32 | case 0x30: /* GTIDR & TFRR */ |
1311 | b7169916 | aurel32 | if ((addr & 0xF0) == 0xF0) |
1312 | b7169916 | aurel32 | mpp->dst[cpu].tfrr = val; |
1313 | b7169916 | aurel32 | else
|
1314 | 11de8b71 | Alexander Graf | write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val); |
1315 | b7169916 | aurel32 | break;
|
1316 | b7169916 | aurel32 | } |
1317 | b7169916 | aurel32 | } |
1318 | b7169916 | aurel32 | |
1319 | c227f099 | Anthony Liguori | static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr) |
1320 | b7169916 | aurel32 | { |
1321 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1322 | b7169916 | aurel32 | uint32_t retval; |
1323 | b7169916 | aurel32 | int idx, cpu;
|
1324 | b7169916 | aurel32 | |
1325 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1326 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1327 | b7169916 | aurel32 | if (addr & 0xF) |
1328 | b7169916 | aurel32 | return retval;
|
1329 | b7169916 | aurel32 | addr &= 0xFFFF;
|
1330 | b7169916 | aurel32 | cpu = addr >> 12;
|
1331 | b7169916 | aurel32 | idx = (addr >> 6) & 0x3; |
1332 | b7169916 | aurel32 | switch (addr & 0x30) { |
1333 | b7169916 | aurel32 | case 0x00: /* gtccr */ |
1334 | b7169916 | aurel32 | retval = mpp->timers[idx].ticc; |
1335 | b7169916 | aurel32 | break;
|
1336 | b7169916 | aurel32 | case 0x10: /* gtbcr */ |
1337 | b7169916 | aurel32 | retval = mpp->timers[idx].tibc; |
1338 | b7169916 | aurel32 | break;
|
1339 | b7169916 | aurel32 | case 0x20: /* TIPV */ |
1340 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx); |
1341 | b7169916 | aurel32 | break;
|
1342 | b7169916 | aurel32 | case 0x30: /* TIDR */ |
1343 | b7169916 | aurel32 | if ((addr &0xF0) == 0XF0) |
1344 | b7169916 | aurel32 | retval = mpp->dst[cpu].tfrr; |
1345 | b7169916 | aurel32 | else
|
1346 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx); |
1347 | b7169916 | aurel32 | break;
|
1348 | b7169916 | aurel32 | } |
1349 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1350 | b7169916 | aurel32 | |
1351 | b7169916 | aurel32 | return retval;
|
1352 | b7169916 | aurel32 | } |
1353 | b7169916 | aurel32 | |
1354 | c227f099 | Anthony Liguori | static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr, |
1355 | b7169916 | aurel32 | uint32_t val) |
1356 | b7169916 | aurel32 | { |
1357 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1358 | b7169916 | aurel32 | int idx = MPIC_EXT_IRQ;
|
1359 | b7169916 | aurel32 | |
1360 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1361 | b7169916 | aurel32 | if (addr & 0xF) |
1362 | b7169916 | aurel32 | return;
|
1363 | b7169916 | aurel32 | |
1364 | b7169916 | aurel32 | if (addr < MPIC_EXT_REG_SIZE) {
|
1365 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1366 | b7169916 | aurel32 | if (addr & 0x10) { |
1367 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1368 | 11de8b71 | Alexander Graf | write_IRQreg_ide(mpp, idx, val); |
1369 | b7169916 | aurel32 | } else {
|
1370 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1371 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(mpp, idx, val); |
1372 | b7169916 | aurel32 | } |
1373 | b7169916 | aurel32 | } |
1374 | b7169916 | aurel32 | } |
1375 | b7169916 | aurel32 | |
1376 | c227f099 | Anthony Liguori | static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr) |
1377 | b7169916 | aurel32 | { |
1378 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1379 | b7169916 | aurel32 | uint32_t retval; |
1380 | b7169916 | aurel32 | int idx = MPIC_EXT_IRQ;
|
1381 | b7169916 | aurel32 | |
1382 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1383 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1384 | b7169916 | aurel32 | if (addr & 0xF) |
1385 | b7169916 | aurel32 | return retval;
|
1386 | b7169916 | aurel32 | |
1387 | b7169916 | aurel32 | if (addr < MPIC_EXT_REG_SIZE) {
|
1388 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1389 | b7169916 | aurel32 | if (addr & 0x10) { |
1390 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1391 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(mpp, idx); |
1392 | b7169916 | aurel32 | } else {
|
1393 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1394 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(mpp, idx); |
1395 | b7169916 | aurel32 | } |
1396 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1397 | b7169916 | aurel32 | } |
1398 | b7169916 | aurel32 | |
1399 | b7169916 | aurel32 | return retval;
|
1400 | b7169916 | aurel32 | } |
1401 | b7169916 | aurel32 | |
1402 | c227f099 | Anthony Liguori | static void mpic_src_int_write (void *opaque, target_phys_addr_t addr, |
1403 | b7169916 | aurel32 | uint32_t val) |
1404 | b7169916 | aurel32 | { |
1405 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1406 | b7169916 | aurel32 | int idx = MPIC_INT_IRQ;
|
1407 | b7169916 | aurel32 | |
1408 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1409 | b7169916 | aurel32 | if (addr & 0xF) |
1410 | b7169916 | aurel32 | return;
|
1411 | b7169916 | aurel32 | |
1412 | b7169916 | aurel32 | if (addr < MPIC_INT_REG_SIZE) {
|
1413 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1414 | b7169916 | aurel32 | if (addr & 0x10) { |
1415 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1416 | 11de8b71 | Alexander Graf | write_IRQreg_ide(mpp, idx, val); |
1417 | b7169916 | aurel32 | } else {
|
1418 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1419 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(mpp, idx, val); |
1420 | b7169916 | aurel32 | } |
1421 | b7169916 | aurel32 | } |
1422 | b7169916 | aurel32 | } |
1423 | b7169916 | aurel32 | |
1424 | c227f099 | Anthony Liguori | static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr) |
1425 | b7169916 | aurel32 | { |
1426 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1427 | b7169916 | aurel32 | uint32_t retval; |
1428 | b7169916 | aurel32 | int idx = MPIC_INT_IRQ;
|
1429 | b7169916 | aurel32 | |
1430 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1431 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1432 | b7169916 | aurel32 | if (addr & 0xF) |
1433 | b7169916 | aurel32 | return retval;
|
1434 | b7169916 | aurel32 | |
1435 | b7169916 | aurel32 | if (addr < MPIC_INT_REG_SIZE) {
|
1436 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1437 | b7169916 | aurel32 | if (addr & 0x10) { |
1438 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1439 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(mpp, idx); |
1440 | b7169916 | aurel32 | } else {
|
1441 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1442 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(mpp, idx); |
1443 | b7169916 | aurel32 | } |
1444 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1445 | b7169916 | aurel32 | } |
1446 | b7169916 | aurel32 | |
1447 | b7169916 | aurel32 | return retval;
|
1448 | b7169916 | aurel32 | } |
1449 | b7169916 | aurel32 | |
1450 | c227f099 | Anthony Liguori | static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr, |
1451 | b7169916 | aurel32 | uint32_t val) |
1452 | b7169916 | aurel32 | { |
1453 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1454 | b7169916 | aurel32 | int idx = MPIC_MSG_IRQ;
|
1455 | b7169916 | aurel32 | |
1456 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1457 | b7169916 | aurel32 | if (addr & 0xF) |
1458 | b7169916 | aurel32 | return;
|
1459 | b7169916 | aurel32 | |
1460 | b7169916 | aurel32 | if (addr < MPIC_MSG_REG_SIZE) {
|
1461 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1462 | b7169916 | aurel32 | if (addr & 0x10) { |
1463 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1464 | 11de8b71 | Alexander Graf | write_IRQreg_ide(mpp, idx, val); |
1465 | b7169916 | aurel32 | } else {
|
1466 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1467 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(mpp, idx, val); |
1468 | b7169916 | aurel32 | } |
1469 | b7169916 | aurel32 | } |
1470 | b7169916 | aurel32 | } |
1471 | b7169916 | aurel32 | |
1472 | c227f099 | Anthony Liguori | static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr) |
1473 | b7169916 | aurel32 | { |
1474 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1475 | b7169916 | aurel32 | uint32_t retval; |
1476 | b7169916 | aurel32 | int idx = MPIC_MSG_IRQ;
|
1477 | b7169916 | aurel32 | |
1478 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1479 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1480 | b7169916 | aurel32 | if (addr & 0xF) |
1481 | b7169916 | aurel32 | return retval;
|
1482 | b7169916 | aurel32 | |
1483 | b7169916 | aurel32 | if (addr < MPIC_MSG_REG_SIZE) {
|
1484 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1485 | b7169916 | aurel32 | if (addr & 0x10) { |
1486 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1487 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(mpp, idx); |
1488 | b7169916 | aurel32 | } else {
|
1489 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1490 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(mpp, idx); |
1491 | b7169916 | aurel32 | } |
1492 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1493 | b7169916 | aurel32 | } |
1494 | b7169916 | aurel32 | |
1495 | b7169916 | aurel32 | return retval;
|
1496 | b7169916 | aurel32 | } |
1497 | b7169916 | aurel32 | |
1498 | c227f099 | Anthony Liguori | static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr, |
1499 | b7169916 | aurel32 | uint32_t val) |
1500 | b7169916 | aurel32 | { |
1501 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1502 | b7169916 | aurel32 | int idx = MPIC_MSI_IRQ;
|
1503 | b7169916 | aurel32 | |
1504 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1505 | b7169916 | aurel32 | if (addr & 0xF) |
1506 | b7169916 | aurel32 | return;
|
1507 | b7169916 | aurel32 | |
1508 | b7169916 | aurel32 | if (addr < MPIC_MSI_REG_SIZE) {
|
1509 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1510 | b7169916 | aurel32 | if (addr & 0x10) { |
1511 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1512 | 11de8b71 | Alexander Graf | write_IRQreg_ide(mpp, idx, val); |
1513 | b7169916 | aurel32 | } else {
|
1514 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1515 | 11de8b71 | Alexander Graf | write_IRQreg_ipvp(mpp, idx, val); |
1516 | b7169916 | aurel32 | } |
1517 | b7169916 | aurel32 | } |
1518 | b7169916 | aurel32 | } |
1519 | c227f099 | Anthony Liguori | static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr) |
1520 | b7169916 | aurel32 | { |
1521 | c227f099 | Anthony Liguori | openpic_t *mpp = opaque; |
1522 | b7169916 | aurel32 | uint32_t retval; |
1523 | b7169916 | aurel32 | int idx = MPIC_MSI_IRQ;
|
1524 | b7169916 | aurel32 | |
1525 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1526 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1527 | b7169916 | aurel32 | if (addr & 0xF) |
1528 | b7169916 | aurel32 | return retval;
|
1529 | b7169916 | aurel32 | |
1530 | b7169916 | aurel32 | if (addr < MPIC_MSI_REG_SIZE) {
|
1531 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1532 | b7169916 | aurel32 | if (addr & 0x10) { |
1533 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1534 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ide(mpp, idx); |
1535 | b7169916 | aurel32 | } else {
|
1536 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1537 | 8d3a8c1e | Alexander Graf | retval = read_IRQreg_ipvp(mpp, idx); |
1538 | b7169916 | aurel32 | } |
1539 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1540 | b7169916 | aurel32 | } |
1541 | b7169916 | aurel32 | |
1542 | b7169916 | aurel32 | return retval;
|
1543 | b7169916 | aurel32 | } |
1544 | b7169916 | aurel32 | |
1545 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_glb_ops = { |
1546 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1547 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1548 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1549 | 71cf9e62 | Fabien Chouteau | openpic_gbl_write, |
1550 | 71cf9e62 | Fabien Chouteau | }, |
1551 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1552 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1553 | 71cf9e62 | Fabien Chouteau | openpic_gbl_read, |
1554 | 71cf9e62 | Fabien Chouteau | }, |
1555 | 71cf9e62 | Fabien Chouteau | }, |
1556 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1557 | b7169916 | aurel32 | }; |
1558 | b7169916 | aurel32 | |
1559 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_tmr_ops = { |
1560 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1561 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1562 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1563 | 71cf9e62 | Fabien Chouteau | mpic_timer_write, |
1564 | 71cf9e62 | Fabien Chouteau | }, |
1565 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1566 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1567 | 71cf9e62 | Fabien Chouteau | mpic_timer_read, |
1568 | 71cf9e62 | Fabien Chouteau | }, |
1569 | 71cf9e62 | Fabien Chouteau | }, |
1570 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1571 | b7169916 | aurel32 | }; |
1572 | b7169916 | aurel32 | |
1573 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_cpu_ops = { |
1574 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1575 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1576 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1577 | 71cf9e62 | Fabien Chouteau | openpic_cpu_write, |
1578 | 71cf9e62 | Fabien Chouteau | }, |
1579 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1580 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1581 | 71cf9e62 | Fabien Chouteau | openpic_cpu_read, |
1582 | 71cf9e62 | Fabien Chouteau | }, |
1583 | 71cf9e62 | Fabien Chouteau | }, |
1584 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1585 | b7169916 | aurel32 | }; |
1586 | b7169916 | aurel32 | |
1587 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_ext_ops = { |
1588 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1589 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1590 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1591 | 71cf9e62 | Fabien Chouteau | mpic_src_ext_write, |
1592 | 71cf9e62 | Fabien Chouteau | }, |
1593 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1594 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1595 | 71cf9e62 | Fabien Chouteau | mpic_src_ext_read, |
1596 | 71cf9e62 | Fabien Chouteau | }, |
1597 | 71cf9e62 | Fabien Chouteau | }, |
1598 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1599 | b7169916 | aurel32 | }; |
1600 | b7169916 | aurel32 | |
1601 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_int_ops = { |
1602 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1603 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1604 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1605 | 71cf9e62 | Fabien Chouteau | mpic_src_int_write, |
1606 | 71cf9e62 | Fabien Chouteau | }, |
1607 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1608 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1609 | 71cf9e62 | Fabien Chouteau | mpic_src_int_read, |
1610 | 71cf9e62 | Fabien Chouteau | }, |
1611 | 71cf9e62 | Fabien Chouteau | }, |
1612 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1613 | b7169916 | aurel32 | }; |
1614 | b7169916 | aurel32 | |
1615 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_msg_ops = { |
1616 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1617 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1618 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1619 | 71cf9e62 | Fabien Chouteau | mpic_src_msg_write, |
1620 | 71cf9e62 | Fabien Chouteau | }, |
1621 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1622 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1623 | 71cf9e62 | Fabien Chouteau | mpic_src_msg_read, |
1624 | 71cf9e62 | Fabien Chouteau | }, |
1625 | 71cf9e62 | Fabien Chouteau | }, |
1626 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1627 | b7169916 | aurel32 | }; |
1628 | b7169916 | aurel32 | |
1629 | 71cf9e62 | Fabien Chouteau | static const MemoryRegionOps mpic_msi_ops = { |
1630 | 71cf9e62 | Fabien Chouteau | .old_mmio = { |
1631 | 71cf9e62 | Fabien Chouteau | .write = { openpic_buggy_write, |
1632 | 71cf9e62 | Fabien Chouteau | openpic_buggy_write, |
1633 | 71cf9e62 | Fabien Chouteau | mpic_src_msi_write, |
1634 | 71cf9e62 | Fabien Chouteau | }, |
1635 | 71cf9e62 | Fabien Chouteau | .read = { openpic_buggy_read, |
1636 | 71cf9e62 | Fabien Chouteau | openpic_buggy_read, |
1637 | 71cf9e62 | Fabien Chouteau | mpic_src_msi_read, |
1638 | 71cf9e62 | Fabien Chouteau | }, |
1639 | 71cf9e62 | Fabien Chouteau | }, |
1640 | 71cf9e62 | Fabien Chouteau | .endianness = DEVICE_BIG_ENDIAN, |
1641 | b7169916 | aurel32 | }; |
1642 | b7169916 | aurel32 | |
1643 | 71cf9e62 | Fabien Chouteau | qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base, |
1644 | 71cf9e62 | Fabien Chouteau | int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
|
1645 | b7169916 | aurel32 | { |
1646 | 71cf9e62 | Fabien Chouteau | openpic_t *mpp; |
1647 | 71cf9e62 | Fabien Chouteau | int i;
|
1648 | b7169916 | aurel32 | struct {
|
1649 | 71cf9e62 | Fabien Chouteau | const char *name; |
1650 | 71cf9e62 | Fabien Chouteau | MemoryRegionOps const *ops;
|
1651 | 71cf9e62 | Fabien Chouteau | target_phys_addr_t start_addr; |
1652 | 71cf9e62 | Fabien Chouteau | ram_addr_t size; |
1653 | dfebf62b | aurel32 | } const list[] = {
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1654 | 71cf9e62 | Fabien Chouteau | {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
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1655 | 71cf9e62 | Fabien Chouteau | {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
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1656 | 71cf9e62 | Fabien Chouteau | {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
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1657 | 71cf9e62 | Fabien Chouteau | {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
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1658 | 71cf9e62 | Fabien Chouteau | {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
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1659 | 71cf9e62 | Fabien Chouteau | {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
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1660 | 71cf9e62 | Fabien Chouteau | {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
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1661 | b7169916 | aurel32 | }; |
1662 | b7169916 | aurel32 | |
1663 | 7267c094 | Anthony Liguori | mpp = g_malloc0(sizeof(openpic_t));
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1664 | b7169916 | aurel32 | |
1665 | 71cf9e62 | Fabien Chouteau | memory_region_init(&mpp->mem, "mpic", 0x40000); |
1666 | 71cf9e62 | Fabien Chouteau | memory_region_add_subregion(address_space, base, &mpp->mem); |
1667 | 71cf9e62 | Fabien Chouteau | |
1668 | b7169916 | aurel32 | for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { |
1669 | b7169916 | aurel32 | |
1670 | 71cf9e62 | Fabien Chouteau | memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp, |
1671 | 71cf9e62 | Fabien Chouteau | list[i].name, list[i].size); |
1672 | 71cf9e62 | Fabien Chouteau | |
1673 | 71cf9e62 | Fabien Chouteau | memory_region_add_subregion(&mpp->mem, list[i].start_addr, |
1674 | 71cf9e62 | Fabien Chouteau | &mpp->sub_io_mem[i]); |
1675 | b7169916 | aurel32 | } |
1676 | b7169916 | aurel32 | |
1677 | b7169916 | aurel32 | mpp->nb_cpus = nb_cpus; |
1678 | b7169916 | aurel32 | mpp->max_irq = MPIC_MAX_IRQ; |
1679 | b7169916 | aurel32 | mpp->irq_ipi0 = MPIC_IPI_IRQ; |
1680 | b7169916 | aurel32 | mpp->irq_tim0 = MPIC_TMR_IRQ; |
1681 | b7169916 | aurel32 | |
1682 | b7169916 | aurel32 | for (i = 0; i < nb_cpus; i++) |
1683 | b7169916 | aurel32 | mpp->dst[i].irqs = irqs[i]; |
1684 | b7169916 | aurel32 | mpp->irq_out = irq_out; |
1685 | b7169916 | aurel32 | |
1686 | b7169916 | aurel32 | mpp->irq_raise = mpic_irq_raise; |
1687 | b7169916 | aurel32 | mpp->reset = mpic_reset; |
1688 | b7169916 | aurel32 | |
1689 | 0be71e32 | Alex Williamson | register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp); |
1690 | a08d4367 | Jan Kiszka | qemu_register_reset(mpic_reset, mpp); |
1691 | b7169916 | aurel32 | |
1692 | b7169916 | aurel32 | return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
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1693 | dbda808a | bellard | } |