root / hw / etraxfs_timer.c @ 5439779e
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1 | 83fa1010 | ths | /*
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2 | e62b5b13 | edgar_igl | * QEMU ETRAX Timers
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | #include <stdio.h> |
25 | 83fa1010 | ths | #include <sys/time.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 5439779e | edgar_igl | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "qemu-timer.h" |
29 | 83fa1010 | ths | |
30 | bbaf29c7 | edgar_igl | #define D(x)
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31 | bbaf29c7 | edgar_igl | |
32 | ca87d03b | edgar_igl | #define RW_TMR0_DIV 0x00 |
33 | ca87d03b | edgar_igl | #define R_TMR0_DATA 0x04 |
34 | ca87d03b | edgar_igl | #define RW_TMR0_CTRL 0x08 |
35 | ca87d03b | edgar_igl | #define RW_TMR1_DIV 0x10 |
36 | ca87d03b | edgar_igl | #define R_TMR1_DATA 0x14 |
37 | ca87d03b | edgar_igl | #define RW_TMR1_CTRL 0x18 |
38 | ca87d03b | edgar_igl | #define R_TIME 0x38 |
39 | ca87d03b | edgar_igl | #define RW_WD_CTRL 0x40 |
40 | 5439779e | edgar_igl | #define R_WD_STAT 0x44 |
41 | ca87d03b | edgar_igl | #define RW_INTR_MASK 0x48 |
42 | ca87d03b | edgar_igl | #define RW_ACK_INTR 0x4c |
43 | ca87d03b | edgar_igl | #define R_INTR 0x50 |
44 | ca87d03b | edgar_igl | #define R_MASKED_INTR 0x54 |
45 | 83fa1010 | ths | |
46 | 83fa1010 | ths | struct fs_timer_t {
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47 | ca87d03b | edgar_igl | CPUState *env; |
48 | ca87d03b | edgar_igl | qemu_irq *irq; |
49 | ca87d03b | edgar_igl | target_phys_addr_t base; |
50 | ca87d03b | edgar_igl | |
51 | 5439779e | edgar_igl | QEMUBH *bh_t0; |
52 | 5439779e | edgar_igl | QEMUBH *bh_t1; |
53 | 5439779e | edgar_igl | QEMUBH *bh_wd; |
54 | 5439779e | edgar_igl | ptimer_state *ptimer_t0; |
55 | 5439779e | edgar_igl | ptimer_state *ptimer_t1; |
56 | 5439779e | edgar_igl | ptimer_state *ptimer_wd; |
57 | bbaf29c7 | edgar_igl | struct timeval last;
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58 | e62b5b13 | edgar_igl | |
59 | 60237223 | edgar_igl | /* Control registers. */
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60 | 60237223 | edgar_igl | uint32_t rw_tmr0_div; |
61 | 60237223 | edgar_igl | uint32_t r_tmr0_data; |
62 | 60237223 | edgar_igl | uint32_t rw_tmr0_ctrl; |
63 | 60237223 | edgar_igl | |
64 | 60237223 | edgar_igl | uint32_t rw_tmr1_div; |
65 | 60237223 | edgar_igl | uint32_t r_tmr1_data; |
66 | 60237223 | edgar_igl | uint32_t rw_tmr1_ctrl; |
67 | 60237223 | edgar_igl | |
68 | 5439779e | edgar_igl | uint32_t rw_wd_ctrl; |
69 | 5439779e | edgar_igl | |
70 | e62b5b13 | edgar_igl | uint32_t rw_intr_mask; |
71 | e62b5b13 | edgar_igl | uint32_t rw_ack_intr; |
72 | e62b5b13 | edgar_igl | uint32_t r_intr; |
73 | 60237223 | edgar_igl | uint32_t r_masked_intr; |
74 | 83fa1010 | ths | }; |
75 | 83fa1010 | ths | |
76 | ca87d03b | edgar_igl | static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr) |
77 | 83fa1010 | ths | { |
78 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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79 | ca87d03b | edgar_igl | CPUState *env = t->env; |
80 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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81 | ca87d03b | edgar_igl | addr, env->pc); |
82 | ca87d03b | edgar_igl | return 0; |
83 | 83fa1010 | ths | } |
84 | 83fa1010 | ths | |
85 | 83fa1010 | ths | static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
86 | 83fa1010 | ths | { |
87 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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88 | ca87d03b | edgar_igl | D(CPUState *env = t->env); |
89 | 83fa1010 | ths | uint32_t r = 0;
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90 | 83fa1010 | ths | |
91 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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92 | ca87d03b | edgar_igl | addr -= t->base; |
93 | 83fa1010 | ths | switch (addr) {
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94 | 83fa1010 | ths | case R_TMR0_DATA:
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95 | 83fa1010 | ths | break;
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96 | 83fa1010 | ths | case R_TMR1_DATA:
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97 | bbaf29c7 | edgar_igl | D(printf ("R_TMR1_DATA\n"));
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98 | 83fa1010 | ths | break;
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99 | 83fa1010 | ths | case R_TIME:
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100 | 60237223 | edgar_igl | r = qemu_get_clock(vm_clock) * 10;
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101 | 83fa1010 | ths | break;
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102 | 83fa1010 | ths | case RW_INTR_MASK:
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103 | ca87d03b | edgar_igl | r = t->rw_intr_mask; |
104 | 83fa1010 | ths | break;
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105 | 83fa1010 | ths | case R_MASKED_INTR:
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106 | ca87d03b | edgar_igl | r = t->r_intr & t->rw_intr_mask; |
107 | 83fa1010 | ths | break;
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108 | 83fa1010 | ths | default:
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109 | e62b5b13 | edgar_igl | D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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110 | 83fa1010 | ths | break;
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111 | 83fa1010 | ths | } |
112 | 83fa1010 | ths | return r;
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113 | 83fa1010 | ths | } |
114 | 83fa1010 | ths | |
115 | 83fa1010 | ths | static void |
116 | ca87d03b | edgar_igl | timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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117 | 83fa1010 | ths | { |
118 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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119 | ca87d03b | edgar_igl | CPUState *env = t->env; |
120 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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121 | ca87d03b | edgar_igl | addr, env->pc); |
122 | 83fa1010 | ths | } |
123 | 83fa1010 | ths | |
124 | f0b86b14 | edgar_igl | #define TIMER_SLOWDOWN 1 |
125 | 5439779e | edgar_igl | static void update_ctrl(struct fs_timer_t *t, int tnum) |
126 | 83fa1010 | ths | { |
127 | 60237223 | edgar_igl | unsigned int op; |
128 | 60237223 | edgar_igl | unsigned int freq; |
129 | 60237223 | edgar_igl | unsigned int freq_hz; |
130 | 60237223 | edgar_igl | unsigned int div; |
131 | 5439779e | edgar_igl | uint32_t ctrl; |
132 | 5439779e | edgar_igl | ptimer_state *timer; |
133 | 5439779e | edgar_igl | |
134 | 5439779e | edgar_igl | if (tnum == 0) { |
135 | 5439779e | edgar_igl | ctrl = t->rw_tmr0_ctrl; |
136 | 5439779e | edgar_igl | div = t->rw_tmr0_div; |
137 | 5439779e | edgar_igl | timer = t->ptimer_t0; |
138 | 5439779e | edgar_igl | } else {
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139 | 5439779e | edgar_igl | ctrl = t->rw_tmr1_ctrl; |
140 | 5439779e | edgar_igl | div = t->rw_tmr1_div; |
141 | 5439779e | edgar_igl | timer = t->ptimer_t1; |
142 | 5439779e | edgar_igl | } |
143 | 5439779e | edgar_igl | |
144 | 83fa1010 | ths | |
145 | 5439779e | edgar_igl | op = ctrl & 3;
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146 | 5439779e | edgar_igl | freq = ctrl >> 2;
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147 | 83fa1010 | ths | freq_hz = 32000000;
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148 | 83fa1010 | ths | |
149 | 83fa1010 | ths | switch (freq)
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150 | 83fa1010 | ths | { |
151 | 83fa1010 | ths | case 0: |
152 | 83fa1010 | ths | case 1: |
153 | e62b5b13 | edgar_igl | D(printf ("extern or disabled timer clock?\n"));
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154 | 83fa1010 | ths | break;
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155 | 83fa1010 | ths | case 4: freq_hz = 29493000; break; |
156 | 83fa1010 | ths | case 5: freq_hz = 32000000; break; |
157 | 83fa1010 | ths | case 6: freq_hz = 32768000; break; |
158 | 5439779e | edgar_igl | case 7: freq_hz = 100001000; break; |
159 | 83fa1010 | ths | default:
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160 | 83fa1010 | ths | abort(); |
161 | 83fa1010 | ths | break;
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162 | 83fa1010 | ths | } |
163 | 83fa1010 | ths | |
164 | 5439779e | edgar_igl | D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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165 | 5439779e | edgar_igl | div = div * TIMER_SLOWDOWN; |
166 | 60237223 | edgar_igl | div >>= 15;
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167 | 60237223 | edgar_igl | freq_hz >>= 15;
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168 | 5439779e | edgar_igl | ptimer_set_freq(timer, freq_hz); |
169 | 5439779e | edgar_igl | ptimer_set_limit(timer, div, 0);
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170 | 83fa1010 | ths | |
171 | 83fa1010 | ths | switch (op)
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172 | 83fa1010 | ths | { |
173 | 83fa1010 | ths | case 0: |
174 | 60237223 | edgar_igl | /* Load. */
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175 | 5439779e | edgar_igl | ptimer_set_limit(timer, div, 1);
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176 | 83fa1010 | ths | break;
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177 | 83fa1010 | ths | case 1: |
178 | 60237223 | edgar_igl | /* Hold. */
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179 | 5439779e | edgar_igl | ptimer_stop(timer); |
180 | 83fa1010 | ths | break;
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181 | 83fa1010 | ths | case 2: |
182 | 60237223 | edgar_igl | /* Run. */
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183 | 5439779e | edgar_igl | ptimer_run(timer, 0);
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184 | 83fa1010 | ths | break;
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185 | 83fa1010 | ths | default:
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186 | 83fa1010 | ths | abort(); |
187 | 83fa1010 | ths | break;
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188 | 83fa1010 | ths | } |
189 | 83fa1010 | ths | } |
190 | 83fa1010 | ths | |
191 | 60237223 | edgar_igl | static void timer_update_irq(struct fs_timer_t *t) |
192 | 83fa1010 | ths | { |
193 | 60237223 | edgar_igl | t->r_intr &= ~(t->rw_ack_intr); |
194 | 60237223 | edgar_igl | t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
195 | 60237223 | edgar_igl | |
196 | 60237223 | edgar_igl | D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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197 | eb173de6 | edgar_igl | if (t->r_masked_intr)
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198 | 60237223 | edgar_igl | qemu_irq_raise(t->irq[0]);
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199 | 60237223 | edgar_igl | else
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200 | bbaf29c7 | edgar_igl | qemu_irq_lower(t->irq[0]);
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201 | 83fa1010 | ths | } |
202 | 83fa1010 | ths | |
203 | 5439779e | edgar_igl | static void timer0_hit(void *opaque) |
204 | 60237223 | edgar_igl | { |
205 | 63c1d925 | edgar_igl | struct fs_timer_t *t = opaque;
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206 | 60237223 | edgar_igl | t->r_intr |= 1;
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207 | 60237223 | edgar_igl | timer_update_irq(t); |
208 | 60237223 | edgar_igl | } |
209 | 60237223 | edgar_igl | |
210 | 5439779e | edgar_igl | static void timer1_hit(void *opaque) |
211 | 5439779e | edgar_igl | { |
212 | 5439779e | edgar_igl | struct fs_timer_t *t = opaque;
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213 | 5439779e | edgar_igl | t->r_intr |= 2;
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214 | 5439779e | edgar_igl | timer_update_irq(t); |
215 | 5439779e | edgar_igl | } |
216 | 5439779e | edgar_igl | |
217 | 5439779e | edgar_igl | static void watchdog_hit(void *opaque) |
218 | 5439779e | edgar_igl | { |
219 | 5439779e | edgar_igl | qemu_system_reset_request(); |
220 | 5439779e | edgar_igl | } |
221 | 5439779e | edgar_igl | |
222 | 5439779e | edgar_igl | static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value) |
223 | 5439779e | edgar_igl | { |
224 | 5439779e | edgar_igl | unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
225 | 5439779e | edgar_igl | unsigned int wd_key = t->rw_wd_ctrl >> 9; |
226 | 5439779e | edgar_igl | unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
227 | 5439779e | edgar_igl | unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
228 | 5439779e | edgar_igl | unsigned int new_cmd = (value >> 8) & 1; |
229 | 5439779e | edgar_igl | |
230 | 5439779e | edgar_igl | /* If the watchdog is enabled, they written key must match the
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231 | 5439779e | edgar_igl | complement of the previous. */
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232 | 5439779e | edgar_igl | wd_key = ~wd_key & ((1 << 7) - 1); |
233 | 5439779e | edgar_igl | |
234 | 5439779e | edgar_igl | if (wd_en && wd_key != new_key)
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235 | 5439779e | edgar_igl | return;
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236 | 5439779e | edgar_igl | |
237 | 5439779e | edgar_igl | D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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238 | 5439779e | edgar_igl | wd_en, new_key, wd_key, wd_cmd, wd_cnt)); |
239 | 5439779e | edgar_igl | |
240 | 5439779e | edgar_igl | ptimer_set_freq(t->ptimer_wd, 760);
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241 | 5439779e | edgar_igl | if (wd_cnt == 0) |
242 | 5439779e | edgar_igl | wd_cnt = 256;
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243 | 5439779e | edgar_igl | ptimer_set_count(t->ptimer_wd, wd_cnt); |
244 | 5439779e | edgar_igl | if (new_cmd)
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245 | 5439779e | edgar_igl | ptimer_run(t->ptimer_wd, 1);
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246 | 5439779e | edgar_igl | else
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247 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_wd); |
248 | 5439779e | edgar_igl | |
249 | 5439779e | edgar_igl | t->rw_wd_ctrl = value; |
250 | 5439779e | edgar_igl | } |
251 | 5439779e | edgar_igl | |
252 | 83fa1010 | ths | static void |
253 | 83fa1010 | ths | timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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254 | 83fa1010 | ths | { |
255 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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256 | ca87d03b | edgar_igl | CPUState *env = t->env; |
257 | bbaf29c7 | edgar_igl | |
258 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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259 | ca87d03b | edgar_igl | addr -= t->base; |
260 | 83fa1010 | ths | switch (addr)
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261 | 83fa1010 | ths | { |
262 | 83fa1010 | ths | case RW_TMR0_DIV:
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263 | 60237223 | edgar_igl | t->rw_tmr0_div = value; |
264 | 83fa1010 | ths | break;
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265 | 83fa1010 | ths | case RW_TMR0_CTRL:
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266 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR0_CTRL=%x\n", value));
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267 | 60237223 | edgar_igl | t->rw_tmr0_ctrl = value; |
268 | 5439779e | edgar_igl | update_ctrl(t, 0);
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269 | 83fa1010 | ths | break;
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270 | 83fa1010 | ths | case RW_TMR1_DIV:
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271 | 60237223 | edgar_igl | t->rw_tmr1_div = value; |
272 | 83fa1010 | ths | break;
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273 | 83fa1010 | ths | case RW_TMR1_CTRL:
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274 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR1_CTRL=%x\n", value));
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275 | 5439779e | edgar_igl | t->rw_tmr1_ctrl = value; |
276 | 5439779e | edgar_igl | update_ctrl(t, 1);
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277 | 83fa1010 | ths | break;
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278 | 83fa1010 | ths | case RW_INTR_MASK:
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279 | bbaf29c7 | edgar_igl | D(printf ("RW_INTR_MASK=%x\n", value));
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280 | ca87d03b | edgar_igl | t->rw_intr_mask = value; |
281 | 60237223 | edgar_igl | timer_update_irq(t); |
282 | e62b5b13 | edgar_igl | break;
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283 | e62b5b13 | edgar_igl | case RW_WD_CTRL:
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284 | 5439779e | edgar_igl | timer_watchdog_update(t, value); |
285 | 83fa1010 | ths | break;
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286 | 83fa1010 | ths | case RW_ACK_INTR:
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287 | 60237223 | edgar_igl | t->rw_ack_intr = value; |
288 | 60237223 | edgar_igl | timer_update_irq(t); |
289 | 60237223 | edgar_igl | t->rw_ack_intr = 0;
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290 | 83fa1010 | ths | break;
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291 | 83fa1010 | ths | default:
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292 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n",
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293 | 83fa1010 | ths | __func__, addr, value, env->pc); |
294 | 83fa1010 | ths | break;
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295 | 83fa1010 | ths | } |
296 | 83fa1010 | ths | } |
297 | 83fa1010 | ths | |
298 | 83fa1010 | ths | static CPUReadMemoryFunc *timer_read[] = {
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299 | 5439779e | edgar_igl | &timer_rinvalid, |
300 | 5439779e | edgar_igl | &timer_rinvalid, |
301 | 5439779e | edgar_igl | &timer_readl, |
302 | 83fa1010 | ths | }; |
303 | 83fa1010 | ths | |
304 | 83fa1010 | ths | static CPUWriteMemoryFunc *timer_write[] = {
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305 | 5439779e | edgar_igl | &timer_winvalid, |
306 | 5439779e | edgar_igl | &timer_winvalid, |
307 | 5439779e | edgar_igl | &timer_writel, |
308 | 83fa1010 | ths | }; |
309 | 83fa1010 | ths | |
310 | 5439779e | edgar_igl | static void etraxfs_timer_reset(void *opaque) |
311 | 5439779e | edgar_igl | { |
312 | 5439779e | edgar_igl | struct fs_timer_t *t = opaque;
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313 | 5439779e | edgar_igl | |
314 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_t0); |
315 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_t1); |
316 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_wd); |
317 | 5439779e | edgar_igl | t->rw_wd_ctrl = 0;
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318 | 5439779e | edgar_igl | t->r_intr = 0;
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319 | 5439779e | edgar_igl | t->rw_intr_mask = 0;
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320 | 5439779e | edgar_igl | qemu_irq_lower(t->irq[0]);
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321 | 5439779e | edgar_igl | } |
322 | 5439779e | edgar_igl | |
323 | ca87d03b | edgar_igl | void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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324 | ca87d03b | edgar_igl | target_phys_addr_t base) |
325 | 83fa1010 | ths | { |
326 | ca87d03b | edgar_igl | static struct fs_timer_t *t; |
327 | 83fa1010 | ths | int timer_regs;
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328 | 83fa1010 | ths | |
329 | ca87d03b | edgar_igl | t = qemu_mallocz(sizeof *t);
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330 | ca87d03b | edgar_igl | if (!t)
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331 | ca87d03b | edgar_igl | return;
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332 | bbaf29c7 | edgar_igl | |
333 | 5439779e | edgar_igl | t->bh_t0 = qemu_bh_new(timer0_hit, t); |
334 | 5439779e | edgar_igl | t->bh_t1 = qemu_bh_new(timer1_hit, t); |
335 | 5439779e | edgar_igl | t->bh_wd = qemu_bh_new(watchdog_hit, t); |
336 | 5439779e | edgar_igl | t->ptimer_t0 = ptimer_init(t->bh_t0); |
337 | 5439779e | edgar_igl | t->ptimer_t1 = ptimer_init(t->bh_t1); |
338 | 5439779e | edgar_igl | t->ptimer_wd = ptimer_init(t->bh_wd); |
339 | 60237223 | edgar_igl | t->irq = irqs; |
340 | ca87d03b | edgar_igl | t->env = env; |
341 | ca87d03b | edgar_igl | t->base = base; |
342 | 83fa1010 | ths | |
343 | ca87d03b | edgar_igl | timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
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344 | ca87d03b | edgar_igl | cpu_register_physical_memory (base, 0x5c, timer_regs);
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345 | 5439779e | edgar_igl | |
346 | 5439779e | edgar_igl | qemu_register_reset(etraxfs_timer_reset, t); |
347 | 83fa1010 | ths | } |