root / hw / mcf5206.c @ 5439779e
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1 | 5fafdf24 | ths | /*
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2 | 0633879f | pbrook | * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
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3 | 0633879f | pbrook | *
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4 | 0633879f | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | 0633879f | pbrook | *
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6 | 0633879f | pbrook | * This code is licenced under the GPL
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7 | 0633879f | pbrook | */
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8 | 87ecb68b | pbrook | #include "hw.h" |
9 | 87ecb68b | pbrook | #include "mcf.h" |
10 | 87ecb68b | pbrook | #include "qemu-timer.h" |
11 | 87ecb68b | pbrook | #include "sysemu.h" |
12 | 0633879f | pbrook | |
13 | 0633879f | pbrook | /* General purpose timer module. */
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14 | 0633879f | pbrook | typedef struct { |
15 | 0633879f | pbrook | uint16_t tmr; |
16 | 0633879f | pbrook | uint16_t trr; |
17 | 0633879f | pbrook | uint16_t tcr; |
18 | 0633879f | pbrook | uint16_t ter; |
19 | 0633879f | pbrook | ptimer_state *timer; |
20 | 0633879f | pbrook | qemu_irq irq; |
21 | 0633879f | pbrook | int irq_state;
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22 | 0633879f | pbrook | } m5206_timer_state; |
23 | 0633879f | pbrook | |
24 | 0633879f | pbrook | #define TMR_RST 0x01 |
25 | 0633879f | pbrook | #define TMR_CLK 0x06 |
26 | 0633879f | pbrook | #define TMR_FRR 0x08 |
27 | 0633879f | pbrook | #define TMR_ORI 0x10 |
28 | 0633879f | pbrook | #define TMR_OM 0x20 |
29 | 0633879f | pbrook | #define TMR_CE 0xc0 |
30 | 0633879f | pbrook | |
31 | 0633879f | pbrook | #define TER_CAP 0x01 |
32 | 0633879f | pbrook | #define TER_REF 0x02 |
33 | 0633879f | pbrook | |
34 | 0633879f | pbrook | static void m5206_timer_update(m5206_timer_state *s) |
35 | 0633879f | pbrook | { |
36 | 0633879f | pbrook | if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) |
37 | 0633879f | pbrook | qemu_irq_raise(s->irq); |
38 | 0633879f | pbrook | else
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39 | 0633879f | pbrook | qemu_irq_lower(s->irq); |
40 | 0633879f | pbrook | } |
41 | 0633879f | pbrook | |
42 | 0633879f | pbrook | static void m5206_timer_reset(m5206_timer_state *s) |
43 | 0633879f | pbrook | { |
44 | 0633879f | pbrook | s->tmr = 0;
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45 | 0633879f | pbrook | s->trr = 0;
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46 | 0633879f | pbrook | } |
47 | 0633879f | pbrook | |
48 | 0633879f | pbrook | static void m5206_timer_recalibrate(m5206_timer_state *s) |
49 | 0633879f | pbrook | { |
50 | 0633879f | pbrook | int prescale;
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51 | 0633879f | pbrook | int mode;
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52 | 0633879f | pbrook | |
53 | 0633879f | pbrook | ptimer_stop(s->timer); |
54 | 0633879f | pbrook | |
55 | 0633879f | pbrook | if ((s->tmr & TMR_RST) == 0) |
56 | 0633879f | pbrook | return;
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57 | 0633879f | pbrook | |
58 | 0633879f | pbrook | prescale = (s->tmr >> 8) + 1; |
59 | 0633879f | pbrook | mode = (s->tmr >> 1) & 3; |
60 | 0633879f | pbrook | if (mode == 2) |
61 | 0633879f | pbrook | prescale *= 16;
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62 | 0633879f | pbrook | |
63 | 0633879f | pbrook | if (mode == 3 || mode == 0) |
64 | 5fafdf24 | ths | cpu_abort(cpu_single_env, |
65 | 0633879f | pbrook | "m5206_timer: mode %d not implemented\n", mode);
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66 | 0633879f | pbrook | if ((s->tmr & TMR_FRR) == 0) |
67 | 0633879f | pbrook | cpu_abort(cpu_single_env, |
68 | 0633879f | pbrook | "m5206_timer: free running mode not implemented\n");
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69 | 0633879f | pbrook | |
70 | 0633879f | pbrook | /* Assume 66MHz system clock. */
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71 | 0633879f | pbrook | ptimer_set_freq(s->timer, 66000000 / prescale);
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72 | 0633879f | pbrook | |
73 | 0633879f | pbrook | ptimer_set_limit(s->timer, s->trr, 0);
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74 | 0633879f | pbrook | |
75 | 0633879f | pbrook | ptimer_run(s->timer, 0);
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76 | 0633879f | pbrook | } |
77 | 0633879f | pbrook | |
78 | 0633879f | pbrook | static void m5206_timer_trigger(void *opaque) |
79 | 0633879f | pbrook | { |
80 | 0633879f | pbrook | m5206_timer_state *s = (m5206_timer_state *)opaque; |
81 | 0633879f | pbrook | s->ter |= TER_REF; |
82 | 0633879f | pbrook | m5206_timer_update(s); |
83 | 0633879f | pbrook | } |
84 | 0633879f | pbrook | |
85 | 0633879f | pbrook | static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
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86 | 0633879f | pbrook | { |
87 | 0633879f | pbrook | switch (addr) {
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88 | 0633879f | pbrook | case 0: |
89 | 0633879f | pbrook | return s->tmr;
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90 | 0633879f | pbrook | case 4: |
91 | 0633879f | pbrook | return s->trr;
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92 | 0633879f | pbrook | case 8: |
93 | 0633879f | pbrook | return s->tcr;
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94 | 0633879f | pbrook | case 0xc: |
95 | 0633879f | pbrook | return s->trr - ptimer_get_count(s->timer);
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96 | 0633879f | pbrook | case 0x11: |
97 | 0633879f | pbrook | return s->ter;
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98 | 0633879f | pbrook | default:
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99 | 0633879f | pbrook | return 0; |
100 | 0633879f | pbrook | } |
101 | 0633879f | pbrook | } |
102 | 0633879f | pbrook | |
103 | 0633879f | pbrook | static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val) |
104 | 0633879f | pbrook | { |
105 | 0633879f | pbrook | switch (addr) {
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106 | 0633879f | pbrook | case 0: |
107 | 0633879f | pbrook | if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) { |
108 | 0633879f | pbrook | m5206_timer_reset(s); |
109 | 0633879f | pbrook | } |
110 | 0633879f | pbrook | s->tmr = val; |
111 | 0633879f | pbrook | m5206_timer_recalibrate(s); |
112 | 0633879f | pbrook | break;
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113 | 0633879f | pbrook | case 4: |
114 | 0633879f | pbrook | s->trr = val; |
115 | 0633879f | pbrook | m5206_timer_recalibrate(s); |
116 | 0633879f | pbrook | break;
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117 | 0633879f | pbrook | case 8: |
118 | 0633879f | pbrook | s->tcr = val; |
119 | 0633879f | pbrook | break;
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120 | 0633879f | pbrook | case 0xc: |
121 | 0633879f | pbrook | ptimer_set_count(s->timer, val); |
122 | 0633879f | pbrook | break;
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123 | 0633879f | pbrook | case 0x11: |
124 | 0633879f | pbrook | s->ter &= ~val; |
125 | 0633879f | pbrook | break;
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126 | 0633879f | pbrook | default:
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127 | 0633879f | pbrook | break;
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128 | 0633879f | pbrook | } |
129 | 0633879f | pbrook | m5206_timer_update(s); |
130 | 0633879f | pbrook | } |
131 | 0633879f | pbrook | |
132 | 0633879f | pbrook | static m5206_timer_state *m5206_timer_init(qemu_irq irq)
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133 | 0633879f | pbrook | { |
134 | 0633879f | pbrook | m5206_timer_state *s; |
135 | 0633879f | pbrook | QEMUBH *bh; |
136 | 0633879f | pbrook | |
137 | 0633879f | pbrook | s = (m5206_timer_state *)qemu_mallocz(sizeof(m5206_timer_state));
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138 | 0633879f | pbrook | bh = qemu_bh_new(m5206_timer_trigger, s); |
139 | 0633879f | pbrook | s->timer = ptimer_init(bh); |
140 | 0633879f | pbrook | s->irq = irq; |
141 | 0633879f | pbrook | m5206_timer_reset(s); |
142 | 0633879f | pbrook | return s;
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143 | 0633879f | pbrook | } |
144 | 0633879f | pbrook | |
145 | 0633879f | pbrook | /* System Integration Module. */
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146 | 0633879f | pbrook | |
147 | 0633879f | pbrook | typedef struct { |
148 | 0633879f | pbrook | CPUState *env; |
149 | 0633879f | pbrook | m5206_timer_state *timer[2];
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150 | 20dcee94 | pbrook | void *uart[2]; |
151 | 0633879f | pbrook | uint8_t scr; |
152 | 0633879f | pbrook | uint8_t icr[14];
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153 | 0633879f | pbrook | uint16_t imr; /* 1 == interrupt is masked. */
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154 | 0633879f | pbrook | uint16_t ipr; |
155 | 0633879f | pbrook | uint8_t rsr; |
156 | 0633879f | pbrook | uint8_t swivr; |
157 | 0633879f | pbrook | uint8_t par; |
158 | 0633879f | pbrook | /* Include the UART vector registers here. */
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159 | 0633879f | pbrook | uint8_t uivr[2];
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160 | 0633879f | pbrook | } m5206_mbar_state; |
161 | 0633879f | pbrook | |
162 | 0633879f | pbrook | /* Interrupt controller. */
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163 | 0633879f | pbrook | |
164 | 0633879f | pbrook | static int m5206_find_pending_irq(m5206_mbar_state *s) |
165 | 0633879f | pbrook | { |
166 | 0633879f | pbrook | int level;
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167 | 0633879f | pbrook | int vector;
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168 | 0633879f | pbrook | uint16_t active; |
169 | 0633879f | pbrook | int i;
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170 | 0633879f | pbrook | |
171 | 0633879f | pbrook | level = 0;
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172 | 0633879f | pbrook | vector = 0;
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173 | 0633879f | pbrook | active = s->ipr & ~s->imr; |
174 | 0633879f | pbrook | if (!active)
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175 | 0633879f | pbrook | return 0; |
176 | 0633879f | pbrook | |
177 | 0633879f | pbrook | for (i = 1; i < 14; i++) { |
178 | 0633879f | pbrook | if (active & (1 << i)) { |
179 | 0633879f | pbrook | if ((s->icr[i] & 0x1f) > level) { |
180 | 0633879f | pbrook | level = s->icr[i] & 0x1f;
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181 | 0633879f | pbrook | vector = i; |
182 | 0633879f | pbrook | } |
183 | 0633879f | pbrook | } |
184 | 0633879f | pbrook | } |
185 | 0633879f | pbrook | |
186 | 0633879f | pbrook | if (level < 4) |
187 | 0633879f | pbrook | vector = 0;
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188 | 0633879f | pbrook | |
189 | 0633879f | pbrook | return vector;
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190 | 0633879f | pbrook | } |
191 | 0633879f | pbrook | |
192 | 0633879f | pbrook | static void m5206_mbar_update(m5206_mbar_state *s) |
193 | 0633879f | pbrook | { |
194 | 0633879f | pbrook | int irq;
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195 | 0633879f | pbrook | int vector;
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196 | 0633879f | pbrook | int level;
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197 | 0633879f | pbrook | |
198 | 0633879f | pbrook | irq = m5206_find_pending_irq(s); |
199 | 0633879f | pbrook | if (irq) {
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200 | 0633879f | pbrook | int tmp;
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201 | 0633879f | pbrook | tmp = s->icr[irq]; |
202 | 0633879f | pbrook | level = (tmp >> 2) & 7; |
203 | 0633879f | pbrook | if (tmp & 0x80) { |
204 | 0633879f | pbrook | /* Autovector. */
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205 | 0633879f | pbrook | vector = 24 + level;
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206 | 0633879f | pbrook | } else {
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207 | 0633879f | pbrook | switch (irq) {
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208 | 0633879f | pbrook | case 8: /* SWT */ |
209 | 0633879f | pbrook | vector = s->swivr; |
210 | 0633879f | pbrook | break;
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211 | 0633879f | pbrook | case 12: /* UART1 */ |
212 | 0633879f | pbrook | vector = s->uivr[0];
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213 | 0633879f | pbrook | break;
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214 | 0633879f | pbrook | case 13: /* UART2 */ |
215 | 0633879f | pbrook | vector = s->uivr[1];
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216 | 0633879f | pbrook | break;
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217 | 0633879f | pbrook | default:
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218 | 0633879f | pbrook | /* Unknown vector. */
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219 | 0633879f | pbrook | fprintf(stderr, "Unhandled vector for IRQ %d\n", irq);
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220 | 0633879f | pbrook | vector = 0xf;
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221 | 0633879f | pbrook | break;
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222 | 0633879f | pbrook | } |
223 | 0633879f | pbrook | } |
224 | 0633879f | pbrook | } else {
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225 | 0633879f | pbrook | level = 0;
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226 | 0633879f | pbrook | vector = 0;
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227 | 0633879f | pbrook | } |
228 | 0633879f | pbrook | m68k_set_irq_level(s->env, level, vector); |
229 | 0633879f | pbrook | } |
230 | 0633879f | pbrook | |
231 | 0633879f | pbrook | static void m5206_mbar_set_irq(void *opaque, int irq, int level) |
232 | 0633879f | pbrook | { |
233 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
234 | 0633879f | pbrook | if (level) {
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235 | 0633879f | pbrook | s->ipr |= 1 << irq;
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236 | 0633879f | pbrook | } else {
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237 | 0633879f | pbrook | s->ipr &= ~(1 << irq);
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238 | 0633879f | pbrook | } |
239 | 0633879f | pbrook | m5206_mbar_update(s); |
240 | 0633879f | pbrook | } |
241 | 0633879f | pbrook | |
242 | 0633879f | pbrook | /* System Integration Module. */
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243 | 0633879f | pbrook | |
244 | 0633879f | pbrook | static void m5206_mbar_reset(m5206_mbar_state *s) |
245 | 0633879f | pbrook | { |
246 | 0633879f | pbrook | s->scr = 0xc0;
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247 | 0633879f | pbrook | s->icr[1] = 0x04; |
248 | 0633879f | pbrook | s->icr[2] = 0x08; |
249 | 0633879f | pbrook | s->icr[3] = 0x0c; |
250 | 0633879f | pbrook | s->icr[4] = 0x10; |
251 | 0633879f | pbrook | s->icr[5] = 0x14; |
252 | 0633879f | pbrook | s->icr[6] = 0x18; |
253 | 0633879f | pbrook | s->icr[7] = 0x1c; |
254 | 0633879f | pbrook | s->icr[8] = 0x1c; |
255 | 0633879f | pbrook | s->icr[9] = 0x80; |
256 | 0633879f | pbrook | s->icr[10] = 0x80; |
257 | 0633879f | pbrook | s->icr[11] = 0x80; |
258 | 0633879f | pbrook | s->icr[12] = 0x00; |
259 | 0633879f | pbrook | s->icr[13] = 0x00; |
260 | 0633879f | pbrook | s->imr = 0x3ffe;
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261 | 0633879f | pbrook | s->rsr = 0x80;
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262 | 0633879f | pbrook | s->swivr = 0x0f;
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263 | 0633879f | pbrook | s->par = 0;
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264 | 0633879f | pbrook | } |
265 | 0633879f | pbrook | |
266 | 0633879f | pbrook | static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
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267 | 0633879f | pbrook | { |
268 | 0633879f | pbrook | if (offset >= 0x100 && offset < 0x120) { |
269 | 0633879f | pbrook | return m5206_timer_read(s->timer[0], offset - 0x100); |
270 | 0633879f | pbrook | } else if (offset >= 0x120 && offset < 0x140) { |
271 | 0633879f | pbrook | return m5206_timer_read(s->timer[1], offset - 0x120); |
272 | 0633879f | pbrook | } else if (offset >= 0x140 && offset < 0x160) { |
273 | 20dcee94 | pbrook | return mcf_uart_read(s->uart[0], offset - 0x140); |
274 | 0633879f | pbrook | } else if (offset >= 0x180 && offset < 0x1a0) { |
275 | 20dcee94 | pbrook | return mcf_uart_read(s->uart[1], offset - 0x180); |
276 | 0633879f | pbrook | } |
277 | 0633879f | pbrook | switch (offset) {
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278 | 0633879f | pbrook | case 0x03: return s->scr; |
279 | 0633879f | pbrook | case 0x14 ... 0x20: return s->icr[offset - 0x13]; |
280 | 0633879f | pbrook | case 0x36: return s->imr; |
281 | 0633879f | pbrook | case 0x3a: return s->ipr; |
282 | 0633879f | pbrook | case 0x40: return s->rsr; |
283 | 0633879f | pbrook | case 0x41: return 0; |
284 | 0633879f | pbrook | case 0x42: return s->swivr; |
285 | 0633879f | pbrook | case 0x50: |
286 | 0633879f | pbrook | /* DRAM mask register. */
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287 | 0633879f | pbrook | /* FIXME: currently hardcoded to 128Mb. */
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288 | 0633879f | pbrook | { |
289 | 0633879f | pbrook | uint32_t mask = ~0;
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290 | 0633879f | pbrook | while (mask > ram_size)
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291 | 0633879f | pbrook | mask >>= 1;
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292 | 0633879f | pbrook | return mask & 0x0ffe0000; |
293 | 0633879f | pbrook | } |
294 | 0633879f | pbrook | case 0x5c: return 1; /* DRAM bank 1 empty. */ |
295 | 0633879f | pbrook | case 0xcb: return s->par; |
296 | 0633879f | pbrook | case 0x170: return s->uivr[0]; |
297 | 0633879f | pbrook | case 0x1b0: return s->uivr[1]; |
298 | 0633879f | pbrook | } |
299 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset); |
300 | 0633879f | pbrook | return 0; |
301 | 0633879f | pbrook | } |
302 | 0633879f | pbrook | |
303 | 0633879f | pbrook | static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, |
304 | 0633879f | pbrook | uint32_t value) |
305 | 0633879f | pbrook | { |
306 | 0633879f | pbrook | if (offset >= 0x100 && offset < 0x120) { |
307 | 0633879f | pbrook | m5206_timer_write(s->timer[0], offset - 0x100, value); |
308 | 0633879f | pbrook | return;
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309 | 0633879f | pbrook | } else if (offset >= 0x120 && offset < 0x140) { |
310 | 0633879f | pbrook | m5206_timer_write(s->timer[1], offset - 0x120, value); |
311 | 0633879f | pbrook | return;
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312 | 0633879f | pbrook | } else if (offset >= 0x140 && offset < 0x160) { |
313 | 20dcee94 | pbrook | mcf_uart_write(s->uart[0], offset - 0x140, value); |
314 | 0633879f | pbrook | return;
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315 | 0633879f | pbrook | } else if (offset >= 0x180 && offset < 0x1a0) { |
316 | 20dcee94 | pbrook | mcf_uart_write(s->uart[1], offset - 0x180, value); |
317 | 0633879f | pbrook | return;
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318 | 0633879f | pbrook | } |
319 | 0633879f | pbrook | switch (offset) {
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320 | 0633879f | pbrook | case 0x03: |
321 | 0633879f | pbrook | s->scr = value; |
322 | 0633879f | pbrook | break;
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323 | 0633879f | pbrook | case 0x14 ... 0x20: |
324 | 0633879f | pbrook | s->icr[offset - 0x13] = value;
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325 | 0633879f | pbrook | m5206_mbar_update(s); |
326 | 0633879f | pbrook | break;
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327 | 0633879f | pbrook | case 0x36: |
328 | 0633879f | pbrook | s->imr = value; |
329 | 0633879f | pbrook | m5206_mbar_update(s); |
330 | 0633879f | pbrook | break;
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331 | 0633879f | pbrook | case 0x40: |
332 | 0633879f | pbrook | s->rsr &= ~value; |
333 | 0633879f | pbrook | break;
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334 | 0633879f | pbrook | case 0x41: |
335 | 0633879f | pbrook | /* TODO: implement watchdog. */
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336 | 0633879f | pbrook | break;
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337 | 0633879f | pbrook | case 0x42: |
338 | 0633879f | pbrook | s->swivr = value; |
339 | 0633879f | pbrook | break;
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340 | 0633879f | pbrook | case 0xcb: |
341 | 0633879f | pbrook | s->par = value; |
342 | 0633879f | pbrook | break;
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343 | 0633879f | pbrook | case 0x170: |
344 | 0633879f | pbrook | s->uivr[0] = value;
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345 | 0633879f | pbrook | break;
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346 | 0633879f | pbrook | case 0x178: case 0x17c: case 0x1c8: case 0x1bc: |
347 | 0633879f | pbrook | /* Not implemented: UART Output port bits. */
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348 | 0633879f | pbrook | break;
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349 | 0633879f | pbrook | case 0x1b0: |
350 | 0633879f | pbrook | s->uivr[1] = value;
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351 | 0633879f | pbrook | break;
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352 | 0633879f | pbrook | default:
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353 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset); |
354 | 0633879f | pbrook | break;
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355 | 0633879f | pbrook | } |
356 | 0633879f | pbrook | } |
357 | 0633879f | pbrook | |
358 | 0633879f | pbrook | /* Internal peripherals use a variety of register widths.
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359 | 0633879f | pbrook | This lookup table allows a single routine to handle all of them. */
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360 | 5fafdf24 | ths | static const int m5206_mbar_width[] = |
361 | 0633879f | pbrook | { |
362 | 0633879f | pbrook | /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, |
363 | 0633879f | pbrook | /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2, |
364 | 0633879f | pbrook | /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, |
365 | 0633879f | pbrook | /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
366 | 0633879f | pbrook | /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0, |
367 | 0633879f | pbrook | /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
368 | 0633879f | pbrook | /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
369 | 0633879f | pbrook | /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
370 | 0633879f | pbrook | }; |
371 | 0633879f | pbrook | |
372 | 0633879f | pbrook | static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset); |
373 | 0633879f | pbrook | static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset); |
374 | 0633879f | pbrook | |
375 | 0633879f | pbrook | static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset) |
376 | 0633879f | pbrook | { |
377 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
378 | 0633879f | pbrook | offset &= 0x3ff;
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379 | 0633879f | pbrook | if (offset > 0x200) { |
380 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset); |
381 | 0633879f | pbrook | } |
382 | 0633879f | pbrook | if (m5206_mbar_width[offset >> 2] > 1) { |
383 | 0633879f | pbrook | uint16_t val; |
384 | 0633879f | pbrook | val = m5206_mbar_readw(opaque, offset & ~1);
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385 | 0633879f | pbrook | if ((offset & 1) == 0) { |
386 | 0633879f | pbrook | val >>= 8;
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387 | 0633879f | pbrook | } |
388 | 0633879f | pbrook | return val & 0xff; |
389 | 0633879f | pbrook | } |
390 | 0633879f | pbrook | return m5206_mbar_read(s, offset);
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391 | 0633879f | pbrook | } |
392 | 0633879f | pbrook | |
393 | 0633879f | pbrook | static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) |
394 | 0633879f | pbrook | { |
395 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
396 | 0633879f | pbrook | int width;
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397 | 0633879f | pbrook | offset &= 0x3ff;
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398 | 0633879f | pbrook | if (offset > 0x200) { |
399 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset); |
400 | 0633879f | pbrook | } |
401 | 0633879f | pbrook | width = m5206_mbar_width[offset >> 2];
|
402 | 0633879f | pbrook | if (width > 2) { |
403 | 0633879f | pbrook | uint32_t val; |
404 | 0633879f | pbrook | val = m5206_mbar_readl(opaque, offset & ~3);
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405 | 0633879f | pbrook | if ((offset & 3) == 0) |
406 | 0633879f | pbrook | val >>= 16;
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407 | 0633879f | pbrook | return val & 0xffff; |
408 | 0633879f | pbrook | } else if (width < 2) { |
409 | 0633879f | pbrook | uint16_t val; |
410 | 0633879f | pbrook | val = m5206_mbar_readb(opaque, offset) << 8;
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411 | 0633879f | pbrook | val |= m5206_mbar_readb(opaque, offset + 1);
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412 | 0633879f | pbrook | return val;
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413 | 0633879f | pbrook | } |
414 | 0633879f | pbrook | return m5206_mbar_read(s, offset);
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415 | 0633879f | pbrook | } |
416 | 0633879f | pbrook | |
417 | 0633879f | pbrook | static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) |
418 | 0633879f | pbrook | { |
419 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
420 | 0633879f | pbrook | int width;
|
421 | 0633879f | pbrook | offset &= 0x3ff;
|
422 | 0633879f | pbrook | if (offset > 0x200) { |
423 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset); |
424 | 0633879f | pbrook | } |
425 | 0633879f | pbrook | width = m5206_mbar_width[offset >> 2];
|
426 | 0633879f | pbrook | if (width < 4) { |
427 | 0633879f | pbrook | uint32_t val; |
428 | 0633879f | pbrook | val = m5206_mbar_readw(opaque, offset) << 16;
|
429 | 0633879f | pbrook | val |= m5206_mbar_readw(opaque, offset + 2);
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430 | 0633879f | pbrook | return val;
|
431 | 0633879f | pbrook | } |
432 | 0633879f | pbrook | return m5206_mbar_read(s, offset);
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433 | 0633879f | pbrook | } |
434 | 0633879f | pbrook | |
435 | 0633879f | pbrook | static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, |
436 | 0633879f | pbrook | uint32_t value); |
437 | 0633879f | pbrook | static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, |
438 | 0633879f | pbrook | uint32_t value); |
439 | 0633879f | pbrook | |
440 | 0633879f | pbrook | static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset, |
441 | 0633879f | pbrook | uint32_t value) |
442 | 0633879f | pbrook | { |
443 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
444 | 0633879f | pbrook | int width;
|
445 | 0633879f | pbrook | offset &= 0x3ff;
|
446 | 0633879f | pbrook | if (offset > 0x200) { |
447 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset); |
448 | 0633879f | pbrook | } |
449 | 0633879f | pbrook | width = m5206_mbar_width[offset >> 2];
|
450 | 0633879f | pbrook | if (width > 1) { |
451 | 0633879f | pbrook | uint32_t tmp; |
452 | 0633879f | pbrook | tmp = m5206_mbar_readw(opaque, offset & ~1);
|
453 | 0633879f | pbrook | if (offset & 1) { |
454 | 0633879f | pbrook | tmp = (tmp & 0xff00) | value;
|
455 | 0633879f | pbrook | } else {
|
456 | 0633879f | pbrook | tmp = (tmp & 0x00ff) | (value << 8); |
457 | 0633879f | pbrook | } |
458 | 0633879f | pbrook | m5206_mbar_writew(opaque, offset & ~1, tmp);
|
459 | 0633879f | pbrook | return;
|
460 | 0633879f | pbrook | } |
461 | 0633879f | pbrook | m5206_mbar_write(s, offset, value); |
462 | 0633879f | pbrook | } |
463 | 0633879f | pbrook | |
464 | 0633879f | pbrook | static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, |
465 | 0633879f | pbrook | uint32_t value) |
466 | 0633879f | pbrook | { |
467 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
468 | 0633879f | pbrook | int width;
|
469 | 0633879f | pbrook | offset &= 0x3ff;
|
470 | 0633879f | pbrook | if (offset > 0x200) { |
471 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset); |
472 | 0633879f | pbrook | } |
473 | 0633879f | pbrook | width = m5206_mbar_width[offset >> 2];
|
474 | 0633879f | pbrook | if (width > 2) { |
475 | 0633879f | pbrook | uint32_t tmp; |
476 | 0633879f | pbrook | tmp = m5206_mbar_readl(opaque, offset & ~3);
|
477 | 0633879f | pbrook | if (offset & 3) { |
478 | 0633879f | pbrook | tmp = (tmp & 0xffff0000) | value;
|
479 | 0633879f | pbrook | } else {
|
480 | 0633879f | pbrook | tmp = (tmp & 0x0000ffff) | (value << 16); |
481 | 0633879f | pbrook | } |
482 | 0633879f | pbrook | m5206_mbar_writel(opaque, offset & ~3, tmp);
|
483 | 0633879f | pbrook | return;
|
484 | 0633879f | pbrook | } else if (width < 2) { |
485 | 0633879f | pbrook | m5206_mbar_writeb(opaque, offset, value >> 8);
|
486 | 0633879f | pbrook | m5206_mbar_writeb(opaque, offset + 1, value & 0xff); |
487 | 0633879f | pbrook | return;
|
488 | 0633879f | pbrook | } |
489 | 0633879f | pbrook | m5206_mbar_write(s, offset, value); |
490 | 0633879f | pbrook | } |
491 | 0633879f | pbrook | |
492 | 0633879f | pbrook | static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, |
493 | 0633879f | pbrook | uint32_t value) |
494 | 0633879f | pbrook | { |
495 | 0633879f | pbrook | m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
496 | 0633879f | pbrook | int width;
|
497 | 0633879f | pbrook | offset &= 0x3ff;
|
498 | 0633879f | pbrook | if (offset > 0x200) { |
499 | 0633879f | pbrook | cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset); |
500 | 0633879f | pbrook | } |
501 | 0633879f | pbrook | width = m5206_mbar_width[offset >> 2];
|
502 | 0633879f | pbrook | if (width < 4) { |
503 | 0633879f | pbrook | m5206_mbar_writew(opaque, offset, value >> 16);
|
504 | 0633879f | pbrook | m5206_mbar_writew(opaque, offset + 2, value & 0xffff); |
505 | 0633879f | pbrook | return;
|
506 | 0633879f | pbrook | } |
507 | 0633879f | pbrook | m5206_mbar_write(s, offset, value); |
508 | 0633879f | pbrook | } |
509 | 0633879f | pbrook | |
510 | 0633879f | pbrook | static CPUReadMemoryFunc *m5206_mbar_readfn[] = {
|
511 | 0633879f | pbrook | m5206_mbar_readb, |
512 | 0633879f | pbrook | m5206_mbar_readw, |
513 | 0633879f | pbrook | m5206_mbar_readl |
514 | 0633879f | pbrook | }; |
515 | 0633879f | pbrook | |
516 | 0633879f | pbrook | static CPUWriteMemoryFunc *m5206_mbar_writefn[] = {
|
517 | 0633879f | pbrook | m5206_mbar_writeb, |
518 | 0633879f | pbrook | m5206_mbar_writew, |
519 | 0633879f | pbrook | m5206_mbar_writel |
520 | 0633879f | pbrook | }; |
521 | 0633879f | pbrook | |
522 | 0633879f | pbrook | qemu_irq *mcf5206_init(uint32_t base, CPUState *env) |
523 | 0633879f | pbrook | { |
524 | 0633879f | pbrook | m5206_mbar_state *s; |
525 | 0633879f | pbrook | qemu_irq *pic; |
526 | 0633879f | pbrook | int iomemtype;
|
527 | 0633879f | pbrook | |
528 | 0633879f | pbrook | s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
|
529 | 0633879f | pbrook | iomemtype = cpu_register_io_memory(0, m5206_mbar_readfn,
|
530 | 0633879f | pbrook | m5206_mbar_writefn, s); |
531 | 20dcee94 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
532 | 0633879f | pbrook | |
533 | 0633879f | pbrook | pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
|
534 | 0633879f | pbrook | s->timer[0] = m5206_timer_init(pic[9]); |
535 | 0633879f | pbrook | s->timer[1] = m5206_timer_init(pic[10]); |
536 | 20dcee94 | pbrook | s->uart[0] = mcf_uart_init(pic[12], serial_hds[0]); |
537 | 20dcee94 | pbrook | s->uart[1] = mcf_uart_init(pic[13], serial_hds[1]); |
538 | 0633879f | pbrook | s->env = env; |
539 | 0633879f | pbrook | |
540 | 0633879f | pbrook | m5206_mbar_reset(s); |
541 | 0633879f | pbrook | return pic;
|
542 | 0633879f | pbrook | } |