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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #ifndef _CPU_SH4_H
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21 | fdf9b3e8 | bellard | #define _CPU_SH4_H
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22 | fdf9b3e8 | bellard | |
23 | fdf9b3e8 | bellard | #include "config.h" |
24 | fdf9b3e8 | bellard | |
25 | fdf9b3e8 | bellard | #define TARGET_LONG_BITS 32 |
26 | fdf9b3e8 | bellard | #define TARGET_HAS_ICE 1 |
27 | fdf9b3e8 | bellard | |
28 | 9042c0e2 | ths | #define ELF_MACHINE EM_SH
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29 | 9042c0e2 | ths | |
30 | fdf9b3e8 | bellard | #include "cpu-defs.h" |
31 | fdf9b3e8 | bellard | |
32 | eda9b09b | bellard | #include "softfloat.h" |
33 | eda9b09b | bellard | |
34 | fdf9b3e8 | bellard | #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
35 | fdf9b3e8 | bellard | |
36 | fdf9b3e8 | bellard | #define SR_MD (1 << 30) |
37 | fdf9b3e8 | bellard | #define SR_RB (1 << 29) |
38 | fdf9b3e8 | bellard | #define SR_BL (1 << 28) |
39 | fdf9b3e8 | bellard | #define SR_FD (1 << 15) |
40 | fdf9b3e8 | bellard | #define SR_M (1 << 9) |
41 | fdf9b3e8 | bellard | #define SR_Q (1 << 8) |
42 | fdf9b3e8 | bellard | #define SR_S (1 << 1) |
43 | fdf9b3e8 | bellard | #define SR_T (1 << 0) |
44 | fdf9b3e8 | bellard | |
45 | fdf9b3e8 | bellard | #define FPSCR_FR (1 << 21) |
46 | fdf9b3e8 | bellard | #define FPSCR_SZ (1 << 20) |
47 | fdf9b3e8 | bellard | #define FPSCR_PR (1 << 19) |
48 | fdf9b3e8 | bellard | #define FPSCR_DN (1 << 18) |
49 | 823029f9 | ths | #define DELAY_SLOT (1 << 0) |
50 | fdf9b3e8 | bellard | #define DELAY_SLOT_CONDITIONAL (1 << 1) |
51 | 823029f9 | ths | #define DELAY_SLOT_TRUE (1 << 2) |
52 | 823029f9 | ths | #define DELAY_SLOT_CLEARME (1 << 3) |
53 | 823029f9 | ths | /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
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54 | 823029f9 | ths | * after the delay slot should be taken or not. It is calculated from SR_T.
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55 | 823029f9 | ths | *
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56 | 823029f9 | ths | * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
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57 | 823029f9 | ths | * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
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58 | 823029f9 | ths | */
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59 | fdf9b3e8 | bellard | |
60 | fdf9b3e8 | bellard | /* XXXXX The structure could be made more compact */
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61 | fdf9b3e8 | bellard | typedef struct tlb_t { |
62 | fdf9b3e8 | bellard | uint8_t asid; /* address space identifier */
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63 | fdf9b3e8 | bellard | uint32_t vpn; /* virtual page number */
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64 | fdf9b3e8 | bellard | uint8_t v; /* validity */
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65 | fdf9b3e8 | bellard | uint32_t ppn; /* physical page number */
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66 | fdf9b3e8 | bellard | uint8_t sz; /* page size */
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67 | fdf9b3e8 | bellard | uint32_t size; /* cached page size in bytes */
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68 | fdf9b3e8 | bellard | uint8_t sh; /* share status */
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69 | fdf9b3e8 | bellard | uint8_t c; /* cacheability */
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70 | fdf9b3e8 | bellard | uint8_t pr; /* protection key */
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71 | fdf9b3e8 | bellard | uint8_t d; /* dirty */
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72 | fdf9b3e8 | bellard | uint8_t wt; /* write through */
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73 | fdf9b3e8 | bellard | uint8_t sa; /* space attribute (PCMCIA) */
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74 | fdf9b3e8 | bellard | uint8_t tc; /* timing control */
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75 | fdf9b3e8 | bellard | } tlb_t; |
76 | fdf9b3e8 | bellard | |
77 | fdf9b3e8 | bellard | #define UTLB_SIZE 64 |
78 | fdf9b3e8 | bellard | #define ITLB_SIZE 4 |
79 | fdf9b3e8 | bellard | |
80 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
81 | 6ebbf390 | j_mayer | |
82 | fdf9b3e8 | bellard | typedef struct CPUSH4State { |
83 | fdf9b3e8 | bellard | uint32_t flags; /* general execution flags */
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84 | fdf9b3e8 | bellard | uint32_t gregs[24]; /* general registers */ |
85 | e04ea3dc | ths | float32 fregs[32]; /* floating point registers */ |
86 | fdf9b3e8 | bellard | uint32_t sr; /* status register */
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87 | fdf9b3e8 | bellard | uint32_t ssr; /* saved status register */
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88 | fdf9b3e8 | bellard | uint32_t spc; /* saved program counter */
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89 | fdf9b3e8 | bellard | uint32_t gbr; /* global base register */
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90 | fdf9b3e8 | bellard | uint32_t vbr; /* vector base register */
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91 | fdf9b3e8 | bellard | uint32_t sgr; /* saved global register 15 */
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92 | fdf9b3e8 | bellard | uint32_t dbr; /* debug base register */
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93 | fdf9b3e8 | bellard | uint32_t pc; /* program counter */
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94 | fdf9b3e8 | bellard | uint32_t delayed_pc; /* target of delayed jump */
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95 | fdf9b3e8 | bellard | uint32_t mach; /* multiply and accumulate high */
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96 | fdf9b3e8 | bellard | uint32_t macl; /* multiply and accumulate low */
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97 | fdf9b3e8 | bellard | uint32_t pr; /* procedure register */
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98 | fdf9b3e8 | bellard | uint32_t fpscr; /* floating point status/control register */
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99 | fdf9b3e8 | bellard | uint32_t fpul; /* floating point communication register */
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100 | fdf9b3e8 | bellard | |
101 | eda9b09b | bellard | /* temporary float registers */
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102 | eda9b09b | bellard | float32 ft0, ft1; |
103 | eda9b09b | bellard | float64 dt0, dt1; |
104 | ea6cf6be | ths | float_status fp_status; |
105 | eda9b09b | bellard | |
106 | fdf9b3e8 | bellard | /* Those belong to the specific unit (SH7750) but are handled here */
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107 | fdf9b3e8 | bellard | uint32_t mmucr; /* MMU control register */
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108 | fdf9b3e8 | bellard | uint32_t pteh; /* page table entry high register */
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109 | fdf9b3e8 | bellard | uint32_t ptel; /* page table entry low register */
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110 | fdf9b3e8 | bellard | uint32_t ptea; /* page table entry assistance register */
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111 | fdf9b3e8 | bellard | uint32_t ttb; /* tranlation table base register */
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112 | fdf9b3e8 | bellard | uint32_t tea; /* TLB exception address register */
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113 | fdf9b3e8 | bellard | uint32_t tra; /* TRAPA exception register */
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114 | fdf9b3e8 | bellard | uint32_t expevt; /* exception event register */
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115 | fdf9b3e8 | bellard | uint32_t intevt; /* interrupt event register */
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116 | fdf9b3e8 | bellard | |
117 | fdf9b3e8 | bellard | jmp_buf jmp_env; |
118 | fdf9b3e8 | bellard | int user_mode_only;
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119 | fdf9b3e8 | bellard | int interrupt_request;
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120 | d10927f8 | ths | int halted;
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121 | fdf9b3e8 | bellard | int exception_index;
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122 | fdf9b3e8 | bellard | CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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123 | fdf9b3e8 | bellard | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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124 | e96e2044 | ths | void *intc_handle;
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125 | fdf9b3e8 | bellard | } CPUSH4State; |
126 | fdf9b3e8 | bellard | |
127 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model); |
128 | fdf9b3e8 | bellard | int cpu_sh4_exec(CPUSH4State * s);
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129 | 5fafdf24 | ths | int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
130 | 5a7b542b | ths | void *puc);
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131 | fdf9b3e8 | bellard | |
132 | fdf9b3e8 | bellard | #include "softfloat.h" |
133 | fdf9b3e8 | bellard | |
134 | 9467d44c | ths | #define CPUState CPUSH4State
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135 | 9467d44c | ths | #define cpu_init cpu_sh4_init
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136 | 9467d44c | ths | #define cpu_exec cpu_sh4_exec
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137 | 9467d44c | ths | #define cpu_gen_code cpu_sh4_gen_code
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138 | 9467d44c | ths | #define cpu_signal_handler cpu_sh4_signal_handler
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139 | 9467d44c | ths | |
140 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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141 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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142 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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143 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
144 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
145 | 6ebbf390 | j_mayer | { |
146 | 6ebbf390 | j_mayer | return (env->sr & SR_MD) == 0 ? 1 : 0; |
147 | 6ebbf390 | j_mayer | } |
148 | 6ebbf390 | j_mayer | |
149 | fdf9b3e8 | bellard | #include "cpu-all.h" |
150 | fdf9b3e8 | bellard | |
151 | fdf9b3e8 | bellard | /* Memory access type */
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152 | fdf9b3e8 | bellard | enum {
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153 | fdf9b3e8 | bellard | /* Privilege */
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154 | fdf9b3e8 | bellard | ACCESS_PRIV = 0x01,
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155 | fdf9b3e8 | bellard | /* Direction */
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156 | fdf9b3e8 | bellard | ACCESS_WRITE = 0x02,
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157 | fdf9b3e8 | bellard | /* Type of instruction */
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158 | fdf9b3e8 | bellard | ACCESS_CODE = 0x10,
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159 | fdf9b3e8 | bellard | ACCESS_INT = 0x20
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160 | fdf9b3e8 | bellard | }; |
161 | fdf9b3e8 | bellard | |
162 | fdf9b3e8 | bellard | /* MMU control register */
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163 | fdf9b3e8 | bellard | #define MMUCR 0x1F000010 |
164 | fdf9b3e8 | bellard | #define MMUCR_AT (1<<0) |
165 | fdf9b3e8 | bellard | #define MMUCR_SV (1<<8) |
166 | ea2b542a | aurel32 | #define MMUCR_URC_BITS (6) |
167 | ea2b542a | aurel32 | #define MMUCR_URC_OFFSET (10) |
168 | ea2b542a | aurel32 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
169 | ea2b542a | aurel32 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
170 | ea2b542a | aurel32 | static inline int cpu_mmucr_urc (uint32_t mmucr) |
171 | ea2b542a | aurel32 | { |
172 | ea2b542a | aurel32 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
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173 | ea2b542a | aurel32 | } |
174 | ea2b542a | aurel32 | |
175 | ea2b542a | aurel32 | /* PTEH : Page Translation Entry High register */
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176 | ea2b542a | aurel32 | #define PTEH_ASID_BITS (8) |
177 | ea2b542a | aurel32 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
178 | ea2b542a | aurel32 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
179 | ea2b542a | aurel32 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
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180 | ea2b542a | aurel32 | #define PTEH_VPN_BITS (22) |
181 | ea2b542a | aurel32 | #define PTEH_VPN_OFFSET (10) |
182 | ea2b542a | aurel32 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
183 | ea2b542a | aurel32 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
184 | ea2b542a | aurel32 | static inline int cpu_pteh_vpn (uint32_t pteh) |
185 | ea2b542a | aurel32 | { |
186 | ea2b542a | aurel32 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
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187 | ea2b542a | aurel32 | } |
188 | ea2b542a | aurel32 | |
189 | ea2b542a | aurel32 | /* PTEL : Page Translation Entry Low register */
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190 | ea2b542a | aurel32 | #define PTEL_V (1 << 8) |
191 | ea2b542a | aurel32 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
192 | ea2b542a | aurel32 | #define PTEL_C (1 << 3) |
193 | ea2b542a | aurel32 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
194 | ea2b542a | aurel32 | #define PTEL_D (1 << 2) |
195 | ea2b542a | aurel32 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
196 | ea2b542a | aurel32 | #define PTEL_SH (1 << 1) |
197 | ea2b542a | aurel32 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
198 | ea2b542a | aurel32 | #define PTEL_WT (1 << 0) |
199 | ea2b542a | aurel32 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
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200 | ea2b542a | aurel32 | |
201 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH_OFFSET (7) |
202 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
203 | ea2b542a | aurel32 | #define PTEL_SZ_LOW_OFFSET (4) |
204 | ea2b542a | aurel32 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
205 | ea2b542a | aurel32 | static inline int cpu_ptel_sz (uint32_t ptel) |
206 | ea2b542a | aurel32 | { |
207 | ea2b542a | aurel32 | int sz;
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208 | ea2b542a | aurel32 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
209 | ea2b542a | aurel32 | sz <<= 1;
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210 | ea2b542a | aurel32 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
211 | ea2b542a | aurel32 | return sz;
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212 | ea2b542a | aurel32 | } |
213 | ea2b542a | aurel32 | |
214 | ea2b542a | aurel32 | #define PTEL_PPN_BITS (19) |
215 | ea2b542a | aurel32 | #define PTEL_PPN_OFFSET (10) |
216 | ea2b542a | aurel32 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
217 | ea2b542a | aurel32 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
218 | ea2b542a | aurel32 | static inline int cpu_ptel_ppn (uint32_t ptel) |
219 | ea2b542a | aurel32 | { |
220 | ea2b542a | aurel32 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
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221 | ea2b542a | aurel32 | } |
222 | ea2b542a | aurel32 | |
223 | ea2b542a | aurel32 | #define PTEL_PR_BITS (2) |
224 | ea2b542a | aurel32 | #define PTEL_PR_OFFSET (5) |
225 | ea2b542a | aurel32 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
226 | ea2b542a | aurel32 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
227 | ea2b542a | aurel32 | static inline int cpu_ptel_pr (uint32_t ptel) |
228 | ea2b542a | aurel32 | { |
229 | ea2b542a | aurel32 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
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230 | ea2b542a | aurel32 | } |
231 | ea2b542a | aurel32 | |
232 | ea2b542a | aurel32 | /* PTEA : Page Translation Entry Assistance register */
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233 | ea2b542a | aurel32 | #define PTEA_SA_BITS (3) |
234 | ea2b542a | aurel32 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
235 | ea2b542a | aurel32 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
236 | ea2b542a | aurel32 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
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237 | ea2b542a | aurel32 | #define PTEA_TC (1 << 3) |
238 | ea2b542a | aurel32 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
239 | fdf9b3e8 | bellard | |
240 | fdf9b3e8 | bellard | #endif /* _CPU_SH4_H */ |