root / target-sh4 / op.c @ 5439779e
History | View | Annotate | Download (17.2 kB)
1 | fdf9b3e8 | bellard | /*
|
---|---|---|---|
2 | fdf9b3e8 | bellard | * SH4 emulation
|
3 | 5fafdf24 | ths | *
|
4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
|
5 | fdf9b3e8 | bellard | *
|
6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
|
7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
|
9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | fdf9b3e8 | bellard | *
|
11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
|
15 | fdf9b3e8 | bellard | *
|
16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
|
18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | fdf9b3e8 | bellard | */
|
20 | fdf9b3e8 | bellard | #include "exec.h" |
21 | fdf9b3e8 | bellard | |
22 | fdf9b3e8 | bellard | static inline void set_t(void) |
23 | fdf9b3e8 | bellard | { |
24 | fdf9b3e8 | bellard | env->sr |= SR_T; |
25 | fdf9b3e8 | bellard | } |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | static inline void clr_t(void) |
28 | fdf9b3e8 | bellard | { |
29 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
30 | fdf9b3e8 | bellard | } |
31 | fdf9b3e8 | bellard | |
32 | fdf9b3e8 | bellard | static inline void cond_t(int cond) |
33 | fdf9b3e8 | bellard | { |
34 | fdf9b3e8 | bellard | if (cond)
|
35 | fdf9b3e8 | bellard | set_t(); |
36 | fdf9b3e8 | bellard | else
|
37 | fdf9b3e8 | bellard | clr_t(); |
38 | fdf9b3e8 | bellard | } |
39 | fdf9b3e8 | bellard | |
40 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T0(void) |
41 | fdf9b3e8 | bellard | { |
42 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
43 | fdf9b3e8 | bellard | RETURN(); |
44 | fdf9b3e8 | bellard | } |
45 | fdf9b3e8 | bellard | |
46 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T1(void) |
47 | fdf9b3e8 | bellard | { |
48 | 24988dc2 | aurel32 | T1 = (uint32_t) PARAM1; |
49 | fdf9b3e8 | bellard | RETURN(); |
50 | fdf9b3e8 | bellard | } |
51 | fdf9b3e8 | bellard | |
52 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_imm_T0(void) |
53 | fdf9b3e8 | bellard | { |
54 | fdf9b3e8 | bellard | cond_t((int32_t) T0 == (int32_t) PARAM1); |
55 | fdf9b3e8 | bellard | RETURN(); |
56 | fdf9b3e8 | bellard | } |
57 | fdf9b3e8 | bellard | |
58 | fdf9b3e8 | bellard | void OPPROTO op_cmd_eq_T0_T1(void) |
59 | fdf9b3e8 | bellard | { |
60 | fdf9b3e8 | bellard | cond_t(T0 == T1); |
61 | fdf9b3e8 | bellard | RETURN(); |
62 | fdf9b3e8 | bellard | } |
63 | fdf9b3e8 | bellard | |
64 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hs_T0_T1(void) |
65 | fdf9b3e8 | bellard | { |
66 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 <= (uint32_t) T1); |
67 | fdf9b3e8 | bellard | RETURN(); |
68 | fdf9b3e8 | bellard | } |
69 | fdf9b3e8 | bellard | |
70 | fdf9b3e8 | bellard | void OPPROTO op_cmd_ge_T0_T1(void) |
71 | fdf9b3e8 | bellard | { |
72 | fdf9b3e8 | bellard | cond_t((int32_t) T0 <= (int32_t) T1); |
73 | fdf9b3e8 | bellard | RETURN(); |
74 | fdf9b3e8 | bellard | } |
75 | fdf9b3e8 | bellard | |
76 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hi_T0_T1(void) |
77 | fdf9b3e8 | bellard | { |
78 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 < (uint32_t) T1); |
79 | fdf9b3e8 | bellard | RETURN(); |
80 | fdf9b3e8 | bellard | } |
81 | fdf9b3e8 | bellard | |
82 | fdf9b3e8 | bellard | void OPPROTO op_cmd_gt_T0_T1(void) |
83 | fdf9b3e8 | bellard | { |
84 | fdf9b3e8 | bellard | cond_t((int32_t) T0 < (int32_t) T1); |
85 | fdf9b3e8 | bellard | RETURN(); |
86 | fdf9b3e8 | bellard | } |
87 | fdf9b3e8 | bellard | |
88 | fdf9b3e8 | bellard | void OPPROTO op_not_T0(void) |
89 | fdf9b3e8 | bellard | { |
90 | fdf9b3e8 | bellard | T0 = ~T0; |
91 | fdf9b3e8 | bellard | RETURN(); |
92 | fdf9b3e8 | bellard | } |
93 | fdf9b3e8 | bellard | |
94 | fdf9b3e8 | bellard | void OPPROTO op_bf_s(void) |
95 | fdf9b3e8 | bellard | { |
96 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
97 | 823029f9 | ths | if (!(env->sr & SR_T)) {
|
98 | 823029f9 | ths | env->flags |= DELAY_SLOT_TRUE; |
99 | 823029f9 | ths | } |
100 | fdf9b3e8 | bellard | RETURN(); |
101 | fdf9b3e8 | bellard | } |
102 | fdf9b3e8 | bellard | |
103 | fdf9b3e8 | bellard | void OPPROTO op_bt_s(void) |
104 | fdf9b3e8 | bellard | { |
105 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
106 | 823029f9 | ths | if (env->sr & SR_T) {
|
107 | 823029f9 | ths | env->flags |= DELAY_SLOT_TRUE; |
108 | 823029f9 | ths | } |
109 | 823029f9 | ths | RETURN(); |
110 | 823029f9 | ths | } |
111 | 823029f9 | ths | |
112 | 823029f9 | ths | void OPPROTO op_store_flags(void) |
113 | 823029f9 | ths | { |
114 | 823029f9 | ths | env->flags &= DELAY_SLOT_TRUE; |
115 | 823029f9 | ths | env->flags |= PARAM1; |
116 | fdf9b3e8 | bellard | RETURN(); |
117 | fdf9b3e8 | bellard | } |
118 | fdf9b3e8 | bellard | |
119 | fdf9b3e8 | bellard | void OPPROTO op_bra(void) |
120 | fdf9b3e8 | bellard | { |
121 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
122 | fdf9b3e8 | bellard | RETURN(); |
123 | fdf9b3e8 | bellard | } |
124 | fdf9b3e8 | bellard | |
125 | fdf9b3e8 | bellard | void OPPROTO op_braf_T0(void) |
126 | fdf9b3e8 | bellard | { |
127 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
128 | fdf9b3e8 | bellard | RETURN(); |
129 | fdf9b3e8 | bellard | } |
130 | fdf9b3e8 | bellard | |
131 | fdf9b3e8 | bellard | void OPPROTO op_bsr(void) |
132 | fdf9b3e8 | bellard | { |
133 | fdf9b3e8 | bellard | env->pr = PARAM1; |
134 | fdf9b3e8 | bellard | env->delayed_pc = PARAM2; |
135 | fdf9b3e8 | bellard | RETURN(); |
136 | fdf9b3e8 | bellard | } |
137 | fdf9b3e8 | bellard | |
138 | fdf9b3e8 | bellard | void OPPROTO op_bsrf_T0(void) |
139 | fdf9b3e8 | bellard | { |
140 | fdf9b3e8 | bellard | env->pr = PARAM1; |
141 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
142 | fdf9b3e8 | bellard | RETURN(); |
143 | fdf9b3e8 | bellard | } |
144 | fdf9b3e8 | bellard | |
145 | fdf9b3e8 | bellard | void OPPROTO op_jsr_T0(void) |
146 | fdf9b3e8 | bellard | { |
147 | fdf9b3e8 | bellard | env->pr = PARAM1; |
148 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
149 | fdf9b3e8 | bellard | RETURN(); |
150 | fdf9b3e8 | bellard | } |
151 | fdf9b3e8 | bellard | |
152 | fdf9b3e8 | bellard | void OPPROTO op_rts(void) |
153 | fdf9b3e8 | bellard | { |
154 | fdf9b3e8 | bellard | env->delayed_pc = env->pr; |
155 | fdf9b3e8 | bellard | RETURN(); |
156 | fdf9b3e8 | bellard | } |
157 | fdf9b3e8 | bellard | |
158 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T0(void) |
159 | fdf9b3e8 | bellard | { |
160 | fdf9b3e8 | bellard | T0 += PARAM1; |
161 | fdf9b3e8 | bellard | RETURN(); |
162 | fdf9b3e8 | bellard | } |
163 | fdf9b3e8 | bellard | |
164 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T1(void) |
165 | fdf9b3e8 | bellard | { |
166 | fdf9b3e8 | bellard | T1 += PARAM1; |
167 | fdf9b3e8 | bellard | RETURN(); |
168 | fdf9b3e8 | bellard | } |
169 | fdf9b3e8 | bellard | |
170 | fdf9b3e8 | bellard | void OPPROTO op_clrmac(void) |
171 | fdf9b3e8 | bellard | { |
172 | fdf9b3e8 | bellard | env->mach = env->macl = 0;
|
173 | fdf9b3e8 | bellard | RETURN(); |
174 | fdf9b3e8 | bellard | } |
175 | fdf9b3e8 | bellard | |
176 | fdf9b3e8 | bellard | void OPPROTO op_clrs(void) |
177 | fdf9b3e8 | bellard | { |
178 | fdf9b3e8 | bellard | env->sr &= ~SR_S; |
179 | fdf9b3e8 | bellard | RETURN(); |
180 | fdf9b3e8 | bellard | } |
181 | fdf9b3e8 | bellard | |
182 | fdf9b3e8 | bellard | void OPPROTO op_clrt(void) |
183 | fdf9b3e8 | bellard | { |
184 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
185 | fdf9b3e8 | bellard | RETURN(); |
186 | fdf9b3e8 | bellard | } |
187 | fdf9b3e8 | bellard | |
188 | ea2b542a | aurel32 | void OPPROTO op_ldtlb(void) |
189 | ea2b542a | aurel32 | { |
190 | ea2b542a | aurel32 | helper_ldtlb(); |
191 | ea2b542a | aurel32 | RETURN(); |
192 | ea2b542a | aurel32 | } |
193 | ea2b542a | aurel32 | |
194 | fdf9b3e8 | bellard | void OPPROTO op_sets(void) |
195 | fdf9b3e8 | bellard | { |
196 | fdf9b3e8 | bellard | env->sr |= SR_S; |
197 | fdf9b3e8 | bellard | RETURN(); |
198 | fdf9b3e8 | bellard | } |
199 | fdf9b3e8 | bellard | |
200 | fdf9b3e8 | bellard | void OPPROTO op_sett(void) |
201 | fdf9b3e8 | bellard | { |
202 | fdf9b3e8 | bellard | env->sr |= SR_T; |
203 | fdf9b3e8 | bellard | RETURN(); |
204 | fdf9b3e8 | bellard | } |
205 | fdf9b3e8 | bellard | |
206 | eda9b09b | bellard | void OPPROTO op_frchg(void) |
207 | eda9b09b | bellard | { |
208 | eda9b09b | bellard | env->fpscr ^= FPSCR_FR; |
209 | eda9b09b | bellard | RETURN(); |
210 | eda9b09b | bellard | } |
211 | eda9b09b | bellard | |
212 | eda9b09b | bellard | void OPPROTO op_fschg(void) |
213 | eda9b09b | bellard | { |
214 | eda9b09b | bellard | env->fpscr ^= FPSCR_SZ; |
215 | eda9b09b | bellard | RETURN(); |
216 | eda9b09b | bellard | } |
217 | eda9b09b | bellard | |
218 | fdf9b3e8 | bellard | void OPPROTO op_rte(void) |
219 | fdf9b3e8 | bellard | { |
220 | fdf9b3e8 | bellard | env->sr = env->ssr; |
221 | fdf9b3e8 | bellard | env->delayed_pc = env->spc; |
222 | fdf9b3e8 | bellard | RETURN(); |
223 | fdf9b3e8 | bellard | } |
224 | fdf9b3e8 | bellard | |
225 | fdf9b3e8 | bellard | void OPPROTO op_swapb_T0(void) |
226 | fdf9b3e8 | bellard | { |
227 | fdf9b3e8 | bellard | T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); |
228 | fdf9b3e8 | bellard | RETURN(); |
229 | fdf9b3e8 | bellard | } |
230 | fdf9b3e8 | bellard | |
231 | fdf9b3e8 | bellard | void OPPROTO op_swapw_T0(void) |
232 | fdf9b3e8 | bellard | { |
233 | fdf9b3e8 | bellard | T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); |
234 | fdf9b3e8 | bellard | RETURN(); |
235 | fdf9b3e8 | bellard | } |
236 | fdf9b3e8 | bellard | |
237 | fdf9b3e8 | bellard | void OPPROTO op_xtrct_T0_T1(void) |
238 | fdf9b3e8 | bellard | { |
239 | fdf9b3e8 | bellard | T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); |
240 | fdf9b3e8 | bellard | RETURN(); |
241 | fdf9b3e8 | bellard | } |
242 | fdf9b3e8 | bellard | |
243 | 24988dc2 | aurel32 | void OPPROTO op_add_T0_T1(void) |
244 | 24988dc2 | aurel32 | { |
245 | 24988dc2 | aurel32 | T1 += T0; |
246 | 24988dc2 | aurel32 | RETURN(); |
247 | 24988dc2 | aurel32 | } |
248 | 24988dc2 | aurel32 | |
249 | fdf9b3e8 | bellard | void OPPROTO op_addc_T0_T1(void) |
250 | fdf9b3e8 | bellard | { |
251 | fdf9b3e8 | bellard | helper_addc_T0_T1(); |
252 | fdf9b3e8 | bellard | RETURN(); |
253 | fdf9b3e8 | bellard | } |
254 | fdf9b3e8 | bellard | |
255 | fdf9b3e8 | bellard | void OPPROTO op_addv_T0_T1(void) |
256 | fdf9b3e8 | bellard | { |
257 | fdf9b3e8 | bellard | helper_addv_T0_T1(); |
258 | fdf9b3e8 | bellard | RETURN(); |
259 | fdf9b3e8 | bellard | } |
260 | fdf9b3e8 | bellard | |
261 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_T0_T1(void) |
262 | fdf9b3e8 | bellard | { |
263 | fdf9b3e8 | bellard | cond_t(T1 == T0); |
264 | fdf9b3e8 | bellard | RETURN(); |
265 | fdf9b3e8 | bellard | } |
266 | fdf9b3e8 | bellard | |
267 | fdf9b3e8 | bellard | void OPPROTO op_cmp_ge_T0_T1(void) |
268 | fdf9b3e8 | bellard | { |
269 | fdf9b3e8 | bellard | cond_t((int32_t) T1 >= (int32_t) T0); |
270 | fdf9b3e8 | bellard | RETURN(); |
271 | fdf9b3e8 | bellard | } |
272 | fdf9b3e8 | bellard | |
273 | fdf9b3e8 | bellard | void OPPROTO op_cmp_gt_T0_T1(void) |
274 | fdf9b3e8 | bellard | { |
275 | fdf9b3e8 | bellard | cond_t((int32_t) T1 > (int32_t) T0); |
276 | fdf9b3e8 | bellard | RETURN(); |
277 | fdf9b3e8 | bellard | } |
278 | fdf9b3e8 | bellard | |
279 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hi_T0_T1(void) |
280 | fdf9b3e8 | bellard | { |
281 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 > (uint32_t) T0); |
282 | fdf9b3e8 | bellard | RETURN(); |
283 | fdf9b3e8 | bellard | } |
284 | fdf9b3e8 | bellard | |
285 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hs_T0_T1(void) |
286 | fdf9b3e8 | bellard | { |
287 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 >= (uint32_t) T0); |
288 | fdf9b3e8 | bellard | RETURN(); |
289 | fdf9b3e8 | bellard | } |
290 | fdf9b3e8 | bellard | |
291 | fdf9b3e8 | bellard | void OPPROTO op_cmp_str_T0_T1(void) |
292 | fdf9b3e8 | bellard | { |
293 | fdf9b3e8 | bellard | cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
294 | fdf9b3e8 | bellard | (T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
295 | fdf9b3e8 | bellard | (T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
296 | fdf9b3e8 | bellard | (T0 & 0xff000000) == (T1 & 0xff000000)); |
297 | fdf9b3e8 | bellard | RETURN(); |
298 | fdf9b3e8 | bellard | } |
299 | fdf9b3e8 | bellard | |
300 | fdf9b3e8 | bellard | void OPPROTO op_tst_T0_T1(void) |
301 | fdf9b3e8 | bellard | { |
302 | fdf9b3e8 | bellard | cond_t((T1 & T0) == 0);
|
303 | fdf9b3e8 | bellard | RETURN(); |
304 | fdf9b3e8 | bellard | } |
305 | fdf9b3e8 | bellard | |
306 | fdf9b3e8 | bellard | void OPPROTO op_div0s_T0_T1(void) |
307 | fdf9b3e8 | bellard | { |
308 | fdf9b3e8 | bellard | if (T1 & 0x80000000) |
309 | fdf9b3e8 | bellard | env->sr |= SR_Q; |
310 | fdf9b3e8 | bellard | else
|
311 | fdf9b3e8 | bellard | env->sr &= ~SR_Q; |
312 | fdf9b3e8 | bellard | if (T0 & 0x80000000) |
313 | fdf9b3e8 | bellard | env->sr |= SR_M; |
314 | fdf9b3e8 | bellard | else
|
315 | fdf9b3e8 | bellard | env->sr &= ~SR_M; |
316 | fdf9b3e8 | bellard | cond_t((T1 ^ T0) & 0x80000000);
|
317 | fdf9b3e8 | bellard | RETURN(); |
318 | fdf9b3e8 | bellard | } |
319 | fdf9b3e8 | bellard | |
320 | fdf9b3e8 | bellard | void OPPROTO op_div0u(void) |
321 | fdf9b3e8 | bellard | { |
322 | fdf9b3e8 | bellard | env->sr &= ~(SR_M | SR_Q | SR_T); |
323 | fdf9b3e8 | bellard | RETURN(); |
324 | fdf9b3e8 | bellard | } |
325 | fdf9b3e8 | bellard | |
326 | fdf9b3e8 | bellard | void OPPROTO op_div1_T0_T1(void) |
327 | fdf9b3e8 | bellard | { |
328 | fdf9b3e8 | bellard | helper_div1_T0_T1(); |
329 | fdf9b3e8 | bellard | RETURN(); |
330 | fdf9b3e8 | bellard | } |
331 | fdf9b3e8 | bellard | |
332 | fdf9b3e8 | bellard | void OPPROTO op_dmulsl_T0_T1(void) |
333 | fdf9b3e8 | bellard | { |
334 | fdf9b3e8 | bellard | helper_dmulsl_T0_T1(); |
335 | fdf9b3e8 | bellard | RETURN(); |
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | void OPPROTO op_dmulul_T0_T1(void) |
339 | fdf9b3e8 | bellard | { |
340 | fdf9b3e8 | bellard | helper_dmulul_T0_T1(); |
341 | fdf9b3e8 | bellard | RETURN(); |
342 | fdf9b3e8 | bellard | } |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | void OPPROTO op_macl_T0_T1(void) |
345 | fdf9b3e8 | bellard | { |
346 | fdf9b3e8 | bellard | helper_macl_T0_T1(); |
347 | fdf9b3e8 | bellard | RETURN(); |
348 | fdf9b3e8 | bellard | } |
349 | fdf9b3e8 | bellard | |
350 | fdf9b3e8 | bellard | void OPPROTO op_macw_T0_T1(void) |
351 | fdf9b3e8 | bellard | { |
352 | fdf9b3e8 | bellard | helper_macw_T0_T1(); |
353 | fdf9b3e8 | bellard | RETURN(); |
354 | fdf9b3e8 | bellard | } |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | void OPPROTO op_mull_T0_T1(void) |
357 | fdf9b3e8 | bellard | { |
358 | fdf9b3e8 | bellard | env->macl = (T0 * T1) & 0xffffffff;
|
359 | fdf9b3e8 | bellard | RETURN(); |
360 | fdf9b3e8 | bellard | } |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | void OPPROTO op_mulsw_T0_T1(void) |
363 | fdf9b3e8 | bellard | { |
364 | 24988dc2 | aurel32 | env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1; |
365 | fdf9b3e8 | bellard | RETURN(); |
366 | fdf9b3e8 | bellard | } |
367 | fdf9b3e8 | bellard | |
368 | fdf9b3e8 | bellard | void OPPROTO op_muluw_T0_T1(void) |
369 | fdf9b3e8 | bellard | { |
370 | 24988dc2 | aurel32 | env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1; |
371 | fdf9b3e8 | bellard | RETURN(); |
372 | fdf9b3e8 | bellard | } |
373 | fdf9b3e8 | bellard | |
374 | fdf9b3e8 | bellard | void OPPROTO op_neg_T0(void) |
375 | fdf9b3e8 | bellard | { |
376 | fdf9b3e8 | bellard | T0 = -T0; |
377 | fdf9b3e8 | bellard | RETURN(); |
378 | fdf9b3e8 | bellard | } |
379 | fdf9b3e8 | bellard | |
380 | fdf9b3e8 | bellard | void OPPROTO op_negc_T0(void) |
381 | fdf9b3e8 | bellard | { |
382 | fdf9b3e8 | bellard | helper_negc_T0(); |
383 | fdf9b3e8 | bellard | RETURN(); |
384 | fdf9b3e8 | bellard | } |
385 | fdf9b3e8 | bellard | |
386 | fdf9b3e8 | bellard | void OPPROTO op_shad_T0_T1(void) |
387 | fdf9b3e8 | bellard | { |
388 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
389 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
390 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
391 | 24988dc2 | aurel32 | T1 = (T1 & 0x80000000)? 0xffffffff : 0; |
392 | fdf9b3e8 | bellard | else
|
393 | fdf9b3e8 | bellard | T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
394 | fdf9b3e8 | bellard | RETURN(); |
395 | fdf9b3e8 | bellard | } |
396 | fdf9b3e8 | bellard | |
397 | fdf9b3e8 | bellard | void OPPROTO op_shld_T0_T1(void) |
398 | fdf9b3e8 | bellard | { |
399 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
400 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
401 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
402 | fdf9b3e8 | bellard | T1 = 0;
|
403 | fdf9b3e8 | bellard | else
|
404 | fdf9b3e8 | bellard | T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
405 | fdf9b3e8 | bellard | RETURN(); |
406 | fdf9b3e8 | bellard | } |
407 | fdf9b3e8 | bellard | |
408 | fdf9b3e8 | bellard | void OPPROTO op_subc_T0_T1(void) |
409 | fdf9b3e8 | bellard | { |
410 | fdf9b3e8 | bellard | helper_subc_T0_T1(); |
411 | fdf9b3e8 | bellard | RETURN(); |
412 | fdf9b3e8 | bellard | } |
413 | fdf9b3e8 | bellard | |
414 | fdf9b3e8 | bellard | void OPPROTO op_subv_T0_T1(void) |
415 | fdf9b3e8 | bellard | { |
416 | fdf9b3e8 | bellard | helper_subv_T0_T1(); |
417 | fdf9b3e8 | bellard | RETURN(); |
418 | fdf9b3e8 | bellard | } |
419 | fdf9b3e8 | bellard | |
420 | fdf9b3e8 | bellard | void OPPROTO op_trapa(void) |
421 | fdf9b3e8 | bellard | { |
422 | e96e2044 | ths | env->tra = PARAM1 << 2;
|
423 | fdf9b3e8 | bellard | env->exception_index = 0x160;
|
424 | fdf9b3e8 | bellard | do_raise_exception(); |
425 | fdf9b3e8 | bellard | RETURN(); |
426 | fdf9b3e8 | bellard | } |
427 | fdf9b3e8 | bellard | |
428 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pl_T0(void) |
429 | fdf9b3e8 | bellard | { |
430 | fdf9b3e8 | bellard | cond_t((int32_t) T0 > 0);
|
431 | fdf9b3e8 | bellard | RETURN(); |
432 | fdf9b3e8 | bellard | } |
433 | fdf9b3e8 | bellard | |
434 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pz_T0(void) |
435 | fdf9b3e8 | bellard | { |
436 | fdf9b3e8 | bellard | cond_t((int32_t) T0 >= 0);
|
437 | fdf9b3e8 | bellard | RETURN(); |
438 | fdf9b3e8 | bellard | } |
439 | fdf9b3e8 | bellard | |
440 | fdf9b3e8 | bellard | void OPPROTO op_jmp_T0(void) |
441 | fdf9b3e8 | bellard | { |
442 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
443 | fdf9b3e8 | bellard | RETURN(); |
444 | fdf9b3e8 | bellard | } |
445 | fdf9b3e8 | bellard | |
446 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_rN(void) |
447 | fdf9b3e8 | bellard | { |
448 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
449 | fdf9b3e8 | bellard | RETURN(); |
450 | fdf9b3e8 | bellard | } |
451 | fdf9b3e8 | bellard | |
452 | fdf9b3e8 | bellard | void OPPROTO op_ldcl_rMplus_rN_bank(void) |
453 | fdf9b3e8 | bellard | { |
454 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
455 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
456 | fdf9b3e8 | bellard | RETURN(); |
457 | fdf9b3e8 | bellard | } |
458 | fdf9b3e8 | bellard | |
459 | eda9b09b | bellard | void OPPROTO op_ldc_T0_sr(void) |
460 | eda9b09b | bellard | { |
461 | eda9b09b | bellard | env->sr = T0 & 0x700083f3;
|
462 | eda9b09b | bellard | RETURN(); |
463 | eda9b09b | bellard | } |
464 | eda9b09b | bellard | |
465 | eda9b09b | bellard | void OPPROTO op_stc_sr_T0(void) |
466 | eda9b09b | bellard | { |
467 | eda9b09b | bellard | T0 = env->sr; |
468 | eda9b09b | bellard | RETURN(); |
469 | eda9b09b | bellard | } |
470 | eda9b09b | bellard | |
471 | fdf9b3e8 | bellard | #define LDSTOPS(target,load,store) \
|
472 | fdf9b3e8 | bellard | void OPPROTO op_##load##_T0_##target (void) \ |
473 | fdf9b3e8 | bellard | { env ->target = T0; RETURN(); \ |
474 | fdf9b3e8 | bellard | } \ |
475 | fdf9b3e8 | bellard | void OPPROTO op_##store##_##target##_T0 (void) \ |
476 | fdf9b3e8 | bellard | { T0 = env->target; RETURN(); \ |
477 | fdf9b3e8 | bellard | } \ |
478 | fdf9b3e8 | bellard | |
479 | fdf9b3e8 | bellard | LDSTOPS(gbr, ldc, stc) |
480 | fdf9b3e8 | bellard | LDSTOPS(vbr, ldc, stc) |
481 | fdf9b3e8 | bellard | LDSTOPS(ssr, ldc, stc) |
482 | fdf9b3e8 | bellard | LDSTOPS(spc, ldc, stc) |
483 | fdf9b3e8 | bellard | LDSTOPS(sgr, ldc, stc) |
484 | fdf9b3e8 | bellard | LDSTOPS(dbr, ldc, stc) |
485 | fdf9b3e8 | bellard | LDSTOPS(mach, lds, sts) |
486 | fdf9b3e8 | bellard | LDSTOPS(macl, lds, sts) |
487 | fdf9b3e8 | bellard | LDSTOPS(pr, lds, sts) |
488 | eda9b09b | bellard | LDSTOPS(fpul, lds, sts) |
489 | eda9b09b | bellard | |
490 | eda9b09b | bellard | void OPPROTO op_lds_T0_fpscr(void) |
491 | eda9b09b | bellard | { |
492 | eda9b09b | bellard | env->fpscr = T0 & 0x003fffff;
|
493 | ea6cf6be | ths | env->fp_status.float_rounding_mode = T0 & 0x01 ?
|
494 | ea6cf6be | ths | float_round_to_zero : float_round_nearest_even; |
495 | ea6cf6be | ths | |
496 | eda9b09b | bellard | RETURN(); |
497 | eda9b09b | bellard | } |
498 | eda9b09b | bellard | |
499 | eda9b09b | bellard | void OPPROTO op_sts_fpscr_T0(void) |
500 | eda9b09b | bellard | { |
501 | eda9b09b | bellard | T0 = env->fpscr & 0x003fffff;
|
502 | eda9b09b | bellard | RETURN(); |
503 | eda9b09b | bellard | } |
504 | fdf9b3e8 | bellard | |
505 | fdf9b3e8 | bellard | void OPPROTO op_movt_rN(void) |
506 | fdf9b3e8 | bellard | { |
507 | fdf9b3e8 | bellard | env->gregs[PARAM1] = env->sr & SR_T; |
508 | fdf9b3e8 | bellard | RETURN(); |
509 | fdf9b3e8 | bellard | } |
510 | fdf9b3e8 | bellard | |
511 | fdf9b3e8 | bellard | void OPPROTO op_rotcl_Rn(void) |
512 | fdf9b3e8 | bellard | { |
513 | fdf9b3e8 | bellard | helper_rotcl(&env->gregs[PARAM1]); |
514 | fdf9b3e8 | bellard | RETURN(); |
515 | fdf9b3e8 | bellard | } |
516 | fdf9b3e8 | bellard | |
517 | fdf9b3e8 | bellard | void OPPROTO op_rotcr_Rn(void) |
518 | fdf9b3e8 | bellard | { |
519 | fdf9b3e8 | bellard | helper_rotcr(&env->gregs[PARAM1]); |
520 | fdf9b3e8 | bellard | RETURN(); |
521 | fdf9b3e8 | bellard | } |
522 | fdf9b3e8 | bellard | |
523 | fdf9b3e8 | bellard | void OPPROTO op_rotl_Rn(void) |
524 | fdf9b3e8 | bellard | { |
525 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
526 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
527 | fdf9b3e8 | bellard | RETURN(); |
528 | fdf9b3e8 | bellard | } |
529 | fdf9b3e8 | bellard | |
530 | fdf9b3e8 | bellard | void OPPROTO op_rotr_Rn(void) |
531 | fdf9b3e8 | bellard | { |
532 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
533 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
534 | fdf9b3e8 | bellard | ((env->sr & SR_T) ? 0x80000000 : 0); |
535 | fdf9b3e8 | bellard | RETURN(); |
536 | fdf9b3e8 | bellard | } |
537 | fdf9b3e8 | bellard | |
538 | fdf9b3e8 | bellard | void OPPROTO op_shal_Rn(void) |
539 | fdf9b3e8 | bellard | { |
540 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
541 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 1;
|
542 | fdf9b3e8 | bellard | RETURN(); |
543 | fdf9b3e8 | bellard | } |
544 | fdf9b3e8 | bellard | |
545 | fdf9b3e8 | bellard | void OPPROTO op_shar_Rn(void) |
546 | fdf9b3e8 | bellard | { |
547 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
548 | 24988dc2 | aurel32 | *(int32_t *)&env->gregs[PARAM1] >>= 1;
|
549 | fdf9b3e8 | bellard | RETURN(); |
550 | fdf9b3e8 | bellard | } |
551 | fdf9b3e8 | bellard | |
552 | fdf9b3e8 | bellard | void OPPROTO op_shlr_Rn(void) |
553 | fdf9b3e8 | bellard | { |
554 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
555 | a5d251bd | ths | env->gregs[PARAM1] >>= 1;
|
556 | fdf9b3e8 | bellard | RETURN(); |
557 | fdf9b3e8 | bellard | } |
558 | fdf9b3e8 | bellard | |
559 | fdf9b3e8 | bellard | void OPPROTO op_shll2_Rn(void) |
560 | fdf9b3e8 | bellard | { |
561 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 2;
|
562 | fdf9b3e8 | bellard | RETURN(); |
563 | fdf9b3e8 | bellard | } |
564 | fdf9b3e8 | bellard | |
565 | fdf9b3e8 | bellard | void OPPROTO op_shll8_Rn(void) |
566 | fdf9b3e8 | bellard | { |
567 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 8;
|
568 | fdf9b3e8 | bellard | RETURN(); |
569 | fdf9b3e8 | bellard | } |
570 | fdf9b3e8 | bellard | |
571 | fdf9b3e8 | bellard | void OPPROTO op_shll16_Rn(void) |
572 | fdf9b3e8 | bellard | { |
573 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 16;
|
574 | fdf9b3e8 | bellard | RETURN(); |
575 | fdf9b3e8 | bellard | } |
576 | fdf9b3e8 | bellard | |
577 | fdf9b3e8 | bellard | void OPPROTO op_shlr2_Rn(void) |
578 | fdf9b3e8 | bellard | { |
579 | a5d251bd | ths | env->gregs[PARAM1] >>= 2;
|
580 | fdf9b3e8 | bellard | RETURN(); |
581 | fdf9b3e8 | bellard | } |
582 | fdf9b3e8 | bellard | |
583 | fdf9b3e8 | bellard | void OPPROTO op_shlr8_Rn(void) |
584 | fdf9b3e8 | bellard | { |
585 | a5d251bd | ths | env->gregs[PARAM1] >>= 8;
|
586 | fdf9b3e8 | bellard | RETURN(); |
587 | fdf9b3e8 | bellard | } |
588 | fdf9b3e8 | bellard | |
589 | fdf9b3e8 | bellard | void OPPROTO op_shlr16_Rn(void) |
590 | fdf9b3e8 | bellard | { |
591 | a5d251bd | ths | env->gregs[PARAM1] >>= 16;
|
592 | fdf9b3e8 | bellard | RETURN(); |
593 | fdf9b3e8 | bellard | } |
594 | fdf9b3e8 | bellard | |
595 | fdf9b3e8 | bellard | void OPPROTO op_tasb_rN(void) |
596 | fdf9b3e8 | bellard | { |
597 | fdf9b3e8 | bellard | cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
|
598 | fdf9b3e8 | bellard | *(int8_t *) env->gregs[PARAM1] |= 0x80;
|
599 | fdf9b3e8 | bellard | RETURN(); |
600 | fdf9b3e8 | bellard | } |
601 | fdf9b3e8 | bellard | |
602 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_rN(void) |
603 | fdf9b3e8 | bellard | { |
604 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T0; |
605 | fdf9b3e8 | bellard | RETURN(); |
606 | fdf9b3e8 | bellard | } |
607 | fdf9b3e8 | bellard | |
608 | fdf9b3e8 | bellard | void OPPROTO op_movl_T1_rN(void) |
609 | fdf9b3e8 | bellard | { |
610 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T1; |
611 | fdf9b3e8 | bellard | RETURN(); |
612 | fdf9b3e8 | bellard | } |
613 | fdf9b3e8 | bellard | |
614 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T0(void) |
615 | fdf9b3e8 | bellard | { |
616 | fdf9b3e8 | bellard | T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
617 | fdf9b3e8 | bellard | RETURN(); |
618 | fdf9b3e8 | bellard | } |
619 | fdf9b3e8 | bellard | |
620 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T0(void) |
621 | fdf9b3e8 | bellard | { |
622 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xff;
|
623 | fdf9b3e8 | bellard | RETURN(); |
624 | fdf9b3e8 | bellard | } |
625 | fdf9b3e8 | bellard | |
626 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T0(void) |
627 | fdf9b3e8 | bellard | { |
628 | fdf9b3e8 | bellard | T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
629 | fdf9b3e8 | bellard | RETURN(); |
630 | fdf9b3e8 | bellard | } |
631 | fdf9b3e8 | bellard | |
632 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T0(void) |
633 | fdf9b3e8 | bellard | { |
634 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xffff;
|
635 | fdf9b3e8 | bellard | RETURN(); |
636 | fdf9b3e8 | bellard | } |
637 | fdf9b3e8 | bellard | |
638 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T0(void) |
639 | fdf9b3e8 | bellard | { |
640 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1]; |
641 | fdf9b3e8 | bellard | RETURN(); |
642 | fdf9b3e8 | bellard | } |
643 | fdf9b3e8 | bellard | |
644 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T1(void) |
645 | fdf9b3e8 | bellard | { |
646 | fdf9b3e8 | bellard | T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
647 | fdf9b3e8 | bellard | RETURN(); |
648 | fdf9b3e8 | bellard | } |
649 | fdf9b3e8 | bellard | |
650 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T1(void) |
651 | fdf9b3e8 | bellard | { |
652 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xff;
|
653 | fdf9b3e8 | bellard | RETURN(); |
654 | fdf9b3e8 | bellard | } |
655 | fdf9b3e8 | bellard | |
656 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T1(void) |
657 | fdf9b3e8 | bellard | { |
658 | fdf9b3e8 | bellard | T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
659 | fdf9b3e8 | bellard | RETURN(); |
660 | fdf9b3e8 | bellard | } |
661 | fdf9b3e8 | bellard | |
662 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T1(void) |
663 | fdf9b3e8 | bellard | { |
664 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xffff;
|
665 | fdf9b3e8 | bellard | RETURN(); |
666 | fdf9b3e8 | bellard | } |
667 | fdf9b3e8 | bellard | |
668 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T1(void) |
669 | fdf9b3e8 | bellard | { |
670 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1]; |
671 | fdf9b3e8 | bellard | RETURN(); |
672 | fdf9b3e8 | bellard | } |
673 | fdf9b3e8 | bellard | |
674 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_rN(void) |
675 | fdf9b3e8 | bellard | { |
676 | fdf9b3e8 | bellard | env->gregs[PARAM2] = PARAM1; |
677 | fdf9b3e8 | bellard | RETURN(); |
678 | fdf9b3e8 | bellard | } |
679 | fdf9b3e8 | bellard | |
680 | eda9b09b | bellard | void OPPROTO op_fmov_frN_FT0(void) |
681 | eda9b09b | bellard | { |
682 | e04ea3dc | ths | FT0 = env->fregs[PARAM1]; |
683 | eda9b09b | bellard | RETURN(); |
684 | eda9b09b | bellard | } |
685 | eda9b09b | bellard | |
686 | eda9b09b | bellard | void OPPROTO op_fmov_drN_DT0(void) |
687 | eda9b09b | bellard | { |
688 | e04ea3dc | ths | CPU_DoubleU d; |
689 | e04ea3dc | ths | |
690 | e04ea3dc | ths | d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
691 | e04ea3dc | ths | d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
692 | e04ea3dc | ths | DT0 = d.d; |
693 | eda9b09b | bellard | RETURN(); |
694 | eda9b09b | bellard | } |
695 | eda9b09b | bellard | |
696 | ea6cf6be | ths | void OPPROTO op_fmov_frN_FT1(void) |
697 | ea6cf6be | ths | { |
698 | e04ea3dc | ths | FT1 = env->fregs[PARAM1]; |
699 | ea6cf6be | ths | RETURN(); |
700 | ea6cf6be | ths | } |
701 | ea6cf6be | ths | |
702 | ea6cf6be | ths | void OPPROTO op_fmov_drN_DT1(void) |
703 | ea6cf6be | ths | { |
704 | e04ea3dc | ths | CPU_DoubleU d; |
705 | e04ea3dc | ths | |
706 | e04ea3dc | ths | d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
707 | e04ea3dc | ths | d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
708 | e04ea3dc | ths | DT1 = d.d; |
709 | ea6cf6be | ths | RETURN(); |
710 | ea6cf6be | ths | } |
711 | ea6cf6be | ths | |
712 | eda9b09b | bellard | void OPPROTO op_fmov_FT0_frN(void) |
713 | eda9b09b | bellard | { |
714 | e04ea3dc | ths | env->fregs[PARAM1] = FT0; |
715 | eda9b09b | bellard | RETURN(); |
716 | eda9b09b | bellard | } |
717 | eda9b09b | bellard | |
718 | eda9b09b | bellard | void OPPROTO op_fmov_DT0_drN(void) |
719 | eda9b09b | bellard | { |
720 | e04ea3dc | ths | CPU_DoubleU d; |
721 | e04ea3dc | ths | |
722 | e04ea3dc | ths | d.d = DT0; |
723 | e04ea3dc | ths | *(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
724 | e04ea3dc | ths | *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
725 | eda9b09b | bellard | RETURN(); |
726 | eda9b09b | bellard | } |
727 | eda9b09b | bellard | |
728 | ea6cf6be | ths | void OPPROTO op_fadd_FT(void) |
729 | ea6cf6be | ths | { |
730 | ea6cf6be | ths | FT0 = float32_add(FT0, FT1, &env->fp_status); |
731 | ea6cf6be | ths | RETURN(); |
732 | ea6cf6be | ths | } |
733 | ea6cf6be | ths | |
734 | ea6cf6be | ths | void OPPROTO op_fadd_DT(void) |
735 | ea6cf6be | ths | { |
736 | ea6cf6be | ths | DT0 = float64_add(DT0, DT1, &env->fp_status); |
737 | ea6cf6be | ths | RETURN(); |
738 | ea6cf6be | ths | } |
739 | ea6cf6be | ths | |
740 | ea6cf6be | ths | void OPPROTO op_fsub_FT(void) |
741 | ea6cf6be | ths | { |
742 | ea6cf6be | ths | FT0 = float32_sub(FT0, FT1, &env->fp_status); |
743 | ea6cf6be | ths | RETURN(); |
744 | ea6cf6be | ths | } |
745 | ea6cf6be | ths | |
746 | ea6cf6be | ths | void OPPROTO op_fsub_DT(void) |
747 | ea6cf6be | ths | { |
748 | ea6cf6be | ths | DT0 = float64_sub(DT0, DT1, &env->fp_status); |
749 | ea6cf6be | ths | RETURN(); |
750 | ea6cf6be | ths | } |
751 | ea6cf6be | ths | |
752 | ea6cf6be | ths | void OPPROTO op_fmul_FT(void) |
753 | ea6cf6be | ths | { |
754 | ea6cf6be | ths | FT0 = float32_mul(FT0, FT1, &env->fp_status); |
755 | ea6cf6be | ths | RETURN(); |
756 | ea6cf6be | ths | } |
757 | ea6cf6be | ths | |
758 | ea6cf6be | ths | void OPPROTO op_fmul_DT(void) |
759 | ea6cf6be | ths | { |
760 | ea6cf6be | ths | DT0 = float64_mul(DT0, DT1, &env->fp_status); |
761 | ea6cf6be | ths | RETURN(); |
762 | ea6cf6be | ths | } |
763 | ea6cf6be | ths | |
764 | ea6cf6be | ths | void OPPROTO op_fdiv_FT(void) |
765 | ea6cf6be | ths | { |
766 | ea6cf6be | ths | FT0 = float32_div(FT0, FT1, &env->fp_status); |
767 | ea6cf6be | ths | RETURN(); |
768 | ea6cf6be | ths | } |
769 | ea6cf6be | ths | |
770 | ea6cf6be | ths | void OPPROTO op_fdiv_DT(void) |
771 | ea6cf6be | ths | { |
772 | ea6cf6be | ths | DT0 = float64_div(DT0, DT1, &env->fp_status); |
773 | ea6cf6be | ths | RETURN(); |
774 | ea6cf6be | ths | } |
775 | ea6cf6be | ths | |
776 | 24988dc2 | aurel32 | void OPPROTO op_fcmp_eq_FT(void) |
777 | 24988dc2 | aurel32 | { |
778 | 24988dc2 | aurel32 | cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
|
779 | 24988dc2 | aurel32 | RETURN(); |
780 | 24988dc2 | aurel32 | } |
781 | 24988dc2 | aurel32 | |
782 | 24988dc2 | aurel32 | void OPPROTO op_fcmp_eq_DT(void) |
783 | 24988dc2 | aurel32 | { |
784 | 24988dc2 | aurel32 | cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
|
785 | 24988dc2 | aurel32 | RETURN(); |
786 | 24988dc2 | aurel32 | } |
787 | 24988dc2 | aurel32 | |
788 | 24988dc2 | aurel32 | void OPPROTO op_fcmp_gt_FT(void) |
789 | 24988dc2 | aurel32 | { |
790 | 24988dc2 | aurel32 | cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
|
791 | 24988dc2 | aurel32 | RETURN(); |
792 | 24988dc2 | aurel32 | } |
793 | 24988dc2 | aurel32 | |
794 | 24988dc2 | aurel32 | void OPPROTO op_fcmp_gt_DT(void) |
795 | 24988dc2 | aurel32 | { |
796 | 24988dc2 | aurel32 | cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
|
797 | 24988dc2 | aurel32 | RETURN(); |
798 | 24988dc2 | aurel32 | } |
799 | 24988dc2 | aurel32 | |
800 | ea6cf6be | ths | void OPPROTO op_float_FT(void) |
801 | ea6cf6be | ths | { |
802 | ea6cf6be | ths | FT0 = int32_to_float32(env->fpul, &env->fp_status); |
803 | ea6cf6be | ths | RETURN(); |
804 | ea6cf6be | ths | } |
805 | ea6cf6be | ths | |
806 | ea6cf6be | ths | void OPPROTO op_float_DT(void) |
807 | ea6cf6be | ths | { |
808 | ea6cf6be | ths | DT0 = int32_to_float64(env->fpul, &env->fp_status); |
809 | ea6cf6be | ths | RETURN(); |
810 | ea6cf6be | ths | } |
811 | ea6cf6be | ths | |
812 | ea6cf6be | ths | void OPPROTO op_ftrc_FT(void) |
813 | ea6cf6be | ths | { |
814 | ea6cf6be | ths | env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
815 | ea6cf6be | ths | RETURN(); |
816 | ea6cf6be | ths | } |
817 | ea6cf6be | ths | |
818 | ea6cf6be | ths | void OPPROTO op_ftrc_DT(void) |
819 | ea6cf6be | ths | { |
820 | ea6cf6be | ths | env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
821 | ea6cf6be | ths | RETURN(); |
822 | ea6cf6be | ths | } |
823 | ea6cf6be | ths | |
824 | 24988dc2 | aurel32 | void OPPROTO op_fneg_frN(void) |
825 | 24988dc2 | aurel32 | { |
826 | 24988dc2 | aurel32 | env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]); |
827 | 24988dc2 | aurel32 | RETURN(); |
828 | 24988dc2 | aurel32 | } |
829 | 24988dc2 | aurel32 | |
830 | 24988dc2 | aurel32 | void OPPROTO op_fabs_FT(void) |
831 | 24988dc2 | aurel32 | { |
832 | 24988dc2 | aurel32 | FT0 = float32_abs(FT0); |
833 | 24988dc2 | aurel32 | RETURN(); |
834 | 24988dc2 | aurel32 | } |
835 | 24988dc2 | aurel32 | |
836 | 24988dc2 | aurel32 | void OPPROTO op_fabs_DT(void) |
837 | 24988dc2 | aurel32 | { |
838 | 24988dc2 | aurel32 | DT0 = float64_abs(DT0); |
839 | 24988dc2 | aurel32 | RETURN(); |
840 | 24988dc2 | aurel32 | } |
841 | 24988dc2 | aurel32 | |
842 | 24988dc2 | aurel32 | void OPPROTO op_fcnvsd_FT_DT(void) |
843 | 24988dc2 | aurel32 | { |
844 | 24988dc2 | aurel32 | DT0 = float32_to_float64(FT0, &env->fp_status); |
845 | 24988dc2 | aurel32 | RETURN(); |
846 | 24988dc2 | aurel32 | } |
847 | 24988dc2 | aurel32 | |
848 | 24988dc2 | aurel32 | void OPPROTO op_fcnvds_DT_FT(void) |
849 | 24988dc2 | aurel32 | { |
850 | 24988dc2 | aurel32 | FT0 = float64_to_float32(DT0, &env->fp_status); |
851 | 24988dc2 | aurel32 | RETURN(); |
852 | 24988dc2 | aurel32 | } |
853 | 24988dc2 | aurel32 | |
854 | 24988dc2 | aurel32 | void OPPROTO op_fsqrt_FT(void) |
855 | 24988dc2 | aurel32 | { |
856 | 24988dc2 | aurel32 | FT0 = float32_sqrt(FT0, &env->fp_status); |
857 | 24988dc2 | aurel32 | RETURN(); |
858 | 24988dc2 | aurel32 | } |
859 | 24988dc2 | aurel32 | |
860 | 24988dc2 | aurel32 | void OPPROTO op_fsqrt_DT(void) |
861 | 24988dc2 | aurel32 | { |
862 | 24988dc2 | aurel32 | DT0 = float64_sqrt(DT0, &env->fp_status); |
863 | 24988dc2 | aurel32 | RETURN(); |
864 | 24988dc2 | aurel32 | } |
865 | 24988dc2 | aurel32 | |
866 | ea6cf6be | ths | void OPPROTO op_fmov_T0_frN(void) |
867 | ea6cf6be | ths | { |
868 | 24988dc2 | aurel32 | *(uint32_t *)&env->fregs[PARAM1] = T0; |
869 | ea6cf6be | ths | RETURN(); |
870 | ea6cf6be | ths | } |
871 | ea6cf6be | ths | |
872 | fdf9b3e8 | bellard | void OPPROTO op_dec1_rN(void) |
873 | fdf9b3e8 | bellard | { |
874 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 1;
|
875 | fdf9b3e8 | bellard | RETURN(); |
876 | fdf9b3e8 | bellard | } |
877 | fdf9b3e8 | bellard | |
878 | fdf9b3e8 | bellard | void OPPROTO op_dec2_rN(void) |
879 | fdf9b3e8 | bellard | { |
880 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 2;
|
881 | fdf9b3e8 | bellard | RETURN(); |
882 | fdf9b3e8 | bellard | } |
883 | fdf9b3e8 | bellard | |
884 | fdf9b3e8 | bellard | void OPPROTO op_dec4_rN(void) |
885 | fdf9b3e8 | bellard | { |
886 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 4;
|
887 | fdf9b3e8 | bellard | RETURN(); |
888 | fdf9b3e8 | bellard | } |
889 | fdf9b3e8 | bellard | |
890 | eda9b09b | bellard | void OPPROTO op_dec8_rN(void) |
891 | eda9b09b | bellard | { |
892 | 0a618140 | ths | env->gregs[PARAM1] -= 8;
|
893 | eda9b09b | bellard | RETURN(); |
894 | eda9b09b | bellard | } |
895 | eda9b09b | bellard | |
896 | fdf9b3e8 | bellard | void OPPROTO op_inc1_rN(void) |
897 | fdf9b3e8 | bellard | { |
898 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 1;
|
899 | fdf9b3e8 | bellard | RETURN(); |
900 | fdf9b3e8 | bellard | } |
901 | fdf9b3e8 | bellard | |
902 | fdf9b3e8 | bellard | void OPPROTO op_inc2_rN(void) |
903 | fdf9b3e8 | bellard | { |
904 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 2;
|
905 | fdf9b3e8 | bellard | RETURN(); |
906 | fdf9b3e8 | bellard | } |
907 | fdf9b3e8 | bellard | |
908 | fdf9b3e8 | bellard | void OPPROTO op_inc4_rN(void) |
909 | fdf9b3e8 | bellard | { |
910 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
911 | fdf9b3e8 | bellard | RETURN(); |
912 | fdf9b3e8 | bellard | } |
913 | fdf9b3e8 | bellard | |
914 | eda9b09b | bellard | void OPPROTO op_inc8_rN(void) |
915 | eda9b09b | bellard | { |
916 | 0a618140 | ths | env->gregs[PARAM1] += 8;
|
917 | eda9b09b | bellard | RETURN(); |
918 | eda9b09b | bellard | } |
919 | eda9b09b | bellard | |
920 | fdf9b3e8 | bellard | void OPPROTO op_add_T0_rN(void) |
921 | fdf9b3e8 | bellard | { |
922 | fdf9b3e8 | bellard | env->gregs[PARAM1] += T0; |
923 | fdf9b3e8 | bellard | RETURN(); |
924 | fdf9b3e8 | bellard | } |
925 | fdf9b3e8 | bellard | |
926 | fdf9b3e8 | bellard | void OPPROTO op_sub_T0_rN(void) |
927 | fdf9b3e8 | bellard | { |
928 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= T0; |
929 | fdf9b3e8 | bellard | RETURN(); |
930 | fdf9b3e8 | bellard | } |
931 | fdf9b3e8 | bellard | |
932 | fdf9b3e8 | bellard | void OPPROTO op_and_T0_rN(void) |
933 | fdf9b3e8 | bellard | { |
934 | fdf9b3e8 | bellard | env->gregs[PARAM1] &= T0; |
935 | fdf9b3e8 | bellard | RETURN(); |
936 | fdf9b3e8 | bellard | } |
937 | fdf9b3e8 | bellard | |
938 | fdf9b3e8 | bellard | void OPPROTO op_or_T0_rN(void) |
939 | fdf9b3e8 | bellard | { |
940 | fdf9b3e8 | bellard | env->gregs[PARAM1] |= T0; |
941 | fdf9b3e8 | bellard | RETURN(); |
942 | fdf9b3e8 | bellard | } |
943 | fdf9b3e8 | bellard | |
944 | fdf9b3e8 | bellard | void OPPROTO op_xor_T0_rN(void) |
945 | fdf9b3e8 | bellard | { |
946 | fdf9b3e8 | bellard | env->gregs[PARAM1] ^= T0; |
947 | fdf9b3e8 | bellard | RETURN(); |
948 | fdf9b3e8 | bellard | } |
949 | fdf9b3e8 | bellard | |
950 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T0(void) |
951 | fdf9b3e8 | bellard | { |
952 | fdf9b3e8 | bellard | T0 += env->gregs[PARAM1]; |
953 | fdf9b3e8 | bellard | RETURN(); |
954 | fdf9b3e8 | bellard | } |
955 | fdf9b3e8 | bellard | |
956 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T1(void) |
957 | fdf9b3e8 | bellard | { |
958 | fdf9b3e8 | bellard | T1 += env->gregs[PARAM1]; |
959 | fdf9b3e8 | bellard | RETURN(); |
960 | fdf9b3e8 | bellard | } |
961 | fdf9b3e8 | bellard | |
962 | fdf9b3e8 | bellard | void OPPROTO op_add_imm_rN(void) |
963 | fdf9b3e8 | bellard | { |
964 | fdf9b3e8 | bellard | env->gregs[PARAM2] += PARAM1; |
965 | fdf9b3e8 | bellard | RETURN(); |
966 | fdf9b3e8 | bellard | } |
967 | fdf9b3e8 | bellard | |
968 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_rN(void) |
969 | fdf9b3e8 | bellard | { |
970 | fdf9b3e8 | bellard | env->gregs[PARAM2] &= PARAM1; |
971 | fdf9b3e8 | bellard | RETURN(); |
972 | fdf9b3e8 | bellard | } |
973 | fdf9b3e8 | bellard | |
974 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_rN(void) |
975 | fdf9b3e8 | bellard | { |
976 | fdf9b3e8 | bellard | env->gregs[PARAM2] |= PARAM1; |
977 | fdf9b3e8 | bellard | RETURN(); |
978 | fdf9b3e8 | bellard | } |
979 | fdf9b3e8 | bellard | |
980 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_rN(void) |
981 | fdf9b3e8 | bellard | { |
982 | fdf9b3e8 | bellard | env->gregs[PARAM2] ^= PARAM1; |
983 | fdf9b3e8 | bellard | RETURN(); |
984 | fdf9b3e8 | bellard | } |
985 | fdf9b3e8 | bellard | |
986 | fdf9b3e8 | bellard | void OPPROTO op_dt_rN(void) |
987 | fdf9b3e8 | bellard | { |
988 | fdf9b3e8 | bellard | cond_t((--env->gregs[PARAM1]) == 0);
|
989 | fdf9b3e8 | bellard | RETURN(); |
990 | fdf9b3e8 | bellard | } |
991 | fdf9b3e8 | bellard | |
992 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_rN(void) |
993 | fdf9b3e8 | bellard | { |
994 | fdf9b3e8 | bellard | cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
995 | fdf9b3e8 | bellard | RETURN(); |
996 | fdf9b3e8 | bellard | } |
997 | fdf9b3e8 | bellard | |
998 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_T1(void) |
999 | fdf9b3e8 | bellard | { |
1000 | fdf9b3e8 | bellard | T1 = T0; |
1001 | fdf9b3e8 | bellard | RETURN(); |
1002 | fdf9b3e8 | bellard | } |
1003 | fdf9b3e8 | bellard | |
1004 | eda9b09b | bellard | void OPPROTO op_movl_fpul_FT0(void) |
1005 | eda9b09b | bellard | { |
1006 | eda9b09b | bellard | FT0 = *(float32 *)&env->fpul; |
1007 | eda9b09b | bellard | RETURN(); |
1008 | eda9b09b | bellard | } |
1009 | eda9b09b | bellard | |
1010 | eda9b09b | bellard | void OPPROTO op_movl_FT0_fpul(void) |
1011 | eda9b09b | bellard | { |
1012 | eda9b09b | bellard | *(float32 *)&env->fpul = FT0; |
1013 | eda9b09b | bellard | RETURN(); |
1014 | eda9b09b | bellard | } |
1015 | eda9b09b | bellard | |
1016 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_PC(void) |
1017 | fdf9b3e8 | bellard | { |
1018 | fdf9b3e8 | bellard | env->pc = PARAM1; |
1019 | fdf9b3e8 | bellard | RETURN(); |
1020 | fdf9b3e8 | bellard | } |
1021 | fdf9b3e8 | bellard | |
1022 | fdf9b3e8 | bellard | void OPPROTO op_jT(void) |
1023 | fdf9b3e8 | bellard | { |
1024 | fdf9b3e8 | bellard | if (env->sr & SR_T)
|
1025 | fdf9b3e8 | bellard | GOTO_LABEL_PARAM(1);
|
1026 | fdf9b3e8 | bellard | RETURN(); |
1027 | fdf9b3e8 | bellard | } |
1028 | fdf9b3e8 | bellard | |
1029 | 9c2a9ea1 | pbrook | void OPPROTO op_jdelayed(void) |
1030 | fdf9b3e8 | bellard | { |
1031 | 823029f9 | ths | if (env->flags & DELAY_SLOT_TRUE) {
|
1032 | 823029f9 | ths | env->flags &= ~DELAY_SLOT_TRUE; |
1033 | 823029f9 | ths | GOTO_LABEL_PARAM(1);
|
1034 | 823029f9 | ths | } |
1035 | fdf9b3e8 | bellard | RETURN(); |
1036 | fdf9b3e8 | bellard | } |
1037 | fdf9b3e8 | bellard | |
1038 | fdf9b3e8 | bellard | void OPPROTO op_movl_delayed_pc_PC(void) |
1039 | fdf9b3e8 | bellard | { |
1040 | fdf9b3e8 | bellard | env->pc = env->delayed_pc; |
1041 | fdf9b3e8 | bellard | RETURN(); |
1042 | fdf9b3e8 | bellard | } |
1043 | fdf9b3e8 | bellard | |
1044 | fdf9b3e8 | bellard | void OPPROTO op_addl_GBR_T0(void) |
1045 | fdf9b3e8 | bellard | { |
1046 | fdf9b3e8 | bellard | T0 += env->gbr; |
1047 | fdf9b3e8 | bellard | RETURN(); |
1048 | fdf9b3e8 | bellard | } |
1049 | fdf9b3e8 | bellard | |
1050 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_T0(void) |
1051 | fdf9b3e8 | bellard | { |
1052 | fdf9b3e8 | bellard | T0 &= PARAM1; |
1053 | fdf9b3e8 | bellard | RETURN(); |
1054 | fdf9b3e8 | bellard | } |
1055 | fdf9b3e8 | bellard | |
1056 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_T0(void) |
1057 | fdf9b3e8 | bellard | { |
1058 | fdf9b3e8 | bellard | T0 |= PARAM1; |
1059 | fdf9b3e8 | bellard | RETURN(); |
1060 | fdf9b3e8 | bellard | } |
1061 | fdf9b3e8 | bellard | |
1062 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_T0(void) |
1063 | fdf9b3e8 | bellard | { |
1064 | fdf9b3e8 | bellard | T0 ^= PARAM1; |
1065 | fdf9b3e8 | bellard | RETURN(); |
1066 | fdf9b3e8 | bellard | } |
1067 | fdf9b3e8 | bellard | |
1068 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_T0(void) |
1069 | fdf9b3e8 | bellard | { |
1070 | fdf9b3e8 | bellard | cond_t((T0 & PARAM1) == 0);
|
1071 | fdf9b3e8 | bellard | RETURN(); |
1072 | fdf9b3e8 | bellard | } |
1073 | fdf9b3e8 | bellard | |
1074 | fdf9b3e8 | bellard | void OPPROTO op_raise_illegal_instruction(void) |
1075 | fdf9b3e8 | bellard | { |
1076 | fdf9b3e8 | bellard | env->exception_index = 0x180;
|
1077 | fdf9b3e8 | bellard | do_raise_exception(); |
1078 | fdf9b3e8 | bellard | RETURN(); |
1079 | fdf9b3e8 | bellard | } |
1080 | fdf9b3e8 | bellard | |
1081 | fdf9b3e8 | bellard | void OPPROTO op_raise_slot_illegal_instruction(void) |
1082 | fdf9b3e8 | bellard | { |
1083 | fdf9b3e8 | bellard | env->exception_index = 0x1a0;
|
1084 | fdf9b3e8 | bellard | do_raise_exception(); |
1085 | fdf9b3e8 | bellard | RETURN(); |
1086 | fdf9b3e8 | bellard | } |
1087 | fdf9b3e8 | bellard | |
1088 | fdf9b3e8 | bellard | void OPPROTO op_debug(void) |
1089 | fdf9b3e8 | bellard | { |
1090 | fdf9b3e8 | bellard | env->exception_index = EXCP_DEBUG; |
1091 | fdf9b3e8 | bellard | cpu_loop_exit(); |
1092 | fdf9b3e8 | bellard | } |
1093 | fdf9b3e8 | bellard | |
1094 | fdf9b3e8 | bellard | /* Load and store */
|
1095 | fdf9b3e8 | bellard | #define MEMSUFFIX _raw
|
1096 | fdf9b3e8 | bellard | #include "op_mem.c" |
1097 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1098 | fdf9b3e8 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1099 | fdf9b3e8 | bellard | #define MEMSUFFIX _user
|
1100 | fdf9b3e8 | bellard | #include "op_mem.c" |
1101 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1102 | fdf9b3e8 | bellard | |
1103 | fdf9b3e8 | bellard | #define MEMSUFFIX _kernel
|
1104 | fdf9b3e8 | bellard | #include "op_mem.c" |
1105 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1106 | fdf9b3e8 | bellard | #endif |