Revision 5439779e hw/etraxfs_timer.c
| b/hw/etraxfs_timer.c | ||
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#include <stdio.h> |
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#include <sys/time.h> |
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#include "hw.h" |
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#include "sysemu.h" |
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#include "qemu-timer.h" |
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|
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#define D(x) |
| ... | ... | |
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#define RW_TMR1_CTRL 0x18 |
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#define R_TIME 0x38 |
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#define RW_WD_CTRL 0x40 |
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#define R_WD_STAT 0x44 |
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#define RW_INTR_MASK 0x48 |
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#define RW_ACK_INTR 0x4c |
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#define R_INTR 0x50 |
| ... | ... | |
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qemu_irq *irq; |
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target_phys_addr_t base; |
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|
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QEMUBH *bh; |
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ptimer_state *ptimer; |
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QEMUBH *bh_t0; |
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QEMUBH *bh_t1; |
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QEMUBH *bh_wd; |
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ptimer_state *ptimer_t0; |
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ptimer_state *ptimer_t1; |
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ptimer_state *ptimer_wd; |
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struct timeval last; |
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/* Control registers. */ |
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uint32_t r_tmr1_data; |
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uint32_t rw_tmr1_ctrl; |
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uint32_t rw_wd_ctrl; |
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|
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uint32_t rw_intr_mask; |
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uint32_t rw_ack_intr; |
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uint32_t r_intr; |
| ... | ... | |
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} |
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|
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#define TIMER_SLOWDOWN 1 |
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static void update_ctrl(struct fs_timer_t *t) |
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static void update_ctrl(struct fs_timer_t *t, int tnum)
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{
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unsigned int op; |
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unsigned int freq; |
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unsigned int freq_hz; |
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unsigned int div; |
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uint32_t ctrl; |
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ptimer_state *timer; |
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if (tnum == 0) {
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ctrl = t->rw_tmr0_ctrl; |
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div = t->rw_tmr0_div; |
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timer = t->ptimer_t0; |
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} else {
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ctrl = t->rw_tmr1_ctrl; |
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div = t->rw_tmr1_div; |
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timer = t->ptimer_t1; |
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} |
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op = t->rw_tmr0_ctrl & 3;
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freq = t->rw_tmr0_ctrl >> 2;
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op = ctrl & 3; |
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freq = ctrl >> 2; |
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freq_hz = 32000000; |
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switch (freq) |
| ... | ... | |
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case 4: freq_hz = 29493000; break; |
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case 5: freq_hz = 32000000; break; |
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case 6: freq_hz = 32768000; break; |
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case 7: freq_hz = 100000000; break;
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case 7: freq_hz = 100001000; break;
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default: |
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abort(); |
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break; |
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} |
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D(printf ("freq_hz=%d div=%d\n", freq_hz, t->rw_tmr0_div));
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div = t->rw_tmr0_div * TIMER_SLOWDOWN;
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D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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div = div * TIMER_SLOWDOWN; |
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div >>= 15; |
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freq_hz >>= 15; |
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ptimer_set_freq(t->ptimer, freq_hz);
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ptimer_set_limit(t->ptimer, div, 0);
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ptimer_set_freq(timer, freq_hz); |
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ptimer_set_limit(timer, div, 0); |
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switch (op) |
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{
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case 0: |
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/* Load. */ |
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ptimer_set_limit(t->ptimer, div, 1); |
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ptimer_run(t->ptimer, 1); |
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ptimer_set_limit(timer, div, 1); |
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break; |
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case 1: |
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/* Hold. */ |
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ptimer_stop(t->ptimer);
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ptimer_stop(timer); |
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break; |
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case 2: |
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/* Run. */ |
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ptimer_run(t->ptimer, 0);
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ptimer_run(timer, 0); |
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break; |
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default: |
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abort(); |
| ... | ... | |
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qemu_irq_lower(t->irq[0]); |
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} |
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static void timer_hit(void *opaque) |
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static void timer0_hit(void *opaque)
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{
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struct fs_timer_t *t = opaque; |
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t->r_intr |= 1; |
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timer_update_irq(t); |
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} |
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static void timer1_hit(void *opaque) |
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{
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struct fs_timer_t *t = opaque; |
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t->r_intr |= 2; |
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timer_update_irq(t); |
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} |
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static void watchdog_hit(void *opaque) |
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{
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qemu_system_reset_request(); |
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} |
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static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value) |
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{
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unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
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unsigned int wd_key = t->rw_wd_ctrl >> 9; |
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unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
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unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
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unsigned int new_cmd = (value >> 8) & 1; |
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/* If the watchdog is enabled, they written key must match the |
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complement of the previous. */ |
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wd_key = ~wd_key & ((1 << 7) - 1); |
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if (wd_en && wd_key != new_key) |
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return; |
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D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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wd_en, new_key, wd_key, wd_cmd, wd_cnt)); |
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ptimer_set_freq(t->ptimer_wd, 760); |
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if (wd_cnt == 0) |
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wd_cnt = 256; |
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ptimer_set_count(t->ptimer_wd, wd_cnt); |
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if (new_cmd) |
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ptimer_run(t->ptimer_wd, 1); |
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else |
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ptimer_stop(t->ptimer_wd); |
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t->rw_wd_ctrl = value; |
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} |
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|
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static void |
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{
|
| ... | ... | |
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case RW_TMR0_CTRL: |
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D(printf ("RW_TMR0_CTRL=%x\n", value));
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t->rw_tmr0_ctrl = value; |
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update_ctrl(t); |
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update_ctrl(t, 0);
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break; |
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case RW_TMR1_DIV: |
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t->rw_tmr1_div = value; |
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break; |
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case RW_TMR1_CTRL: |
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D(printf ("RW_TMR1_CTRL=%x\n", value));
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t->rw_tmr1_ctrl = value; |
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update_ctrl(t, 1); |
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break; |
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case RW_INTR_MASK: |
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D(printf ("RW_INTR_MASK=%x\n", value));
|
| ... | ... | |
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timer_update_irq(t); |
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break; |
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case RW_WD_CTRL: |
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D(printf ("RW_WD_CTRL=%x\n", value));
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timer_watchdog_update(t, value);
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break; |
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case RW_ACK_INTR: |
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t->rw_ack_intr = value; |
| ... | ... | |
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} |
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static CPUReadMemoryFunc *timer_read[] = {
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&timer_rinvalid,
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&timer_rinvalid,
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&timer_readl,
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&timer_rinvalid,
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&timer_rinvalid,
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&timer_readl,
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}; |
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static CPUWriteMemoryFunc *timer_write[] = {
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&timer_winvalid,
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&timer_winvalid,
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&timer_writel,
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&timer_winvalid,
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&timer_winvalid,
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&timer_writel,
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}; |
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static void etraxfs_timer_reset(void *opaque) |
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{
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struct fs_timer_t *t = opaque; |
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|
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ptimer_stop(t->ptimer_t0); |
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ptimer_stop(t->ptimer_t1); |
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ptimer_stop(t->ptimer_wd); |
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t->rw_wd_ctrl = 0; |
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t->r_intr = 0; |
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t->rw_intr_mask = 0; |
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qemu_irq_lower(t->irq[0]); |
|
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} |
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|
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, |
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target_phys_addr_t base) |
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{
|
| ... | ... | |
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if (!t) |
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return; |
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|
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t->bh = qemu_bh_new(timer_hit, t); |
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t->ptimer = ptimer_init(t->bh); |
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t->bh_t0 = qemu_bh_new(timer0_hit, t); |
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t->bh_t1 = qemu_bh_new(timer1_hit, t); |
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t->bh_wd = qemu_bh_new(watchdog_hit, t); |
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t->ptimer_t0 = ptimer_init(t->bh_t0); |
|
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t->ptimer_t1 = ptimer_init(t->bh_t1); |
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t->ptimer_wd = ptimer_init(t->bh_wd); |
|
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t->irq = irqs; |
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t->env = env; |
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t->base = base; |
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|
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); |
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cpu_register_physical_memory (base, 0x5c, timer_regs); |
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|
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qemu_register_reset(etraxfs_timer_reset, t); |
|
| 264 | 347 |
} |
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