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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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|
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "qemu-common.h" |
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#include "helper.h" |
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//#define DEBUG_MMU
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//#define DEBUG_FEATURES
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//#define DEBUG_PCALL
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typedef struct sparc_def_t sparc_def_t; |
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struct sparc_def_t {
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const char *name; |
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target_ulong iu_version; |
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uint32_t fpu_version; |
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uint32_t mmu_version; |
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uint32_t mmu_bm; |
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uint32_t mmu_ctpr_mask; |
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uint32_t mmu_cxr_mask; |
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uint32_t mmu_sfsr_mask; |
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uint32_t mmu_trcr_mask; |
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uint32_t features; |
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}; |
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|
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static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
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|
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/* Sparc MMU emulation */
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|
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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void cpu_lock(void) |
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{ |
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spin_lock(&global_cpu_lock); |
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} |
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|
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void cpu_unlock(void) |
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{ |
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spin_unlock(&global_cpu_lock); |
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} |
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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if (rw & 2) |
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env1->exception_index = TT_TFAULT; |
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else
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env1->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 }, |
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{ 0, 0, 0, 0, 2, 0, 0, 0 }, |
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{ 2, 2, 0, 0, 0, 2, 3, 3 }, |
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{ 2, 2, 0, 0, 0, 2, 0, 0 }, |
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{ 2, 0, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 0, 2, 0, 2, 0, 2, 0 }, |
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{ 2, 2, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 2, 2, 0, 2, 2, 2, 0 } |
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}; |
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static const int perm_table[2][8] = { |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
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int *prot, int *access_index, |
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target_ulong address, int rw, int mmu_idx) |
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{ |
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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is_user = mmu_idx == MMU_USER_IDX; |
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virt_addr = address & TARGET_PAGE_MASK; |
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & |
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(TARGET_PAGE_SIZE - 1);
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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} |
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} |
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, |
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address, rw, mmu_idx); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
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} |
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|
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
263 |
env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
264 |
env->mmuregs[4] = address; /* Fault address register */ |
265 |
|
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
267 |
// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
281 |
} |
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} |
283 |
|
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{ |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
292 |
pde = ldl_phys(pde_ptr); |
293 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
297 |
case 2: /* PTE, maybe should not happen? */ |
298 |
case 3: /* Reserved */ |
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return 0; |
300 |
case 1: /* L1 PDE */ |
301 |
if (mmulev == 3) |
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
304 |
pde = ldl_phys(pde_ptr); |
305 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
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308 |
case 0: /* Invalid */ |
309 |
case 3: /* Reserved */ |
310 |
return 0; |
311 |
case 2: /* L1 PTE */ |
312 |
return pde;
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case 1: /* L2 PDE */ |
314 |
if (mmulev == 2) |
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
317 |
pde = ldl_phys(pde_ptr); |
318 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
320 |
default:
|
321 |
case 0: /* Invalid */ |
322 |
case 3: /* Reserved */ |
323 |
return 0; |
324 |
case 2: /* L2 PTE */ |
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return pde;
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case 1: /* L3 PDE */ |
327 |
if (mmulev == 1) |
328 |
return pde;
|
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
330 |
pde = ldl_phys(pde_ptr); |
331 |
|
332 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
333 |
default:
|
334 |
case 0: /* Invalid */ |
335 |
case 1: /* PDE, should not happen */ |
336 |
case 3: /* Reserved */ |
337 |
return 0; |
338 |
case 2: /* L3 PTE */ |
339 |
return pde;
|
340 |
} |
341 |
} |
342 |
} |
343 |
} |
344 |
return 0; |
345 |
} |
346 |
|
347 |
#ifdef DEBUG_MMU
|
348 |
void dump_mmu(CPUState *env)
|
349 |
{ |
350 |
target_ulong va, va1, va2; |
351 |
unsigned int n, m, o; |
352 |
target_phys_addr_t pde_ptr, pa; |
353 |
uint32_t pde; |
354 |
|
355 |
printf("MMU dump:\n");
|
356 |
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
357 |
pde = ldl_phys(pde_ptr); |
358 |
printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
359 |
(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
360 |
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
361 |
pde = mmu_probe(env, va, 2);
|
362 |
if (pde) {
|
363 |
pa = cpu_get_phys_page_debug(env, va); |
364 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
365 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
366 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
367 |
pde = mmu_probe(env, va1, 1);
|
368 |
if (pde) {
|
369 |
pa = cpu_get_phys_page_debug(env, va1); |
370 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
371 |
" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
372 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
373 |
pde = mmu_probe(env, va2, 0);
|
374 |
if (pde) {
|
375 |
pa = cpu_get_phys_page_debug(env, va2); |
376 |
printf(" VA: " TARGET_FMT_lx ", PA: " |
377 |
TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
378 |
va2, pa, pde); |
379 |
} |
380 |
} |
381 |
} |
382 |
} |
383 |
} |
384 |
} |
385 |
printf("MMU dump ends\n");
|
386 |
} |
387 |
#endif /* DEBUG_MMU */ |
388 |
|
389 |
#else /* !TARGET_SPARC64 */ |
390 |
/*
|
391 |
* UltraSparc IIi I/DMMUs
|
392 |
*/
|
393 |
static int get_physical_address_data(CPUState *env, |
394 |
target_phys_addr_t *physical, int *prot,
|
395 |
target_ulong address, int rw, int is_user) |
396 |
{ |
397 |
target_ulong mask; |
398 |
unsigned int i; |
399 |
|
400 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
401 |
*physical = address; |
402 |
*prot = PAGE_READ | PAGE_WRITE; |
403 |
return 0; |
404 |
} |
405 |
|
406 |
for (i = 0; i < 64; i++) { |
407 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
408 |
default:
|
409 |
case 0x0: // 8k |
410 |
mask = 0xffffffffffffe000ULL;
|
411 |
break;
|
412 |
case 0x1: // 64k |
413 |
mask = 0xffffffffffff0000ULL;
|
414 |
break;
|
415 |
case 0x2: // 512k |
416 |
mask = 0xfffffffffff80000ULL;
|
417 |
break;
|
418 |
case 0x3: // 4M |
419 |
mask = 0xffffffffffc00000ULL;
|
420 |
break;
|
421 |
} |
422 |
// ctx match, vaddr match?
|
423 |
if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
424 |
(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
425 |
// valid, access ok?
|
426 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
427 |
((env->dtlb_tte[i] & 0x4) && is_user) ||
|
428 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
429 |
if (env->dmmuregs[3]) /* Fault status register */ |
430 |
env->dmmuregs[3] = 2; /* overflow (not read before |
431 |
another fault) */
|
432 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
433 |
env->dmmuregs[4] = address; /* Fault address register */ |
434 |
env->exception_index = TT_DFAULT; |
435 |
#ifdef DEBUG_MMU
|
436 |
printf("DFAULT at 0x%" PRIx64 "\n", address); |
437 |
#endif
|
438 |
return 1; |
439 |
} |
440 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
|
441 |
(address & ~mask & 0x1fffffff000ULL);
|
442 |
*prot = PAGE_READ; |
443 |
if (env->dtlb_tte[i] & 0x2) |
444 |
*prot |= PAGE_WRITE; |
445 |
return 0; |
446 |
} |
447 |
} |
448 |
#ifdef DEBUG_MMU
|
449 |
printf("DMISS at 0x%" PRIx64 "\n", address); |
450 |
#endif
|
451 |
env->exception_index = TT_DMISS; |
452 |
return 1; |
453 |
} |
454 |
|
455 |
static int get_physical_address_code(CPUState *env, |
456 |
target_phys_addr_t *physical, int *prot,
|
457 |
target_ulong address, int is_user)
|
458 |
{ |
459 |
target_ulong mask; |
460 |
unsigned int i; |
461 |
|
462 |
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
463 |
*physical = address; |
464 |
*prot = PAGE_EXEC; |
465 |
return 0; |
466 |
} |
467 |
|
468 |
for (i = 0; i < 64; i++) { |
469 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
470 |
default:
|
471 |
case 0x0: // 8k |
472 |
mask = 0xffffffffffffe000ULL;
|
473 |
break;
|
474 |
case 0x1: // 64k |
475 |
mask = 0xffffffffffff0000ULL;
|
476 |
break;
|
477 |
case 0x2: // 512k |
478 |
mask = 0xfffffffffff80000ULL;
|
479 |
break;
|
480 |
case 0x3: // 4M |
481 |
mask = 0xffffffffffc00000ULL;
|
482 |
break;
|
483 |
} |
484 |
// ctx match, vaddr match?
|
485 |
if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
486 |
(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
487 |
// valid, access ok?
|
488 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
489 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
490 |
if (env->immuregs[3]) /* Fault status register */ |
491 |
env->immuregs[3] = 2; /* overflow (not read before |
492 |
another fault) */
|
493 |
env->immuregs[3] |= (is_user << 3) | 1; |
494 |
env->exception_index = TT_TFAULT; |
495 |
#ifdef DEBUG_MMU
|
496 |
printf("TFAULT at 0x%" PRIx64 "\n", address); |
497 |
#endif
|
498 |
return 1; |
499 |
} |
500 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
|
501 |
(address & ~mask & 0x1fffffff000ULL);
|
502 |
*prot = PAGE_EXEC; |
503 |
return 0; |
504 |
} |
505 |
} |
506 |
#ifdef DEBUG_MMU
|
507 |
printf("TMISS at 0x%" PRIx64 "\n", address); |
508 |
#endif
|
509 |
env->exception_index = TT_TMISS; |
510 |
return 1; |
511 |
} |
512 |
|
513 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
514 |
int *prot, int *access_index, |
515 |
target_ulong address, int rw, int mmu_idx) |
516 |
{ |
517 |
int is_user = mmu_idx == MMU_USER_IDX;
|
518 |
|
519 |
if (rw == 2) |
520 |
return get_physical_address_code(env, physical, prot, address,
|
521 |
is_user); |
522 |
else
|
523 |
return get_physical_address_data(env, physical, prot, address, rw,
|
524 |
is_user); |
525 |
} |
526 |
|
527 |
/* Perform address translation */
|
528 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
529 |
int mmu_idx, int is_softmmu) |
530 |
{ |
531 |
target_ulong virt_addr, vaddr; |
532 |
target_phys_addr_t paddr; |
533 |
int error_code = 0, prot, ret = 0, access_index; |
534 |
|
535 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, |
536 |
address, rw, mmu_idx); |
537 |
if (error_code == 0) { |
538 |
virt_addr = address & TARGET_PAGE_MASK; |
539 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
540 |
(TARGET_PAGE_SIZE - 1));
|
541 |
#ifdef DEBUG_MMU
|
542 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
543 |
"\n", address, paddr, vaddr);
|
544 |
#endif
|
545 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
546 |
return ret;
|
547 |
} |
548 |
// XXX
|
549 |
return 1; |
550 |
} |
551 |
|
552 |
#ifdef DEBUG_MMU
|
553 |
void dump_mmu(CPUState *env)
|
554 |
{ |
555 |
unsigned int i; |
556 |
const char *mask; |
557 |
|
558 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
559 |
env->dmmuregs[1], env->dmmuregs[2]); |
560 |
if ((env->lsu & DMMU_E) == 0) { |
561 |
printf("DMMU disabled\n");
|
562 |
} else {
|
563 |
printf("DMMU dump:\n");
|
564 |
for (i = 0; i < 64; i++) { |
565 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
566 |
default:
|
567 |
case 0x0: |
568 |
mask = " 8k";
|
569 |
break;
|
570 |
case 0x1: |
571 |
mask = " 64k";
|
572 |
break;
|
573 |
case 0x2: |
574 |
mask = "512k";
|
575 |
break;
|
576 |
case 0x3: |
577 |
mask = " 4M";
|
578 |
break;
|
579 |
} |
580 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
581 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
582 |
", %s, %s, %s, %s, ctx %" PRId64 "\n", |
583 |
env->dtlb_tag[i] & ~0x1fffULL,
|
584 |
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
585 |
mask, |
586 |
env->dtlb_tte[i] & 0x4? "priv": "user", |
587 |
env->dtlb_tte[i] & 0x2? "RW": "RO", |
588 |
env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
589 |
env->dtlb_tag[i] & 0x1fffULL);
|
590 |
} |
591 |
} |
592 |
} |
593 |
if ((env->lsu & IMMU_E) == 0) { |
594 |
printf("IMMU disabled\n");
|
595 |
} else {
|
596 |
printf("IMMU dump:\n");
|
597 |
for (i = 0; i < 64; i++) { |
598 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
599 |
default:
|
600 |
case 0x0: |
601 |
mask = " 8k";
|
602 |
break;
|
603 |
case 0x1: |
604 |
mask = " 64k";
|
605 |
break;
|
606 |
case 0x2: |
607 |
mask = "512k";
|
608 |
break;
|
609 |
case 0x3: |
610 |
mask = " 4M";
|
611 |
break;
|
612 |
} |
613 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
614 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
615 |
", %s, %s, %s, ctx %" PRId64 "\n", |
616 |
env->itlb_tag[i] & ~0x1fffULL,
|
617 |
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
618 |
mask, |
619 |
env->itlb_tte[i] & 0x4? "priv": "user", |
620 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
621 |
env->itlb_tag[i] & 0x1fffULL);
|
622 |
} |
623 |
} |
624 |
} |
625 |
} |
626 |
#endif /* DEBUG_MMU */ |
627 |
|
628 |
#endif /* TARGET_SPARC64 */ |
629 |
#endif /* !CONFIG_USER_ONLY */ |
630 |
|
631 |
|
632 |
#if defined(CONFIG_USER_ONLY)
|
633 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
634 |
{ |
635 |
return addr;
|
636 |
} |
637 |
|
638 |
#else
|
639 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
640 |
{ |
641 |
target_phys_addr_t phys_addr; |
642 |
int prot, access_index;
|
643 |
|
644 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
645 |
MMU_KERNEL_IDX) != 0)
|
646 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
647 |
0, MMU_KERNEL_IDX) != 0) |
648 |
return -1; |
649 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
650 |
return -1; |
651 |
return phys_addr;
|
652 |
} |
653 |
#endif
|
654 |
|
655 |
#ifdef TARGET_SPARC64
|
656 |
#ifdef DEBUG_PCALL
|
657 |
static const char * const excp_names[0x50] = { |
658 |
[TT_TFAULT] = "Instruction Access Fault",
|
659 |
[TT_TMISS] = "Instruction Access MMU Miss",
|
660 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
661 |
[TT_ILL_INSN] = "Illegal Instruction",
|
662 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
663 |
[TT_NFPU_INSN] = "FPU Disabled",
|
664 |
[TT_FP_EXCP] = "FPU Exception",
|
665 |
[TT_TOVF] = "Tag Overflow",
|
666 |
[TT_CLRWIN] = "Clean Windows",
|
667 |
[TT_DIV_ZERO] = "Division By Zero",
|
668 |
[TT_DFAULT] = "Data Access Fault",
|
669 |
[TT_DMISS] = "Data Access MMU Miss",
|
670 |
[TT_DATA_ACCESS] = "Data Access Error",
|
671 |
[TT_DPROT] = "Data Protection Error",
|
672 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
673 |
[TT_PRIV_ACT] = "Privileged Action",
|
674 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
675 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
676 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
677 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
678 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
679 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
680 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
681 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
682 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
683 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
684 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
685 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
686 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
687 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
688 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
689 |
}; |
690 |
#endif
|
691 |
|
692 |
void do_interrupt(CPUState *env)
|
693 |
{ |
694 |
int intno = env->exception_index;
|
695 |
|
696 |
#ifdef DEBUG_PCALL
|
697 |
if (loglevel & CPU_LOG_INT) {
|
698 |
static int count; |
699 |
const char *name; |
700 |
|
701 |
if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) |
702 |
name = "Unknown";
|
703 |
else if (intno >= 0x100) |
704 |
name = "Trap Instruction";
|
705 |
else if (intno >= 0xc0) |
706 |
name = "Window Fill";
|
707 |
else if (intno >= 0x80) |
708 |
name = "Window Spill";
|
709 |
else {
|
710 |
name = excp_names[intno]; |
711 |
if (!name)
|
712 |
name = "Unknown";
|
713 |
} |
714 |
|
715 |
fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
716 |
" SP=%016" PRIx64 "\n", |
717 |
count, name, intno, |
718 |
env->pc, |
719 |
env->npc, env->regwptr[6]);
|
720 |
cpu_dump_state(env, logfile, fprintf, 0);
|
721 |
#if 0
|
722 |
{
|
723 |
int i;
|
724 |
uint8_t *ptr;
|
725 |
|
726 |
fprintf(logfile, " code=");
|
727 |
ptr = (uint8_t *)env->pc;
|
728 |
for(i = 0; i < 16; i++) {
|
729 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
730 |
}
|
731 |
fprintf(logfile, "\n");
|
732 |
}
|
733 |
#endif
|
734 |
count++; |
735 |
} |
736 |
#endif
|
737 |
#if !defined(CONFIG_USER_ONLY)
|
738 |
if (env->tl == MAXTL) {
|
739 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
|
740 |
env->exception_index); |
741 |
return;
|
742 |
} |
743 |
#endif
|
744 |
env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
|
745 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
746 |
GET_CWP64(env); |
747 |
env->tsptr->tpc = env->pc; |
748 |
env->tsptr->tnpc = env->npc; |
749 |
env->tsptr->tt = intno; |
750 |
change_pstate(PS_PEF | PS_PRIV | PS_AG); |
751 |
|
752 |
if (intno == TT_CLRWIN)
|
753 |
cpu_set_cwp(env, (env->cwp - 1) & (NWINDOWS - 1)); |
754 |
else if ((intno & 0x1c0) == TT_SPILL) |
755 |
cpu_set_cwp(env, (env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
756 |
else if ((intno & 0x1c0) == TT_FILL) |
757 |
cpu_set_cwp(env, (env->cwp + 1) & (NWINDOWS - 1)); |
758 |
env->tbr &= ~0x7fffULL;
|
759 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
760 |
if (env->tl < MAXTL - 1) { |
761 |
env->tl++; |
762 |
} else {
|
763 |
env->pstate |= PS_RED; |
764 |
if (env->tl != MAXTL)
|
765 |
env->tl++; |
766 |
} |
767 |
env->tsptr = &env->ts[env->tl]; |
768 |
env->pc = env->tbr; |
769 |
env->npc = env->pc + 4;
|
770 |
env->exception_index = 0;
|
771 |
} |
772 |
#else
|
773 |
#ifdef DEBUG_PCALL
|
774 |
static const char * const excp_names[0x80] = { |
775 |
[TT_TFAULT] = "Instruction Access Fault",
|
776 |
[TT_ILL_INSN] = "Illegal Instruction",
|
777 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
778 |
[TT_NFPU_INSN] = "FPU Disabled",
|
779 |
[TT_WIN_OVF] = "Window Overflow",
|
780 |
[TT_WIN_UNF] = "Window Underflow",
|
781 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
782 |
[TT_FP_EXCP] = "FPU Exception",
|
783 |
[TT_DFAULT] = "Data Access Fault",
|
784 |
[TT_TOVF] = "Tag Overflow",
|
785 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
786 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
787 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
788 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
789 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
790 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
791 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
792 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
793 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
794 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
795 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
796 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
797 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
798 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
799 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
800 |
[TT_TOVF] = "Tag Overflow",
|
801 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
802 |
[TT_DATA_ACCESS] = "Data Access Error",
|
803 |
[TT_DIV_ZERO] = "Division By Zero",
|
804 |
[TT_NCP_INSN] = "Coprocessor Disabled",
|
805 |
}; |
806 |
#endif
|
807 |
|
808 |
void do_interrupt(CPUState *env)
|
809 |
{ |
810 |
int cwp, intno = env->exception_index;
|
811 |
|
812 |
#ifdef DEBUG_PCALL
|
813 |
if (loglevel & CPU_LOG_INT) {
|
814 |
static int count; |
815 |
const char *name; |
816 |
|
817 |
if (intno < 0 || intno >= 0x100) |
818 |
name = "Unknown";
|
819 |
else if (intno >= 0x80) |
820 |
name = "Trap Instruction";
|
821 |
else {
|
822 |
name = excp_names[intno]; |
823 |
if (!name)
|
824 |
name = "Unknown";
|
825 |
} |
826 |
|
827 |
fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
828 |
count, name, intno, |
829 |
env->pc, |
830 |
env->npc, env->regwptr[6]);
|
831 |
cpu_dump_state(env, logfile, fprintf, 0);
|
832 |
#if 0
|
833 |
{
|
834 |
int i;
|
835 |
uint8_t *ptr;
|
836 |
|
837 |
fprintf(logfile, " code=");
|
838 |
ptr = (uint8_t *)env->pc;
|
839 |
for(i = 0; i < 16; i++) {
|
840 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
841 |
}
|
842 |
fprintf(logfile, "\n");
|
843 |
}
|
844 |
#endif
|
845 |
count++; |
846 |
} |
847 |
#endif
|
848 |
#if !defined(CONFIG_USER_ONLY)
|
849 |
if (env->psret == 0) { |
850 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
851 |
env->exception_index); |
852 |
return;
|
853 |
} |
854 |
#endif
|
855 |
env->psret = 0;
|
856 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
857 |
cpu_set_cwp(env, cwp); |
858 |
env->regwptr[9] = env->pc;
|
859 |
env->regwptr[10] = env->npc;
|
860 |
env->psrps = env->psrs; |
861 |
env->psrs = 1;
|
862 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
863 |
env->pc = env->tbr; |
864 |
env->npc = env->pc + 4;
|
865 |
env->exception_index = 0;
|
866 |
} |
867 |
#endif
|
868 |
|
869 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
870 |
{ |
871 |
dst[0] = src[0]; |
872 |
dst[1] = src[1]; |
873 |
dst[2] = src[2]; |
874 |
dst[3] = src[3]; |
875 |
dst[4] = src[4]; |
876 |
dst[5] = src[5]; |
877 |
dst[6] = src[6]; |
878 |
dst[7] = src[7]; |
879 |
} |
880 |
|
881 |
void cpu_reset(CPUSPARCState *env)
|
882 |
{ |
883 |
tlb_flush(env, 1);
|
884 |
env->cwp = 0;
|
885 |
env->wim = 1;
|
886 |
env->regwptr = env->regbase + (env->cwp * 16);
|
887 |
#if defined(CONFIG_USER_ONLY)
|
888 |
env->user_mode_only = 1;
|
889 |
#ifdef TARGET_SPARC64
|
890 |
env->cleanwin = NWINDOWS - 2;
|
891 |
env->cansave = NWINDOWS - 2;
|
892 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
893 |
env->asi = 0x82; // Primary no-fault |
894 |
#endif
|
895 |
#else
|
896 |
env->psret = 0;
|
897 |
env->psrs = 1;
|
898 |
env->psrps = 1;
|
899 |
#ifdef TARGET_SPARC64
|
900 |
env->pstate = PS_PRIV; |
901 |
env->hpstate = HS_PRIV; |
902 |
env->pc = 0x1fff0000000ULL;
|
903 |
env->tsptr = &env->ts[env->tl]; |
904 |
#else
|
905 |
env->pc = 0;
|
906 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
907 |
env->mmuregs[0] |= env->mmu_bm;
|
908 |
#endif
|
909 |
env->npc = env->pc + 4;
|
910 |
#endif
|
911 |
} |
912 |
|
913 |
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
914 |
{ |
915 |
sparc_def_t def1, *def = &def1; |
916 |
|
917 |
if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
918 |
return -1; |
919 |
|
920 |
env->features = def->features; |
921 |
env->cpu_model_str = cpu_model; |
922 |
env->version = def->iu_version; |
923 |
env->fsr = def->fpu_version; |
924 |
#if !defined(TARGET_SPARC64)
|
925 |
env->mmu_bm = def->mmu_bm; |
926 |
env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
927 |
env->mmu_cxr_mask = def->mmu_cxr_mask; |
928 |
env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
929 |
env->mmu_trcr_mask = def->mmu_trcr_mask; |
930 |
env->mmuregs[0] |= def->mmu_version;
|
931 |
cpu_sparc_set_id(env, 0);
|
932 |
#endif
|
933 |
return 0; |
934 |
} |
935 |
|
936 |
static void cpu_sparc_close(CPUSPARCState *env) |
937 |
{ |
938 |
free(env); |
939 |
} |
940 |
|
941 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
942 |
{ |
943 |
CPUSPARCState *env; |
944 |
|
945 |
env = qemu_mallocz(sizeof(CPUSPARCState));
|
946 |
if (!env)
|
947 |
return NULL; |
948 |
cpu_exec_init(env); |
949 |
|
950 |
gen_intermediate_code_init(env); |
951 |
|
952 |
if (cpu_sparc_register(env, cpu_model) < 0) { |
953 |
cpu_sparc_close(env); |
954 |
return NULL; |
955 |
} |
956 |
cpu_reset(env); |
957 |
|
958 |
return env;
|
959 |
} |
960 |
|
961 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
962 |
{ |
963 |
#if !defined(TARGET_SPARC64)
|
964 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
965 |
#endif
|
966 |
} |
967 |
|
968 |
static const sparc_def_t sparc_defs[] = { |
969 |
#ifdef TARGET_SPARC64
|
970 |
{ |
971 |
.name = "Fujitsu Sparc64",
|
972 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
973 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
974 |
.fpu_version = 0x00000000,
|
975 |
.mmu_version = 0,
|
976 |
.features = CPU_DEFAULT_FEATURES, |
977 |
}, |
978 |
{ |
979 |
.name = "Fujitsu Sparc64 III",
|
980 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
981 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
982 |
.fpu_version = 0x00000000,
|
983 |
.mmu_version = 0,
|
984 |
.features = CPU_DEFAULT_FEATURES, |
985 |
}, |
986 |
{ |
987 |
.name = "Fujitsu Sparc64 IV",
|
988 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
989 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
990 |
.fpu_version = 0x00000000,
|
991 |
.mmu_version = 0,
|
992 |
.features = CPU_DEFAULT_FEATURES, |
993 |
}, |
994 |
{ |
995 |
.name = "Fujitsu Sparc64 V",
|
996 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
997 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
998 |
.fpu_version = 0x00000000,
|
999 |
.mmu_version = 0,
|
1000 |
.features = CPU_DEFAULT_FEATURES, |
1001 |
}, |
1002 |
{ |
1003 |
.name = "TI UltraSparc I",
|
1004 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
1005 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1006 |
.fpu_version = 0x00000000,
|
1007 |
.mmu_version = 0,
|
1008 |
.features = CPU_DEFAULT_FEATURES, |
1009 |
}, |
1010 |
{ |
1011 |
.name = "TI UltraSparc II",
|
1012 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
1013 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1014 |
.fpu_version = 0x00000000,
|
1015 |
.mmu_version = 0,
|
1016 |
.features = CPU_DEFAULT_FEATURES, |
1017 |
}, |
1018 |
{ |
1019 |
.name = "TI UltraSparc IIi",
|
1020 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
1021 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1022 |
.fpu_version = 0x00000000,
|
1023 |
.mmu_version = 0,
|
1024 |
.features = CPU_DEFAULT_FEATURES, |
1025 |
}, |
1026 |
{ |
1027 |
.name = "TI UltraSparc IIe",
|
1028 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
1029 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1030 |
.fpu_version = 0x00000000,
|
1031 |
.mmu_version = 0,
|
1032 |
.features = CPU_DEFAULT_FEATURES, |
1033 |
}, |
1034 |
{ |
1035 |
.name = "Sun UltraSparc III",
|
1036 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
1037 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1038 |
.fpu_version = 0x00000000,
|
1039 |
.mmu_version = 0,
|
1040 |
.features = CPU_DEFAULT_FEATURES, |
1041 |
}, |
1042 |
{ |
1043 |
.name = "Sun UltraSparc III Cu",
|
1044 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
1045 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1046 |
.fpu_version = 0x00000000,
|
1047 |
.mmu_version = 0,
|
1048 |
.features = CPU_DEFAULT_FEATURES, |
1049 |
}, |
1050 |
{ |
1051 |
.name = "Sun UltraSparc IIIi",
|
1052 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
1053 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1054 |
.fpu_version = 0x00000000,
|
1055 |
.mmu_version = 0,
|
1056 |
.features = CPU_DEFAULT_FEATURES, |
1057 |
}, |
1058 |
{ |
1059 |
.name = "Sun UltraSparc IV",
|
1060 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
1061 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1062 |
.fpu_version = 0x00000000,
|
1063 |
.mmu_version = 0,
|
1064 |
.features = CPU_DEFAULT_FEATURES, |
1065 |
}, |
1066 |
{ |
1067 |
.name = "Sun UltraSparc IV+",
|
1068 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
1069 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1070 |
.fpu_version = 0x00000000,
|
1071 |
.mmu_version = 0,
|
1072 |
.features = CPU_DEFAULT_FEATURES, |
1073 |
}, |
1074 |
{ |
1075 |
.name = "Sun UltraSparc IIIi+",
|
1076 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
1077 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1078 |
.fpu_version = 0x00000000,
|
1079 |
.mmu_version = 0,
|
1080 |
.features = CPU_DEFAULT_FEATURES, |
1081 |
}, |
1082 |
{ |
1083 |
.name = "NEC UltraSparc I",
|
1084 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
1085 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
1086 |
.fpu_version = 0x00000000,
|
1087 |
.mmu_version = 0,
|
1088 |
.features = CPU_DEFAULT_FEATURES, |
1089 |
}, |
1090 |
#else
|
1091 |
{ |
1092 |
.name = "Fujitsu MB86900",
|
1093 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
1094 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1095 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
1096 |
.mmu_bm = 0x00004000,
|
1097 |
.mmu_ctpr_mask = 0x007ffff0,
|
1098 |
.mmu_cxr_mask = 0x0000003f,
|
1099 |
.mmu_sfsr_mask = 0xffffffff,
|
1100 |
.mmu_trcr_mask = 0xffffffff,
|
1101 |
.features = CPU_FEATURE_FLOAT, |
1102 |
}, |
1103 |
{ |
1104 |
.name = "Fujitsu MB86904",
|
1105 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
1106 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1107 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
1108 |
.mmu_bm = 0x00004000,
|
1109 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1110 |
.mmu_cxr_mask = 0x000000ff,
|
1111 |
.mmu_sfsr_mask = 0x00016fff,
|
1112 |
.mmu_trcr_mask = 0x00ffffff,
|
1113 |
.features = CPU_DEFAULT_FEATURES, |
1114 |
}, |
1115 |
{ |
1116 |
.name = "Fujitsu MB86907",
|
1117 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
1118 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1119 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
1120 |
.mmu_bm = 0x00004000,
|
1121 |
.mmu_ctpr_mask = 0xffffffc0,
|
1122 |
.mmu_cxr_mask = 0x000000ff,
|
1123 |
.mmu_sfsr_mask = 0x00016fff,
|
1124 |
.mmu_trcr_mask = 0xffffffff,
|
1125 |
.features = CPU_DEFAULT_FEATURES, |
1126 |
}, |
1127 |
{ |
1128 |
.name = "LSI L64811",
|
1129 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
1130 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
1131 |
.mmu_version = 0x10 << 24, |
1132 |
.mmu_bm = 0x00004000,
|
1133 |
.mmu_ctpr_mask = 0x007ffff0,
|
1134 |
.mmu_cxr_mask = 0x0000003f,
|
1135 |
.mmu_sfsr_mask = 0xffffffff,
|
1136 |
.mmu_trcr_mask = 0xffffffff,
|
1137 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, |
1138 |
}, |
1139 |
{ |
1140 |
.name = "Cypress CY7C601",
|
1141 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
1142 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
1143 |
.mmu_version = 0x10 << 24, |
1144 |
.mmu_bm = 0x00004000,
|
1145 |
.mmu_ctpr_mask = 0x007ffff0,
|
1146 |
.mmu_cxr_mask = 0x0000003f,
|
1147 |
.mmu_sfsr_mask = 0xffffffff,
|
1148 |
.mmu_trcr_mask = 0xffffffff,
|
1149 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, |
1150 |
}, |
1151 |
{ |
1152 |
.name = "Cypress CY7C611",
|
1153 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
1154 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
1155 |
.mmu_version = 0x10 << 24, |
1156 |
.mmu_bm = 0x00004000,
|
1157 |
.mmu_ctpr_mask = 0x007ffff0,
|
1158 |
.mmu_cxr_mask = 0x0000003f,
|
1159 |
.mmu_sfsr_mask = 0xffffffff,
|
1160 |
.mmu_trcr_mask = 0xffffffff,
|
1161 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, |
1162 |
}, |
1163 |
{ |
1164 |
.name = "TI SuperSparc II",
|
1165 |
.iu_version = 0x40000000,
|
1166 |
.fpu_version = 0 << 17, |
1167 |
.mmu_version = 0x04000000,
|
1168 |
.mmu_bm = 0x00002000,
|
1169 |
.mmu_ctpr_mask = 0xffffffc0,
|
1170 |
.mmu_cxr_mask = 0x0000ffff,
|
1171 |
.mmu_sfsr_mask = 0xffffffff,
|
1172 |
.mmu_trcr_mask = 0xffffffff,
|
1173 |
.features = CPU_DEFAULT_FEATURES, |
1174 |
}, |
1175 |
{ |
1176 |
.name = "TI MicroSparc I",
|
1177 |
.iu_version = 0x41000000,
|
1178 |
.fpu_version = 4 << 17, |
1179 |
.mmu_version = 0x41000000,
|
1180 |
.mmu_bm = 0x00004000,
|
1181 |
.mmu_ctpr_mask = 0x007ffff0,
|
1182 |
.mmu_cxr_mask = 0x0000003f,
|
1183 |
.mmu_sfsr_mask = 0x00016fff,
|
1184 |
.mmu_trcr_mask = 0x0000003f,
|
1185 |
.features = CPU_DEFAULT_FEATURES, |
1186 |
}, |
1187 |
{ |
1188 |
.name = "TI MicroSparc II",
|
1189 |
.iu_version = 0x42000000,
|
1190 |
.fpu_version = 4 << 17, |
1191 |
.mmu_version = 0x02000000,
|
1192 |
.mmu_bm = 0x00004000,
|
1193 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1194 |
.mmu_cxr_mask = 0x000000ff,
|
1195 |
.mmu_sfsr_mask = 0x00016fff,
|
1196 |
.mmu_trcr_mask = 0x00ffffff,
|
1197 |
.features = CPU_DEFAULT_FEATURES, |
1198 |
}, |
1199 |
{ |
1200 |
.name = "TI MicroSparc IIep",
|
1201 |
.iu_version = 0x42000000,
|
1202 |
.fpu_version = 4 << 17, |
1203 |
.mmu_version = 0x04000000,
|
1204 |
.mmu_bm = 0x00004000,
|
1205 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1206 |
.mmu_cxr_mask = 0x000000ff,
|
1207 |
.mmu_sfsr_mask = 0x00016bff,
|
1208 |
.mmu_trcr_mask = 0x00ffffff,
|
1209 |
.features = CPU_DEFAULT_FEATURES, |
1210 |
}, |
1211 |
{ |
1212 |
.name = "TI SuperSparc 51",
|
1213 |
.iu_version = 0x43000000,
|
1214 |
.fpu_version = 0 << 17, |
1215 |
.mmu_version = 0x04000000,
|
1216 |
.mmu_bm = 0x00002000,
|
1217 |
.mmu_ctpr_mask = 0xffffffc0,
|
1218 |
.mmu_cxr_mask = 0x0000ffff,
|
1219 |
.mmu_sfsr_mask = 0xffffffff,
|
1220 |
.mmu_trcr_mask = 0xffffffff,
|
1221 |
.features = CPU_DEFAULT_FEATURES, |
1222 |
}, |
1223 |
{ |
1224 |
.name = "TI SuperSparc 61",
|
1225 |
.iu_version = 0x44000000,
|
1226 |
.fpu_version = 0 << 17, |
1227 |
.mmu_version = 0x04000000,
|
1228 |
.mmu_bm = 0x00002000,
|
1229 |
.mmu_ctpr_mask = 0xffffffc0,
|
1230 |
.mmu_cxr_mask = 0x0000ffff,
|
1231 |
.mmu_sfsr_mask = 0xffffffff,
|
1232 |
.mmu_trcr_mask = 0xffffffff,
|
1233 |
.features = CPU_DEFAULT_FEATURES, |
1234 |
}, |
1235 |
{ |
1236 |
.name = "Ross RT625",
|
1237 |
.iu_version = 0x1e000000,
|
1238 |
.fpu_version = 1 << 17, |
1239 |
.mmu_version = 0x1e000000,
|
1240 |
.mmu_bm = 0x00004000,
|
1241 |
.mmu_ctpr_mask = 0x007ffff0,
|
1242 |
.mmu_cxr_mask = 0x0000003f,
|
1243 |
.mmu_sfsr_mask = 0xffffffff,
|
1244 |
.mmu_trcr_mask = 0xffffffff,
|
1245 |
.features = CPU_DEFAULT_FEATURES, |
1246 |
}, |
1247 |
{ |
1248 |
.name = "Ross RT620",
|
1249 |
.iu_version = 0x1f000000,
|
1250 |
.fpu_version = 1 << 17, |
1251 |
.mmu_version = 0x1f000000,
|
1252 |
.mmu_bm = 0x00004000,
|
1253 |
.mmu_ctpr_mask = 0x007ffff0,
|
1254 |
.mmu_cxr_mask = 0x0000003f,
|
1255 |
.mmu_sfsr_mask = 0xffffffff,
|
1256 |
.mmu_trcr_mask = 0xffffffff,
|
1257 |
.features = CPU_DEFAULT_FEATURES, |
1258 |
}, |
1259 |
{ |
1260 |
.name = "BIT B5010",
|
1261 |
.iu_version = 0x20000000,
|
1262 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
1263 |
.mmu_version = 0x20000000,
|
1264 |
.mmu_bm = 0x00004000,
|
1265 |
.mmu_ctpr_mask = 0x007ffff0,
|
1266 |
.mmu_cxr_mask = 0x0000003f,
|
1267 |
.mmu_sfsr_mask = 0xffffffff,
|
1268 |
.mmu_trcr_mask = 0xffffffff,
|
1269 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, |
1270 |
}, |
1271 |
{ |
1272 |
.name = "Matsushita MN10501",
|
1273 |
.iu_version = 0x50000000,
|
1274 |
.fpu_version = 0 << 17, |
1275 |
.mmu_version = 0x50000000,
|
1276 |
.mmu_bm = 0x00004000,
|
1277 |
.mmu_ctpr_mask = 0x007ffff0,
|
1278 |
.mmu_cxr_mask = 0x0000003f,
|
1279 |
.mmu_sfsr_mask = 0xffffffff,
|
1280 |
.mmu_trcr_mask = 0xffffffff,
|
1281 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT, |
1282 |
}, |
1283 |
{ |
1284 |
.name = "Weitek W8601",
|
1285 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1286 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1287 |
.mmu_version = 0x10 << 24, |
1288 |
.mmu_bm = 0x00004000,
|
1289 |
.mmu_ctpr_mask = 0x007ffff0,
|
1290 |
.mmu_cxr_mask = 0x0000003f,
|
1291 |
.mmu_sfsr_mask = 0xffffffff,
|
1292 |
.mmu_trcr_mask = 0xffffffff,
|
1293 |
.features = CPU_DEFAULT_FEATURES, |
1294 |
}, |
1295 |
{ |
1296 |
.name = "LEON2",
|
1297 |
.iu_version = 0xf2000000,
|
1298 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1299 |
.mmu_version = 0xf2000000,
|
1300 |
.mmu_bm = 0x00004000,
|
1301 |
.mmu_ctpr_mask = 0x007ffff0,
|
1302 |
.mmu_cxr_mask = 0x0000003f,
|
1303 |
.mmu_sfsr_mask = 0xffffffff,
|
1304 |
.mmu_trcr_mask = 0xffffffff,
|
1305 |
.features = CPU_DEFAULT_FEATURES, |
1306 |
}, |
1307 |
{ |
1308 |
.name = "LEON3",
|
1309 |
.iu_version = 0xf3000000,
|
1310 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1311 |
.mmu_version = 0xf3000000,
|
1312 |
.mmu_bm = 0x00004000,
|
1313 |
.mmu_ctpr_mask = 0x007ffff0,
|
1314 |
.mmu_cxr_mask = 0x0000003f,
|
1315 |
.mmu_sfsr_mask = 0xffffffff,
|
1316 |
.mmu_trcr_mask = 0xffffffff,
|
1317 |
.features = CPU_DEFAULT_FEATURES, |
1318 |
}, |
1319 |
#endif
|
1320 |
}; |
1321 |
|
1322 |
static const char * const feature_name[] = { |
1323 |
"float",
|
1324 |
"float128",
|
1325 |
"swap",
|
1326 |
"mul",
|
1327 |
"div",
|
1328 |
"flush",
|
1329 |
"fsqrt",
|
1330 |
"fmul",
|
1331 |
"vis1",
|
1332 |
"vis2",
|
1333 |
}; |
1334 |
|
1335 |
static void print_features(FILE *f, |
1336 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1337 |
uint32_t features, const char *prefix) |
1338 |
{ |
1339 |
unsigned int i; |
1340 |
|
1341 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1342 |
if (feature_name[i] && (features & (1 << i))) { |
1343 |
if (prefix)
|
1344 |
(*cpu_fprintf)(f, "%s", prefix);
|
1345 |
(*cpu_fprintf)(f, "%s ", feature_name[i]);
|
1346 |
} |
1347 |
} |
1348 |
|
1349 |
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
1350 |
{ |
1351 |
unsigned int i; |
1352 |
|
1353 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1354 |
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
1355 |
*features |= 1 << i;
|
1356 |
return;
|
1357 |
} |
1358 |
fprintf(stderr, "CPU feature %s not found\n", flagname);
|
1359 |
} |
1360 |
|
1361 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
1362 |
{ |
1363 |
unsigned int i; |
1364 |
const sparc_def_t *def = NULL; |
1365 |
char *s = strdup(cpu_model);
|
1366 |
char *featurestr, *name = strtok(s, ","); |
1367 |
uint32_t plus_features = 0;
|
1368 |
uint32_t minus_features = 0;
|
1369 |
long long iu_version; |
1370 |
uint32_t fpu_version, mmu_version; |
1371 |
|
1372 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1373 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1374 |
def = &sparc_defs[i]; |
1375 |
} |
1376 |
} |
1377 |
if (!def)
|
1378 |
goto error;
|
1379 |
memcpy(cpu_def, def, sizeof(*def));
|
1380 |
|
1381 |
featurestr = strtok(NULL, ","); |
1382 |
while (featurestr) {
|
1383 |
char *val;
|
1384 |
|
1385 |
if (featurestr[0] == '+') { |
1386 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
1387 |
} else if (featurestr[0] == '-') { |
1388 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
1389 |
} else if ((val = strchr(featurestr, '='))) { |
1390 |
*val = 0; val++;
|
1391 |
if (!strcmp(featurestr, "iu_version")) { |
1392 |
char *err;
|
1393 |
|
1394 |
iu_version = strtoll(val, &err, 0);
|
1395 |
if (!*val || *err) {
|
1396 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1397 |
goto error;
|
1398 |
} |
1399 |
cpu_def->iu_version = iu_version; |
1400 |
#ifdef DEBUG_FEATURES
|
1401 |
fprintf(stderr, "iu_version %llx\n", iu_version);
|
1402 |
#endif
|
1403 |
} else if (!strcmp(featurestr, "fpu_version")) { |
1404 |
char *err;
|
1405 |
|
1406 |
fpu_version = strtol(val, &err, 0);
|
1407 |
if (!*val || *err) {
|
1408 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1409 |
goto error;
|
1410 |
} |
1411 |
cpu_def->fpu_version = fpu_version; |
1412 |
#ifdef DEBUG_FEATURES
|
1413 |
fprintf(stderr, "fpu_version %llx\n", fpu_version);
|
1414 |
#endif
|
1415 |
} else if (!strcmp(featurestr, "mmu_version")) { |
1416 |
char *err;
|
1417 |
|
1418 |
mmu_version = strtol(val, &err, 0);
|
1419 |
if (!*val || *err) {
|
1420 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1421 |
goto error;
|
1422 |
} |
1423 |
cpu_def->mmu_version = mmu_version; |
1424 |
#ifdef DEBUG_FEATURES
|
1425 |
fprintf(stderr, "mmu_version %llx\n", mmu_version);
|
1426 |
#endif
|
1427 |
} else {
|
1428 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1429 |
goto error;
|
1430 |
} |
1431 |
} else {
|
1432 |
fprintf(stderr, "feature string `%s' not in format "
|
1433 |
"(+feature|-feature|feature=xyz)\n", featurestr);
|
1434 |
goto error;
|
1435 |
} |
1436 |
featurestr = strtok(NULL, ","); |
1437 |
} |
1438 |
cpu_def->features |= plus_features; |
1439 |
cpu_def->features &= ~minus_features; |
1440 |
#ifdef DEBUG_FEATURES
|
1441 |
print_features(stderr, fprintf, cpu_def->features, NULL);
|
1442 |
#endif
|
1443 |
free(s); |
1444 |
return 0; |
1445 |
|
1446 |
error:
|
1447 |
free(s); |
1448 |
return -1; |
1449 |
} |
1450 |
|
1451 |
void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1452 |
{ |
1453 |
unsigned int i; |
1454 |
|
1455 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1456 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x ", |
1457 |
sparc_defs[i].name, |
1458 |
sparc_defs[i].iu_version, |
1459 |
sparc_defs[i].fpu_version, |
1460 |
sparc_defs[i].mmu_version); |
1461 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1462 |
~sparc_defs[i].features, "-");
|
1463 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
1464 |
sparc_defs[i].features, "+");
|
1465 |
(*cpu_fprintf)(f, "\n");
|
1466 |
} |
1467 |
(*cpu_fprintf)(f, "CPU feature flags (+/-): ");
|
1468 |
print_features(f, cpu_fprintf, -1, NULL); |
1469 |
(*cpu_fprintf)(f, "\n");
|
1470 |
(*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
|
1471 |
"mmu_version\n");
|
1472 |
} |
1473 |
|
1474 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1475 |
|
1476 |
void cpu_dump_state(CPUState *env, FILE *f,
|
1477 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1478 |
int flags)
|
1479 |
{ |
1480 |
int i, x;
|
1481 |
|
1482 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1483 |
env->npc); |
1484 |
cpu_fprintf(f, "General Registers:\n");
|
1485 |
for (i = 0; i < 4; i++) |
1486 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1487 |
cpu_fprintf(f, "\n");
|
1488 |
for (; i < 8; i++) |
1489 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1490 |
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1491 |
for (x = 0; x < 3; x++) { |
1492 |
for (i = 0; i < 4; i++) |
1493 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1494 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1495 |
env->regwptr[i + x * 8]);
|
1496 |
cpu_fprintf(f, "\n");
|
1497 |
for (; i < 8; i++) |
1498 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1499 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1500 |
env->regwptr[i + x * 8]);
|
1501 |
cpu_fprintf(f, "\n");
|
1502 |
} |
1503 |
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1504 |
for (i = 0; i < 32; i++) { |
1505 |
if ((i & 3) == 0) |
1506 |
cpu_fprintf(f, "%%f%02d:", i);
|
1507 |
cpu_fprintf(f, " %016lf", env->fpr[i]);
|
1508 |
if ((i & 3) == 3) |
1509 |
cpu_fprintf(f, "\n");
|
1510 |
} |
1511 |
#ifdef TARGET_SPARC64
|
1512 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1513 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1514 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
|
1515 |
"cleanwin %d cwp %d\n",
|
1516 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
1517 |
env->cleanwin, NWINDOWS - 1 - env->cwp);
|
1518 |
#else
|
1519 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
|
1520 |
GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1521 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1522 |
env->psrs?'S':'-', env->psrps?'P':'-', |
1523 |
env->psret?'E':'-', env->wim); |
1524 |
#endif
|
1525 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
1526 |
} |
1527 |
|
1528 |
#ifdef TARGET_SPARC64
|
1529 |
#if !defined(CONFIG_USER_ONLY)
|
1530 |
#include "qemu-common.h" |
1531 |
#include "hw/irq.h" |
1532 |
#include "qemu-timer.h" |
1533 |
#endif
|
1534 |
|
1535 |
void helper_tick_set_count(void *opaque, uint64_t count) |
1536 |
{ |
1537 |
#if !defined(CONFIG_USER_ONLY)
|
1538 |
ptimer_set_count(opaque, -count); |
1539 |
#endif
|
1540 |
} |
1541 |
|
1542 |
uint64_t helper_tick_get_count(void *opaque)
|
1543 |
{ |
1544 |
#if !defined(CONFIG_USER_ONLY)
|
1545 |
return -ptimer_get_count(opaque);
|
1546 |
#else
|
1547 |
return 0; |
1548 |
#endif
|
1549 |
} |
1550 |
|
1551 |
void helper_tick_set_limit(void *opaque, uint64_t limit) |
1552 |
{ |
1553 |
#if !defined(CONFIG_USER_ONLY)
|
1554 |
ptimer_set_limit(opaque, -limit, 0);
|
1555 |
#endif
|
1556 |
} |
1557 |
#endif
|