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1 | 7d85892b | blueswir1 | /*
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2 | 7d85892b | blueswir1 | * QEMU Sparc SBI interrupt controller emulation
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3 | 7d85892b | blueswir1 | *
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4 | 7d85892b | blueswir1 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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5 | 7d85892b | blueswir1 | *
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6 | 7d85892b | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 7d85892b | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 7d85892b | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 7d85892b | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 7d85892b | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 7d85892b | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 7d85892b | blueswir1 | *
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13 | 7d85892b | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 7d85892b | blueswir1 | * all copies or substantial portions of the Software.
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15 | 7d85892b | blueswir1 | *
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16 | 7d85892b | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 7d85892b | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 7d85892b | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 7d85892b | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 7d85892b | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 7d85892b | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 7d85892b | blueswir1 | * THE SOFTWARE.
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23 | 7d85892b | blueswir1 | */
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24 | 7fc06735 | Blue Swirl | |
25 | 7fc06735 | Blue Swirl | #include "sysbus.h" |
26 | 7d85892b | blueswir1 | |
27 | 7d85892b | blueswir1 | //#define DEBUG_IRQ
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28 | 7d85892b | blueswir1 | |
29 | 7d85892b | blueswir1 | #ifdef DEBUG_IRQ
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30 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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31 | 001faf32 | Blue Swirl | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
32 | 7d85892b | blueswir1 | #else
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33 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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34 | 7d85892b | blueswir1 | #endif
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35 | 7d85892b | blueswir1 | |
36 | 7d85892b | blueswir1 | #define MAX_CPUS 16 |
37 | 7d85892b | blueswir1 | |
38 | 7d85892b | blueswir1 | #define SBI_NREGS 16 |
39 | 7d85892b | blueswir1 | |
40 | 7d85892b | blueswir1 | typedef struct SBIState { |
41 | 7fc06735 | Blue Swirl | SysBusDevice busdev; |
42 | 7d85892b | blueswir1 | uint32_t regs[SBI_NREGS]; |
43 | 7d85892b | blueswir1 | uint32_t intreg_pending[MAX_CPUS]; |
44 | 7fc06735 | Blue Swirl | qemu_irq cpu_irqs[MAX_CPUS]; |
45 | 7d85892b | blueswir1 | uint32_t pil_out[MAX_CPUS]; |
46 | 7d85892b | blueswir1 | } SBIState; |
47 | 7d85892b | blueswir1 | |
48 | 7d85892b | blueswir1 | #define SBI_SIZE (SBI_NREGS * 4) |
49 | 7d85892b | blueswir1 | |
50 | 7d85892b | blueswir1 | static void sbi_set_irq(void *opaque, int irq, int level) |
51 | 7d85892b | blueswir1 | { |
52 | 7d85892b | blueswir1 | } |
53 | 7d85892b | blueswir1 | |
54 | c227f099 | Anthony Liguori | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) |
55 | 7d85892b | blueswir1 | { |
56 | 7d85892b | blueswir1 | SBIState *s = opaque; |
57 | 7d85892b | blueswir1 | uint32_t saddr, ret; |
58 | 7d85892b | blueswir1 | |
59 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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60 | 7d85892b | blueswir1 | switch (saddr) {
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61 | 7d85892b | blueswir1 | default:
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62 | 7d85892b | blueswir1 | ret = s->regs[saddr]; |
63 | 7d85892b | blueswir1 | break;
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64 | 7d85892b | blueswir1 | } |
65 | 7d85892b | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
66 | 7d85892b | blueswir1 | |
67 | 7d85892b | blueswir1 | return ret;
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68 | 7d85892b | blueswir1 | } |
69 | 7d85892b | blueswir1 | |
70 | c227f099 | Anthony Liguori | static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
71 | 7d85892b | blueswir1 | { |
72 | 7d85892b | blueswir1 | SBIState *s = opaque; |
73 | 7d85892b | blueswir1 | uint32_t saddr; |
74 | 7d85892b | blueswir1 | |
75 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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76 | 7d85892b | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
77 | 7d85892b | blueswir1 | switch (saddr) {
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78 | 7d85892b | blueswir1 | default:
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79 | 7d85892b | blueswir1 | s->regs[saddr] = val; |
80 | 7d85892b | blueswir1 | break;
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81 | 7d85892b | blueswir1 | } |
82 | 7d85892b | blueswir1 | } |
83 | 7d85892b | blueswir1 | |
84 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const sbi_mem_read[3] = { |
85 | 7c560456 | blueswir1 | NULL,
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86 | 7c560456 | blueswir1 | NULL,
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87 | 7d85892b | blueswir1 | sbi_mem_readl, |
88 | 7d85892b | blueswir1 | }; |
89 | 7d85892b | blueswir1 | |
90 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const sbi_mem_write[3] = { |
91 | 7c560456 | blueswir1 | NULL,
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92 | 7c560456 | blueswir1 | NULL,
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93 | 7d85892b | blueswir1 | sbi_mem_writel, |
94 | 7d85892b | blueswir1 | }; |
95 | 7d85892b | blueswir1 | |
96 | b280fcdf | Blue Swirl | static const VMStateDescription vmstate_sbi = { |
97 | b280fcdf | Blue Swirl | .name ="sbi",
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98 | b280fcdf | Blue Swirl | .version_id = 1,
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99 | b280fcdf | Blue Swirl | .minimum_version_id = 1,
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100 | b280fcdf | Blue Swirl | .minimum_version_id_old = 1,
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101 | b280fcdf | Blue Swirl | .fields = (VMStateField []) { |
102 | b280fcdf | Blue Swirl | VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS), |
103 | b280fcdf | Blue Swirl | VMSTATE_END_OF_LIST() |
104 | 7d85892b | blueswir1 | } |
105 | b280fcdf | Blue Swirl | }; |
106 | 7d85892b | blueswir1 | |
107 | b280fcdf | Blue Swirl | static void sbi_reset(DeviceState *d) |
108 | 7d85892b | blueswir1 | { |
109 | b280fcdf | Blue Swirl | SBIState *s = container_of(d, SBIState, busdev.qdev); |
110 | 7d85892b | blueswir1 | unsigned int i; |
111 | 7d85892b | blueswir1 | |
112 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
113 | 7d85892b | blueswir1 | s->intreg_pending[i] = 0;
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114 | 7d85892b | blueswir1 | } |
115 | 7d85892b | blueswir1 | } |
116 | 7d85892b | blueswir1 | |
117 | 81a322d4 | Gerd Hoffmann | static int sbi_init1(SysBusDevice *dev) |
118 | 7fc06735 | Blue Swirl | { |
119 | 7fc06735 | Blue Swirl | SBIState *s = FROM_SYSBUS(SBIState, dev); |
120 | 7fc06735 | Blue Swirl | int sbi_io_memory;
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121 | 7fc06735 | Blue Swirl | unsigned int i; |
122 | 7fc06735 | Blue Swirl | |
123 | 7fc06735 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
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124 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
125 | 7fc06735 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_irqs[i]); |
126 | 7d85892b | blueswir1 | } |
127 | 7d85892b | blueswir1 | |
128 | 1eed09cb | Avi Kivity | sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s); |
129 | 7fc06735 | Blue Swirl | sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory); |
130 | 7d85892b | blueswir1 | |
131 | 81a322d4 | Gerd Hoffmann | return 0; |
132 | 7fc06735 | Blue Swirl | } |
133 | 7fc06735 | Blue Swirl | |
134 | 7fc06735 | Blue Swirl | static SysBusDeviceInfo sbi_info = {
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135 | 7fc06735 | Blue Swirl | .init = sbi_init1, |
136 | 7fc06735 | Blue Swirl | .qdev.name = "sbi",
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137 | 7fc06735 | Blue Swirl | .qdev.size = sizeof(SBIState),
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138 | b280fcdf | Blue Swirl | .qdev.vmsd = &vmstate_sbi, |
139 | b280fcdf | Blue Swirl | .qdev.reset = sbi_reset, |
140 | 7fc06735 | Blue Swirl | }; |
141 | 7d85892b | blueswir1 | |
142 | 7fc06735 | Blue Swirl | static void sbi_register_devices(void) |
143 | 7fc06735 | Blue Swirl | { |
144 | 7fc06735 | Blue Swirl | sysbus_register_withprop(&sbi_info); |
145 | 7d85892b | blueswir1 | } |
146 | 7fc06735 | Blue Swirl | |
147 | 7fc06735 | Blue Swirl | device_init(sbi_register_devices) |