root / hw / sh_intc.h @ 543fc7b2
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#ifndef __SH_INTC_H__
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#define __SH_INTC_H__
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#include "qemu-common.h" |
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#include "irq.h" |
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typedef unsigned char intc_enum; |
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struct intc_vect {
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intc_enum enum_id; |
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unsigned short vect; |
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}; |
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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struct intc_group {
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intc_enum enum_id; |
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intc_enum enum_ids[32];
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}; |
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#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width; |
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intc_enum enum_ids[32];
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unsigned long value; |
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}; |
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struct intc_prio_reg {
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unsigned long set_reg, clr_reg, reg_width, field_width; |
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intc_enum enum_ids[16];
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unsigned long value; |
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}; |
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#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
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struct intc_source {
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unsigned short vect; |
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intc_enum next_enum_id; |
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int asserted; /* emulates the interrupt signal line from device to intc */ |
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int enable_count;
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int enable_max;
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int pending; /* emulates the result of signal and masking */ |
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struct intc_desc *parent;
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}; |
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struct intc_desc {
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qemu_irq *irqs; |
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struct intc_source *sources;
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int nr_sources;
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struct intc_mask_reg *mask_regs;
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int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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int nr_prio_regs;
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int iomemtype;
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int pending; /* number of interrupt sources that has pending set */ |
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}; |
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int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); |
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struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); |
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void sh_intc_toggle_source(struct intc_source *source, |
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int enable_adj, int assert_adj); |
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void sh_intc_register_sources(struct intc_desc *desc, |
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struct intc_vect *vectors,
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int nr_vectors,
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struct intc_group *groups,
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int nr_groups);
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int sh_intc_init(struct intc_desc *desc, |
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs);
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void sh_intc_set_irl(void *opaque, int n, int level); |
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#endif /* __SH_INTC_H__ */ |