root / target-mips / helper.c @ 54454097
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | e37e863f | bellard | #include <stdarg.h> |
21 | e37e863f | bellard | #include <stdlib.h> |
22 | e37e863f | bellard | #include <stdio.h> |
23 | e37e863f | bellard | #include <string.h> |
24 | e37e863f | bellard | #include <inttypes.h> |
25 | e37e863f | bellard | #include <signal.h> |
26 | e37e863f | bellard | #include <assert.h> |
27 | e37e863f | bellard | |
28 | e37e863f | bellard | #include "cpu.h" |
29 | e37e863f | bellard | #include "exec-all.h" |
30 | 6af0bf9c | bellard | |
31 | 43057ab1 | bellard | enum {
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32 | 43057ab1 | bellard | TLBRET_DIRTY = -4,
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33 | 43057ab1 | bellard | TLBRET_INVALID = -3,
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34 | 43057ab1 | bellard | TLBRET_NOMATCH = -2,
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35 | 43057ab1 | bellard | TLBRET_BADADDR = -1,
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36 | 43057ab1 | bellard | TLBRET_MATCH = 0
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37 | 43057ab1 | bellard | }; |
38 | 43057ab1 | bellard | |
39 | 29929e34 | ths | /* no MMU emulation */
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40 | 29929e34 | ths | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
41 | 6af0bf9c | bellard | target_ulong address, int rw, int access_type) |
42 | 6af0bf9c | bellard | { |
43 | 29929e34 | ths | *physical = address; |
44 | 29929e34 | ths | *prot = PAGE_READ | PAGE_WRITE; |
45 | 29929e34 | ths | return TLBRET_MATCH;
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46 | 29929e34 | ths | } |
47 | 29929e34 | ths | |
48 | 29929e34 | ths | /* fixed mapping MMU emulation */
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49 | 29929e34 | ths | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
50 | 29929e34 | ths | target_ulong address, int rw, int access_type) |
51 | 29929e34 | ths | { |
52 | 29929e34 | ths | if (address <= (int32_t)0x7FFFFFFFUL) { |
53 | 29929e34 | ths | if (!(env->CP0_Status & (1 << CP0St_ERL))) |
54 | 29929e34 | ths | *physical = address + 0x40000000UL;
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55 | 29929e34 | ths | else
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56 | 29929e34 | ths | *physical = address; |
57 | 29929e34 | ths | } else if (address <= (int32_t)0xBFFFFFFFUL) |
58 | 29929e34 | ths | *physical = address & 0x1FFFFFFF;
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59 | 29929e34 | ths | else
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60 | 29929e34 | ths | *physical = address; |
61 | 29929e34 | ths | |
62 | 29929e34 | ths | *prot = PAGE_READ | PAGE_WRITE; |
63 | 29929e34 | ths | return TLBRET_MATCH;
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64 | 29929e34 | ths | } |
65 | 29929e34 | ths | |
66 | 29929e34 | ths | /* MIPS32/MIPS64 R4000-style MMU emulation */
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67 | 29929e34 | ths | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, |
68 | 29929e34 | ths | target_ulong address, int rw, int access_type) |
69 | 29929e34 | ths | { |
70 | 925fd0f2 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
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71 | 3b1c8be4 | ths | int i;
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72 | 6af0bf9c | bellard | |
73 | ead9360e | ths | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
74 | ead9360e | ths | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
75 | 3b1c8be4 | ths | /* 1k pages are not supported. */
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76 | f2e9ebef | ths | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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77 | 3b1c8be4 | ths | target_ulong tag = address & ~mask; |
78 | f2e9ebef | ths | target_ulong VPN = tlb->VPN & ~mask; |
79 | 100ce988 | ths | #ifdef TARGET_MIPS64
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80 | e034e2c3 | ths | tag &= env->SEGMask; |
81 | 100ce988 | ths | #endif
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82 | 3b1c8be4 | ths | |
83 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
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84 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
85 | 6af0bf9c | bellard | /* TLB match */
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86 | f2e9ebef | ths | int n = !!(address & mask & ~(mask >> 1)); |
87 | 6af0bf9c | bellard | /* Check access rights */
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88 | f2e9ebef | ths | if (!(n ? tlb->V1 : tlb->V0))
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89 | 43057ab1 | bellard | return TLBRET_INVALID;
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90 | f2e9ebef | ths | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
91 | 3b1c8be4 | ths | *physical = tlb->PFN[n] | (address & (mask >> 1));
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92 | 9fb63ac2 | bellard | *prot = PAGE_READ; |
93 | 98c1b82b | pbrook | if (n ? tlb->D1 : tlb->D0)
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94 | 9fb63ac2 | bellard | *prot |= PAGE_WRITE; |
95 | 43057ab1 | bellard | return TLBRET_MATCH;
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96 | 6af0bf9c | bellard | } |
97 | 43057ab1 | bellard | return TLBRET_DIRTY;
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98 | 6af0bf9c | bellard | } |
99 | 6af0bf9c | bellard | } |
100 | 43057ab1 | bellard | return TLBRET_NOMATCH;
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101 | 6af0bf9c | bellard | } |
102 | 6af0bf9c | bellard | |
103 | 43057ab1 | bellard | static int get_physical_address (CPUState *env, target_ulong *physical, |
104 | 43057ab1 | bellard | int *prot, target_ulong address,
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105 | 43057ab1 | bellard | int rw, int access_type) |
106 | 6af0bf9c | bellard | { |
107 | b4ab4b4e | ths | /* User mode can only access useg/xuseg */
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108 | 43057ab1 | bellard | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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109 | b4ab4b4e | ths | #ifdef TARGET_MIPS64
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110 | b4ab4b4e | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
111 | b4ab4b4e | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
112 | b4ab4b4e | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
113 | b4ab4b4e | ths | #endif
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114 | 43057ab1 | bellard | int ret = TLBRET_MATCH;
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115 | 43057ab1 | bellard | |
116 | 6af0bf9c | bellard | #if 0
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117 | 6af0bf9c | bellard | if (logfile) {
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118 | 6af0bf9c | bellard | fprintf(logfile, "user mode %d h %08x\n",
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119 | 6af0bf9c | bellard | user_mode, env->hflags);
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120 | 6af0bf9c | bellard | }
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121 | 6af0bf9c | bellard | #endif
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122 | b4ab4b4e | ths | |
123 | b4ab4b4e | ths | #ifdef TARGET_MIPS64
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124 | b4ab4b4e | ths | if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) |
125 | b4ab4b4e | ths | return TLBRET_BADADDR;
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126 | b4ab4b4e | ths | #else
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127 | 6af0bf9c | bellard | if (user_mode && address > 0x7FFFFFFFUL) |
128 | 43057ab1 | bellard | return TLBRET_BADADDR;
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129 | b4ab4b4e | ths | #endif
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130 | b4ab4b4e | ths | |
131 | b4ab4b4e | ths | if (address <= (int32_t)0x7FFFFFFFUL) { |
132 | b4ab4b4e | ths | /* useg */
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133 | 996ba2cc | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
134 | 29929e34 | ths | *physical = address & 0xFFFFFFFF;
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135 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
136 | 996ba2cc | ths | } else {
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137 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
138 | 6af0bf9c | bellard | } |
139 | b4ab4b4e | ths | #ifdef TARGET_MIPS64
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140 | b4ab4b4e | ths | /*
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141 | b4ab4b4e | ths | XXX: Assuming :
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142 | b4ab4b4e | ths | - PABITS = 36 (correct for MIPS64R1)
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143 | b4ab4b4e | ths | */
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144 | b4ab4b4e | ths | } else if (address < 0x3FFFFFFFFFFFFFFFULL) { |
145 | b4ab4b4e | ths | /* xuseg */
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146 | e034e2c3 | ths | if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
147 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
148 | b4ab4b4e | ths | } else {
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149 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
150 | b4ab4b4e | ths | } |
151 | b4ab4b4e | ths | } else if (address < 0x7FFFFFFFFFFFFFFFULL) { |
152 | b4ab4b4e | ths | /* xsseg */
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153 | e034e2c3 | ths | if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
154 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
155 | b4ab4b4e | ths | } else {
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156 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
157 | b4ab4b4e | ths | } |
158 | b4ab4b4e | ths | } else if (address < 0xBFFFFFFFFFFFFFFFULL) { |
159 | b4ab4b4e | ths | /* xkphys */
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160 | b4ab4b4e | ths | /* XXX: check supervisor mode */
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161 | e034e2c3 | ths | if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) |
162 | b4ab4b4e | ths | { |
163 | e034e2c3 | ths | *physical = address & 0X0000000FFFFFFFFFULL;
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164 | b4ab4b4e | ths | *prot = PAGE_READ | PAGE_WRITE; |
165 | b4ab4b4e | ths | } else {
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166 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
167 | b4ab4b4e | ths | } |
168 | b4ab4b4e | ths | } else if (address < 0xFFFFFFFF7FFFFFFFULL) { |
169 | b4ab4b4e | ths | /* xkseg */
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170 | b4ab4b4e | ths | /* XXX: check supervisor mode */
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171 | e034e2c3 | ths | if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { |
172 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
173 | b4ab4b4e | ths | } else {
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174 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
175 | b4ab4b4e | ths | } |
176 | b4ab4b4e | ths | #endif
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177 | 5dc4b744 | ths | } else if (address < (int32_t)0xA0000000UL) { |
178 | 6af0bf9c | bellard | /* kseg0 */
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179 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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180 | 5dc4b744 | ths | *physical = address - (int32_t)0x80000000UL;
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181 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
182 | 5dc4b744 | ths | } else if (address < (int32_t)0xC0000000UL) { |
183 | 6af0bf9c | bellard | /* kseg1 */
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184 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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185 | 5dc4b744 | ths | *physical = address - (int32_t)0xA0000000UL;
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186 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
187 | 5dc4b744 | ths | } else if (address < (int32_t)0xE0000000UL) { |
188 | 6af0bf9c | bellard | /* kseg2 */
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189 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
190 | 6af0bf9c | bellard | } else {
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191 | 6af0bf9c | bellard | /* kseg3 */
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192 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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193 | 6af0bf9c | bellard | /* XXX: debug segment is not emulated */
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194 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
195 | 6af0bf9c | bellard | } |
196 | 6af0bf9c | bellard | #if 0
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197 | 6af0bf9c | bellard | if (logfile) {
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198 | 3594c774 | ths | fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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199 | c570fd16 | ths | address, rw, access_type, *physical, *prot, ret);
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200 | 6af0bf9c | bellard | }
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201 | 6af0bf9c | bellard | #endif
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202 | 6af0bf9c | bellard | |
203 | 6af0bf9c | bellard | return ret;
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204 | 6af0bf9c | bellard | } |
205 | 6af0bf9c | bellard | |
206 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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207 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
208 | 6af0bf9c | bellard | { |
209 | 6af0bf9c | bellard | return addr;
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210 | 6af0bf9c | bellard | } |
211 | 6af0bf9c | bellard | #else
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212 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
213 | 6af0bf9c | bellard | { |
214 | 6af0bf9c | bellard | target_ulong phys_addr; |
215 | 6af0bf9c | bellard | int prot;
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216 | 6af0bf9c | bellard | |
217 | 6af0bf9c | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
218 | 6af0bf9c | bellard | return -1; |
219 | 6af0bf9c | bellard | return phys_addr;
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220 | 6af0bf9c | bellard | } |
221 | 6af0bf9c | bellard | |
222 | 6af0bf9c | bellard | void cpu_mips_init_mmu (CPUState *env)
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223 | 6af0bf9c | bellard | { |
224 | 6af0bf9c | bellard | } |
225 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
226 | 6af0bf9c | bellard | |
227 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
228 | 6af0bf9c | bellard | int is_user, int is_softmmu) |
229 | 6af0bf9c | bellard | { |
230 | 6af0bf9c | bellard | target_ulong physical; |
231 | 6af0bf9c | bellard | int prot;
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232 | 6af0bf9c | bellard | int exception = 0, error_code = 0; |
233 | 6af0bf9c | bellard | int access_type;
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234 | 6af0bf9c | bellard | int ret = 0; |
235 | 6af0bf9c | bellard | |
236 | 6af0bf9c | bellard | if (logfile) {
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237 | 4ad40f36 | bellard | #if 0
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238 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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239 | 4ad40f36 | bellard | #endif
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240 | 3594c774 | ths | fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
241 | ead9360e | ths | __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu); |
242 | 6af0bf9c | bellard | } |
243 | 4ad40f36 | bellard | |
244 | 4ad40f36 | bellard | rw &= 1;
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245 | 4ad40f36 | bellard | |
246 | 6af0bf9c | bellard | /* data access */
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247 | 6af0bf9c | bellard | /* XXX: put correct access by using cpu_restore_state()
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248 | 6af0bf9c | bellard | correctly */
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249 | 6af0bf9c | bellard | access_type = ACCESS_INT; |
250 | 6af0bf9c | bellard | if (env->user_mode_only) {
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251 | 6af0bf9c | bellard | /* user mode only emulation */
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252 | 43057ab1 | bellard | ret = TLBRET_NOMATCH; |
253 | 6af0bf9c | bellard | goto do_fault;
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254 | 6af0bf9c | bellard | } |
255 | 6af0bf9c | bellard | ret = get_physical_address(env, &physical, &prot, |
256 | 6af0bf9c | bellard | address, rw, access_type); |
257 | 6af0bf9c | bellard | if (logfile) {
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258 | 3594c774 | ths | fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
259 | 6af0bf9c | bellard | __func__, address, ret, physical, prot); |
260 | 6af0bf9c | bellard | } |
261 | 43057ab1 | bellard | if (ret == TLBRET_MATCH) {
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262 | 43057ab1 | bellard | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
263 | 43057ab1 | bellard | physical & TARGET_PAGE_MASK, prot, |
264 | 43057ab1 | bellard | is_user, is_softmmu); |
265 | 6af0bf9c | bellard | } else if (ret < 0) { |
266 | 6af0bf9c | bellard | do_fault:
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267 | 6af0bf9c | bellard | switch (ret) {
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268 | 6af0bf9c | bellard | default:
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269 | 43057ab1 | bellard | case TLBRET_BADADDR:
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270 | 6af0bf9c | bellard | /* Reference to kernel address from user mode or supervisor mode */
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271 | 6af0bf9c | bellard | /* Reference to supervisor address from user mode */
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272 | 6af0bf9c | bellard | if (rw)
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273 | 6af0bf9c | bellard | exception = EXCP_AdES; |
274 | 6af0bf9c | bellard | else
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275 | 6af0bf9c | bellard | exception = EXCP_AdEL; |
276 | 6af0bf9c | bellard | break;
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277 | 43057ab1 | bellard | case TLBRET_NOMATCH:
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278 | 6af0bf9c | bellard | /* No TLB match for a mapped address */
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279 | 6af0bf9c | bellard | if (rw)
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280 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
281 | 6af0bf9c | bellard | else
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282 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
283 | 6af0bf9c | bellard | error_code = 1;
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284 | 6af0bf9c | bellard | break;
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285 | 43057ab1 | bellard | case TLBRET_INVALID:
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286 | 6af0bf9c | bellard | /* TLB match with no valid bit */
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287 | 6af0bf9c | bellard | if (rw)
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288 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
289 | 6af0bf9c | bellard | else
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290 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
291 | 6af0bf9c | bellard | break;
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292 | 43057ab1 | bellard | case TLBRET_DIRTY:
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293 | 6af0bf9c | bellard | /* TLB match but 'D' bit is cleared */
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294 | 6af0bf9c | bellard | exception = EXCP_LTLBL; |
295 | 6af0bf9c | bellard | break;
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296 | 3b46e624 | ths | |
297 | 6af0bf9c | bellard | } |
298 | 6af0bf9c | bellard | /* Raise exception */
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299 | 6af0bf9c | bellard | env->CP0_BadVAddr = address; |
300 | 100ce988 | ths | env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
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301 | 4ad40f36 | bellard | ((address >> 9) & 0x007ffff0); |
302 | 6af0bf9c | bellard | env->CP0_EntryHi = |
303 | 43057ab1 | bellard | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
304 | 100ce988 | ths | #ifdef TARGET_MIPS64
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305 | e034e2c3 | ths | env->CP0_EntryHi &= env->SEGMask; |
306 | e034e2c3 | ths | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | |
307 | e034e2c3 | ths | ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | |
308 | e034e2c3 | ths | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); |
309 | 100ce988 | ths | #endif
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310 | 6af0bf9c | bellard | env->exception_index = exception; |
311 | 6af0bf9c | bellard | env->error_code = error_code; |
312 | 6af0bf9c | bellard | ret = 1;
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313 | 6af0bf9c | bellard | } |
314 | 6af0bf9c | bellard | |
315 | 6af0bf9c | bellard | return ret;
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316 | 6af0bf9c | bellard | } |
317 | 6af0bf9c | bellard | |
318 | ca7c2b1b | ths | #if defined(CONFIG_USER_ONLY)
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319 | ca7c2b1b | ths | void do_interrupt (CPUState *env)
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320 | ca7c2b1b | ths | { |
321 | ca7c2b1b | ths | env->exception_index = EXCP_NONE; |
322 | ca7c2b1b | ths | } |
323 | ca7c2b1b | ths | #else
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324 | 6af0bf9c | bellard | void do_interrupt (CPUState *env)
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325 | 6af0bf9c | bellard | { |
326 | aa328add | ths | target_ulong offset; |
327 | 6af0bf9c | bellard | int cause = -1; |
328 | 6af0bf9c | bellard | |
329 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
330 | 3594c774 | ths | fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
331 | ead9360e | ths | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index); |
332 | 6af0bf9c | bellard | } |
333 | 6af0bf9c | bellard | if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
334 | 6af0bf9c | bellard | (env->hflags & MIPS_HFLAG_DM)) |
335 | 6af0bf9c | bellard | env->exception_index = EXCP_DINT; |
336 | 6af0bf9c | bellard | offset = 0x180;
|
337 | 6af0bf9c | bellard | switch (env->exception_index) {
|
338 | 6af0bf9c | bellard | case EXCP_DSS:
|
339 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DSS;
|
340 | 6af0bf9c | bellard | /* Debug single step cannot be raised inside a delay slot and
|
341 | 6af0bf9c | bellard | * resume will always occur on the next instruction
|
342 | 6af0bf9c | bellard | * (but we assume the pc has always been updated during
|
343 | 6af0bf9c | bellard | * code translation).
|
344 | 6af0bf9c | bellard | */
|
345 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc]; |
346 | 6af0bf9c | bellard | goto enter_debug_mode;
|
347 | 6af0bf9c | bellard | case EXCP_DINT:
|
348 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DINT;
|
349 | 6af0bf9c | bellard | goto set_DEPC;
|
350 | 6af0bf9c | bellard | case EXCP_DIB:
|
351 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DIB;
|
352 | 6af0bf9c | bellard | goto set_DEPC;
|
353 | 6af0bf9c | bellard | case EXCP_DBp:
|
354 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DBp;
|
355 | 6af0bf9c | bellard | goto set_DEPC;
|
356 | 6af0bf9c | bellard | case EXCP_DDBS:
|
357 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBS;
|
358 | 6af0bf9c | bellard | goto set_DEPC;
|
359 | 6af0bf9c | bellard | case EXCP_DDBL:
|
360 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBL;
|
361 | 6af0bf9c | bellard | set_DEPC:
|
362 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
363 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
364 | aa328add | ths | come back to the jump. */
|
365 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc] - 4;
|
366 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
367 | 6af0bf9c | bellard | } else {
|
368 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc]; |
369 | 6af0bf9c | bellard | } |
370 | 6af0bf9c | bellard | enter_debug_mode:
|
371 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
372 | 24c7b0e3 | ths | env->hflags &= ~MIPS_HFLAG_UM; |
373 | 6af0bf9c | bellard | /* EJTAG probe trap enable is not implemented... */
|
374 | 0a6de750 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
375 | 0a6de750 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
376 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00480;
|
377 | 6af0bf9c | bellard | break;
|
378 | 6af0bf9c | bellard | case EXCP_RESET:
|
379 | aa328add | ths | cpu_reset(env); |
380 | aa328add | ths | break;
|
381 | 6af0bf9c | bellard | case EXCP_SRESET:
|
382 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_SR);
|
383 | fd88b6ab | ths | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
384 | 6af0bf9c | bellard | goto set_error_EPC;
|
385 | 6af0bf9c | bellard | case EXCP_NMI:
|
386 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_NMI);
|
387 | 6af0bf9c | bellard | set_error_EPC:
|
388 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
389 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
390 | aa328add | ths | come back to the jump. */
|
391 | ead9360e | ths | env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
|
392 | ecd78a0a | pbrook | env->hflags &= ~MIPS_HFLAG_BMASK; |
393 | 6af0bf9c | bellard | } else {
|
394 | ead9360e | ths | env->CP0_ErrorEPC = env->PC[env->current_tc]; |
395 | 6af0bf9c | bellard | } |
396 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
397 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
398 | 24c7b0e3 | ths | env->hflags &= ~MIPS_HFLAG_UM; |
399 | 0a6de750 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
400 | 0a6de750 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
401 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00000;
|
402 | 6af0bf9c | bellard | break;
|
403 | 6af0bf9c | bellard | case EXCP_MCHECK:
|
404 | 6af0bf9c | bellard | cause = 24;
|
405 | 6af0bf9c | bellard | goto set_EPC;
|
406 | 6af0bf9c | bellard | case EXCP_EXT_INTERRUPT:
|
407 | 6af0bf9c | bellard | cause = 0;
|
408 | 6af0bf9c | bellard | if (env->CP0_Cause & (1 << CP0Ca_IV)) |
409 | 6af0bf9c | bellard | offset = 0x200;
|
410 | 6af0bf9c | bellard | goto set_EPC;
|
411 | 6af0bf9c | bellard | case EXCP_DWATCH:
|
412 | 6af0bf9c | bellard | cause = 23;
|
413 | 6af0bf9c | bellard | /* XXX: TODO: manage defered watch exceptions */
|
414 | 6af0bf9c | bellard | goto set_EPC;
|
415 | 6af0bf9c | bellard | case EXCP_AdEL:
|
416 | 6af0bf9c | bellard | cause = 4;
|
417 | 6af0bf9c | bellard | goto set_EPC;
|
418 | beb811bd | ths | case EXCP_AdES:
|
419 | beb811bd | ths | cause = 5;
|
420 | beb811bd | ths | goto set_EPC;
|
421 | 6af0bf9c | bellard | case EXCP_TLBL:
|
422 | 6af0bf9c | bellard | cause = 2;
|
423 | 100ce988 | ths | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
424 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
425 | 100ce988 | ths | int R = env->CP0_BadVAddr >> 62; |
426 | 100ce988 | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
427 | 100ce988 | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
428 | 100ce988 | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
429 | 100ce988 | ths | |
430 | 100ce988 | ths | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
431 | 100ce988 | ths | offset = 0x080;
|
432 | 100ce988 | ths | else
|
433 | 100ce988 | ths | #endif
|
434 | 100ce988 | ths | offset = 0x000;
|
435 | 100ce988 | ths | } |
436 | 6af0bf9c | bellard | goto set_EPC;
|
437 | 6af0bf9c | bellard | case EXCP_IBE:
|
438 | 6af0bf9c | bellard | cause = 6;
|
439 | 6af0bf9c | bellard | goto set_EPC;
|
440 | 6af0bf9c | bellard | case EXCP_DBE:
|
441 | 6af0bf9c | bellard | cause = 7;
|
442 | 6af0bf9c | bellard | goto set_EPC;
|
443 | 6af0bf9c | bellard | case EXCP_SYSCALL:
|
444 | 6af0bf9c | bellard | cause = 8;
|
445 | 6af0bf9c | bellard | goto set_EPC;
|
446 | 6af0bf9c | bellard | case EXCP_BREAK:
|
447 | 6af0bf9c | bellard | cause = 9;
|
448 | 6af0bf9c | bellard | goto set_EPC;
|
449 | 6af0bf9c | bellard | case EXCP_RI:
|
450 | 6af0bf9c | bellard | cause = 10;
|
451 | 6af0bf9c | bellard | goto set_EPC;
|
452 | 6af0bf9c | bellard | case EXCP_CpU:
|
453 | 6af0bf9c | bellard | cause = 11;
|
454 | 39d51eb8 | ths | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
455 | 39d51eb8 | ths | (env->error_code << CP0Ca_CE); |
456 | 6af0bf9c | bellard | goto set_EPC;
|
457 | 6af0bf9c | bellard | case EXCP_OVERFLOW:
|
458 | 6af0bf9c | bellard | cause = 12;
|
459 | 6af0bf9c | bellard | goto set_EPC;
|
460 | 6af0bf9c | bellard | case EXCP_TRAP:
|
461 | 6af0bf9c | bellard | cause = 13;
|
462 | 6af0bf9c | bellard | goto set_EPC;
|
463 | 5a5012ec | ths | case EXCP_FPE:
|
464 | 5a5012ec | ths | cause = 15;
|
465 | 5a5012ec | ths | goto set_EPC;
|
466 | 6af0bf9c | bellard | case EXCP_LTLBL:
|
467 | 6af0bf9c | bellard | cause = 1;
|
468 | 6af0bf9c | bellard | goto set_EPC;
|
469 | 6af0bf9c | bellard | case EXCP_TLBS:
|
470 | 6af0bf9c | bellard | cause = 3;
|
471 | ead9360e | ths | goto set_EPC;
|
472 | ead9360e | ths | case EXCP_THREAD:
|
473 | ead9360e | ths | cause = 25;
|
474 | 100ce988 | ths | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
475 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
476 | 100ce988 | ths | int R = env->CP0_BadVAddr >> 62; |
477 | 100ce988 | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
478 | 100ce988 | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
479 | 100ce988 | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
480 | 100ce988 | ths | |
481 | 100ce988 | ths | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
482 | 100ce988 | ths | offset = 0x080;
|
483 | 100ce988 | ths | else
|
484 | 100ce988 | ths | #endif
|
485 | 100ce988 | ths | offset = 0x000;
|
486 | 100ce988 | ths | } |
487 | 6af0bf9c | bellard | set_EPC:
|
488 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
489 | 24c7b0e3 | ths | if (env->hflags & MIPS_HFLAG_BMASK) {
|
490 | 24c7b0e3 | ths | /* If the exception was raised from a delay slot,
|
491 | 24c7b0e3 | ths | come back to the jump. */
|
492 | ead9360e | ths | env->CP0_EPC = env->PC[env->current_tc] - 4;
|
493 | 39d51eb8 | ths | env->CP0_Cause |= (1 << CP0Ca_BD);
|
494 | 24c7b0e3 | ths | } else {
|
495 | ead9360e | ths | env->CP0_EPC = env->PC[env->current_tc]; |
496 | 24c7b0e3 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
497 | 24c7b0e3 | ths | } |
498 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_EXL);
|
499 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
500 | 24c7b0e3 | ths | env->hflags &= ~MIPS_HFLAG_UM; |
501 | 6af0bf9c | bellard | } |
502 | c53f4a62 | ths | env->hflags &= ~MIPS_HFLAG_BMASK; |
503 | aa328add | ths | if (env->CP0_Status & (1 << CP0St_BEV)) { |
504 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00200;
|
505 | aa328add | ths | } else {
|
506 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
|
507 | aa328add | ths | } |
508 | ead9360e | ths | env->PC[env->current_tc] += offset; |
509 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
510 | 6af0bf9c | bellard | break;
|
511 | 6af0bf9c | bellard | default:
|
512 | 6af0bf9c | bellard | if (logfile) {
|
513 | 6af0bf9c | bellard | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
514 | 6af0bf9c | bellard | env->exception_index); |
515 | 6af0bf9c | bellard | } |
516 | 6af0bf9c | bellard | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
517 | 6af0bf9c | bellard | exit(1);
|
518 | 6af0bf9c | bellard | } |
519 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
520 | 3594c774 | ths | fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
521 | 3594c774 | ths | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
522 | ead9360e | ths | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index, |
523 | 6af0bf9c | bellard | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
524 | 6af0bf9c | bellard | env->CP0_DEPC); |
525 | 6af0bf9c | bellard | } |
526 | 6af0bf9c | bellard | env->exception_index = EXCP_NONE; |
527 | 6af0bf9c | bellard | } |
528 | ca7c2b1b | ths | #endif /* !defined(CONFIG_USER_ONLY) */ |
529 | 2ee4aed8 | bellard | |
530 | 29929e34 | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
531 | 2ee4aed8 | bellard | { |
532 | 29929e34 | ths | r4k_tlb_t *tlb; |
533 | 3b1c8be4 | ths | target_ulong addr; |
534 | 3b1c8be4 | ths | target_ulong end; |
535 | 3b1c8be4 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
536 | 3b1c8be4 | ths | target_ulong mask; |
537 | 2ee4aed8 | bellard | |
538 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
539 | f2e9ebef | ths | /* The qemu TLB is flushed when the ASID changes, so no need to
|
540 | 2ee4aed8 | bellard | flush these entries again. */
|
541 | 2ee4aed8 | bellard | if (tlb->G == 0 && tlb->ASID != ASID) { |
542 | 2ee4aed8 | bellard | return;
|
543 | 2ee4aed8 | bellard | } |
544 | 2ee4aed8 | bellard | |
545 | ead9360e | ths | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
|
546 | 2ee4aed8 | bellard | /* For tlbwr, we can shadow the discarded entry into
|
547 | 2ee4aed8 | bellard | a new (fake) TLB entry, as long as the guest can not
|
548 | 2ee4aed8 | bellard | tell that it's there. */
|
549 | ead9360e | ths | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
550 | ead9360e | ths | env->tlb->tlb_in_use++; |
551 | 2ee4aed8 | bellard | return;
|
552 | 2ee4aed8 | bellard | } |
553 | 2ee4aed8 | bellard | |
554 | 3b1c8be4 | ths | /* 1k pages are not supported. */
|
555 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
556 | 3b1c8be4 | ths | if (tlb->V0) {
|
557 | f2e9ebef | ths | addr = tlb->VPN & ~mask; |
558 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
559 | e034e2c3 | ths | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
560 | 100ce988 | ths | addr |= 0x3FFFFF0000000000ULL;
|
561 | 100ce988 | ths | } |
562 | 100ce988 | ths | #endif
|
563 | 3b1c8be4 | ths | end = addr | (mask >> 1);
|
564 | 3b1c8be4 | ths | while (addr < end) {
|
565 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
566 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
567 | 3b1c8be4 | ths | } |
568 | 3b1c8be4 | ths | } |
569 | 3b1c8be4 | ths | if (tlb->V1) {
|
570 | f2e9ebef | ths | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
571 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
572 | e034e2c3 | ths | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
573 | 100ce988 | ths | addr |= 0x3FFFFF0000000000ULL;
|
574 | 100ce988 | ths | } |
575 | 100ce988 | ths | #endif
|
576 | 3b1c8be4 | ths | end = addr | mask; |
577 | 3b1c8be4 | ths | while (addr < end) {
|
578 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
579 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
580 | 3b1c8be4 | ths | } |
581 | 3b1c8be4 | ths | } |
582 | 2ee4aed8 | bellard | } |