Revision 544c4be6 hw/ide.c
b/hw/ide.c | ||
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2590 | 2590 |
pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ |
2591 | 2591 |
} |
2592 | 2592 |
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2593 |
void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) |
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2594 |
{ |
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2595 |
PCIIDEState *d; |
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2596 |
uint8_t *pci_conf; |
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2597 |
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2598 |
/* register a function 1 of PIIX */ |
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2599 |
d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE", |
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2600 |
sizeof(PCIIDEState), |
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2601 |
devfn, |
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NULL, NULL); |
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2603 |
d->type = IDE_TYPE_PIIX3; |
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2604 |
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2605 |
pci_conf = d->dev.config; |
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2606 |
pci_conf[0x00] = 0x86; // Intel |
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2607 |
pci_conf[0x01] = 0x80; |
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2608 |
pci_conf[0x02] = 0x30; |
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2609 |
pci_conf[0x03] = 0x12; |
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2610 |
pci_conf[0x08] = 0x02; // Step A1 |
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2611 |
pci_conf[0x09] = 0x80; // legacy ATA mode |
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2612 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
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2613 |
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
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2614 |
pci_conf[0x0e] = 0x00; // header_type |
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2615 |
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2616 |
piix3_reset(d); |
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2617 |
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2618 |
pci_register_io_region((PCIDevice *)d, 4, 0x10, |
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2619 |
PCI_ADDRESS_SPACE_IO, bmdma_map); |
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2620 |
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2621 |
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], |
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2622 |
pic_set_irq_new, isa_pic, 14); |
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2623 |
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], |
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2624 |
pic_set_irq_new, isa_pic, 15); |
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2625 |
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
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2626 |
ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
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2627 |
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2628 |
register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
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2629 |
} |
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2630 |
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2631 | 2593 |
/* hd_table must contain 4 block drivers */ |
2632 | 2594 |
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ |
2633 | 2595 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) |
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