Revision 546921ea hw/net/xgmac.c
| b/hw/net/xgmac.c | ||
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| 135 | 135 |
uint64_t rx_mcast; |
| 136 | 136 |
} RxTxStats; |
| 137 | 137 |
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#define TYPE_XGMAC "xgmac" |
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#define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC) |
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typedef struct XgmacState {
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SysBusDevice busdev; |
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SysBusDevice parent_obj; |
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|
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MemoryRegion iomem; |
| 141 | 145 |
qemu_irq sbd_irq; |
| 142 | 146 |
qemu_irq pmt_irq; |
| ... | ... | |
| 173 | 177 |
} |
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}; |
| 175 | 179 |
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static void xgmac_read_desc(struct XgmacState *s, struct desc *d, int rx)
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static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx) |
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{
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uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] : |
| 179 | 183 |
s->regs[DMA_CUR_TX_DESC_ADDR]; |
| 180 | 184 |
cpu_physical_memory_read(addr, d, sizeof(*d)); |
| 181 | 185 |
} |
| 182 | 186 |
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static void xgmac_write_desc(struct XgmacState *s, struct desc *d, int rx)
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static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx) |
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{
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int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR; |
| 186 | 190 |
uint32_t addr = s->regs[reg]; |
| ... | ... | |
| 195 | 199 |
cpu_physical_memory_write(addr, d, sizeof(*d)); |
| 196 | 200 |
} |
| 197 | 201 |
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static void xgmac_enet_send(struct XgmacState *s)
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static void xgmac_enet_send(XgmacState *s) |
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{
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struct desc bd; |
| 201 | 205 |
int frame_size; |
| ... | ... | |
| 246 | 250 |
} |
| 247 | 251 |
} |
| 248 | 252 |
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static void enet_update_irq(struct XgmacState *s)
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static void enet_update_irq(XgmacState *s) |
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{
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int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA]; |
| 252 | 256 |
qemu_set_irq(s->sbd_irq, !!stat); |
| ... | ... | |
| 254 | 258 |
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static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) |
| 256 | 260 |
{
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struct XgmacState *s = opaque;
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XgmacState *s = opaque; |
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uint64_t r = 0; |
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addr >>= 2; |
| 260 | 264 |
|
| ... | ... | |
| 274 | 278 |
static void enet_write(void *opaque, hwaddr addr, |
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uint64_t value, unsigned size) |
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{
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struct XgmacState *s = opaque;
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XgmacState *s = opaque; |
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addr >>= 2; |
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switch (addr) {
|
| ... | ... | |
| 310 | 314 |
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static int eth_can_rx(NetClientState *nc) |
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{
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struct XgmacState *s = qemu_get_nic_opaque(nc);
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XgmacState *s = qemu_get_nic_opaque(nc); |
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/* RX enabled? */ |
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return s->regs[DMA_CONTROL] & DMA_CONTROL_SR; |
| ... | ... | |
| 318 | 322 |
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static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
| 320 | 324 |
{
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struct XgmacState *s = qemu_get_nic_opaque(nc);
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XgmacState *s = qemu_get_nic_opaque(nc); |
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static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
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0xff, 0xff, 0xff}; |
| 324 | 328 |
int unicast, broadcast, multicast; |
| ... | ... | |
| 366 | 370 |
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static void eth_cleanup(NetClientState *nc) |
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{
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struct XgmacState *s = qemu_get_nic_opaque(nc); |
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XgmacState *s = qemu_get_nic_opaque(nc); |
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s->nic = NULL; |
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} |
| 372 | 377 |
|
| ... | ... | |
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.cleanup = eth_cleanup, |
| 379 | 384 |
}; |
| 380 | 385 |
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static int xgmac_enet_init(SysBusDevice *dev)
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static int xgmac_enet_init(SysBusDevice *sbd)
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{
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struct XgmacState *s = FROM_SYSBUS(typeof(*s), dev); |
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DeviceState *dev = DEVICE(sbd); |
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XgmacState *s = XGMAC(dev); |
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| 384 | 390 |
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memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s, |
| 386 | 392 |
"xgmac", 0x1000); |
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->sbd_irq);
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sysbus_init_irq(dev, &s->pmt_irq);
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sysbus_init_irq(dev, &s->mci_irq);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->sbd_irq);
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sysbus_init_irq(sbd, &s->pmt_irq);
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sysbus_init_irq(sbd, &s->mci_irq);
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| 391 | 397 |
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qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 393 | 399 |
s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf, |
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object_get_typename(OBJECT(dev)), dev->qdev.id, s);
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object_get_typename(OBJECT(dev)), dev->id, s); |
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qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
| 396 | 402 |
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s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) | |
| ... | ... | |
| 405 | 411 |
} |
| 406 | 412 |
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static Property xgmac_properties[] = {
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DEFINE_NIC_PROPERTIES(struct XgmacState, conf),
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DEFINE_NIC_PROPERTIES(XgmacState, conf), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
| 411 | 417 |
|
| ... | ... | |
| 420 | 426 |
} |
| 421 | 427 |
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static const TypeInfo xgmac_enet_info = {
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.name = "xgmac",
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.name = TYPE_XGMAC,
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(struct XgmacState),
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.instance_size = sizeof(XgmacState), |
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.class_init = xgmac_enet_class_init, |
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}; |
| 428 | 434 |
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