root / target-i386 / helper2.c @ 5516d670
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/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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//#define DEBUG_MMU
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#ifdef USE_CODE_COPY
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#include <asm/ldt.h> |
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#include <linux/unistd.h> |
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#include <linux/version.h> |
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|
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_syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount) |
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66) |
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#define modify_ldt_ldt_s user_desc
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#endif
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#endif /* USE_CODE_COPY */ |
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CPUX86State *cpu_x86_init(void)
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{
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CPUX86State *env; |
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static int inited; |
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cpu_exec_init(); |
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env = malloc(sizeof(CPUX86State));
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if (!env)
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return NULL; |
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memset(env, 0, sizeof(CPUX86State)); |
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init(); |
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} |
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#ifdef USE_CODE_COPY
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/* testing code for code copy case */
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{
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struct modify_ldt_ldt_s ldt;
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ldt.entry_number = 1;
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ldt.base_addr = (unsigned long)env; |
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ldt.limit = (sizeof(CPUState) + 0xfff) >> 12; |
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ldt.seg_32bit = 1;
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ldt.contents = MODIFY_LDT_CONTENTS_DATA; |
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */ |
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asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7)); |
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} |
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#endif
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{
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int family, model, stepping;
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#ifdef TARGET_X86_64
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env->cpuid_vendor1 = 0x68747541; /* "Auth" */ |
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env->cpuid_vendor2 = 0x69746e65; /* "enti" */ |
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env->cpuid_vendor3 = 0x444d4163; /* "cAMD" */ |
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family = 6;
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model = 2;
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stepping = 3;
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#else
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env->cpuid_vendor1 = 0x756e6547; /* "Genu" */ |
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env->cpuid_vendor2 = 0x49656e69; /* "ineI" */ |
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env->cpuid_vendor3 = 0x6c65746e; /* "ntel" */ |
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#if 0
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/* pentium 75-200 */
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family = 5;
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model = 2;
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stepping = 11;
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#else
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/* pentium pro */
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family = 6;
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model = 3;
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stepping = 3;
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#endif
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#endif
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env->cpuid_version = (family << 8) | (model << 4) | stepping; |
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env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE | |
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CPUID_TSC | CPUID_MSR | CPUID_MCE | |
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CPUID_CX8 | CPUID_PGE | CPUID_CMOV); |
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env->cpuid_ext_features = 0;
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env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | CPUID_PAE | CPUID_SEP; |
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#ifdef TARGET_X86_64
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/* currently not enabled for std i386 because not fully tested */
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env->cpuid_features |= CPUID_APIC; |
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#endif
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} |
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cpu_single_env = env; |
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cpu_reset(env); |
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#ifdef USE_KQEMU
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kqemu_init(env); |
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#endif
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return env;
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} |
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/* NOTE: must be called outside the CPU execute loop */
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void cpu_reset(CPUX86State *env)
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{
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int i;
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memset(env, 0, offsetof(CPUX86State, breakpoints));
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tlb_flush(env, 1);
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/* init to reset state */
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#ifdef CONFIG_SOFTMMU
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env->hflags |= HF_SOFTMMU_MASK; |
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#endif
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cpu_x86_update_cr0(env, 0x60000010);
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env->a20_mask = 0xffffffff;
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env->idt.limit = 0xffff;
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env->gdt.limit = 0xffff;
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env->ldt.limit = 0xffff;
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env->ldt.flags = DESC_P_MASK; |
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env->tr.limit = 0xffff;
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env->tr.flags = DESC_P_MASK; |
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cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0); |
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env->eip = 0xfff0;
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env->regs[R_EDX] = 0x600; /* indicate P6 processor */ |
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env->eflags = 0x2;
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/* FPU init */
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for(i = 0;i < 8; i++) |
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env->fptags[i] = 1;
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env->fpuc = 0x37f;
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env->mxcsr = 0x1f80;
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} |
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void cpu_x86_close(CPUX86State *env)
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{
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free(env); |
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} |
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[] = { |
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"MULQ",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADDQ",
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"ADCB",
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"ADCW",
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"ADCL",
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"ADCQ",
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"SUBB",
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"SUBW",
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"SUBL",
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"SUBQ",
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"SBBB",
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"SBBW",
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"SBBL",
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"SBBQ",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"LOGICQ",
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"INCB",
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"INCW",
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"INCL",
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"INCQ",
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"DECB",
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"DECW",
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"DECL",
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"DECQ",
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"SHLB",
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"SHLW",
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"SHLL",
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"SHLQ",
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"SARB",
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"SARW",
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"SARL",
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"SARQ",
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}; |
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void cpu_dump_state(CPUState *env, FILE *f,
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int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
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int flags)
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{
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int eflags, i;
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char cc_op_name[32]; |
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; |
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eflags = env->eflags; |
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, |
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"RAX=%016llx RBX=%016llx RCX=%016llx RDX=%016llx\n"
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"RSI=%016llx RDI=%016llx RBP=%016llx RSP=%016llx\n"
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"R8 =%016llx R9 =%016llx R10=%016llx R11=%016llx\n"
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"R12=%016llx R13=%016llx R14=%016llx R15=%016llx\n"
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"RIP=%016llx RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d\n",
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env->regs[R_EAX], |
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env->regs[R_EBX], |
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env->regs[R_ECX], |
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env->regs[R_EDX], |
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env->regs[R_ESI], |
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env->regs[R_EDI], |
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env->regs[R_EBP], |
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env->regs[R_ESP], |
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env->regs[8],
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env->regs[9],
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env->regs[10],
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env->regs[11],
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env->regs[12],
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env->regs[13],
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env->regs[14],
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env->regs[15],
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env->eip, eflags, |
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eflags & DF_MASK ? 'D' : '-', |
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eflags & CC_O ? 'O' : '-', |
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eflags & CC_S ? 'S' : '-', |
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eflags & CC_Z ? 'Z' : '-', |
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eflags & CC_A ? 'A' : '-', |
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eflags & CC_P ? 'P' : '-', |
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eflags & CC_C ? 'C' : '-', |
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env->hflags & HF_CPL_MASK, |
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1); |
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} else
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#endif
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{
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cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d\n",
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(uint32_t)env->regs[R_EAX], |
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(uint32_t)env->regs[R_EBX], |
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(uint32_t)env->regs[R_ECX], |
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(uint32_t)env->regs[R_EDX], |
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(uint32_t)env->regs[R_ESI], |
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(uint32_t)env->regs[R_EDI], |
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(uint32_t)env->regs[R_EBP], |
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(uint32_t)env->regs[R_ESP], |
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(uint32_t)env->eip, eflags, |
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eflags & DF_MASK ? 'D' : '-', |
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eflags & CC_O ? 'O' : '-', |
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eflags & CC_S ? 'S' : '-', |
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eflags & CC_Z ? 'Z' : '-', |
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eflags & CC_A ? 'A' : '-', |
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eflags & CC_P ? 'P' : '-', |
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eflags & CC_C ? 'C' : '-', |
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env->hflags & HF_CPL_MASK, |
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1); |
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} |
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|
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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for(i = 0; i < 6; i++) { |
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SegmentCache *sc = &env->segs[i]; |
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cpu_fprintf(f, "%s =%04x %016llx %08x %08x\n",
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seg_name[i], |
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sc->selector, |
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sc->base, |
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sc->limit, |
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sc->flags); |
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} |
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cpu_fprintf(f, "LDT=%04x %016llx %08x %08x\n",
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env->ldt.selector, |
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env->ldt.base, |
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env->ldt.limit, |
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env->ldt.flags); |
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cpu_fprintf(f, "TR =%04x %016llx %08x %08x\n",
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env->tr.selector, |
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env->tr.base, |
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env->tr.limit, |
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env->tr.flags); |
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cpu_fprintf(f, "GDT= %016llx %08x\n",
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env->gdt.base, env->gdt.limit); |
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cpu_fprintf(f, "IDT= %016llx %08x\n",
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env->idt.base, env->idt.limit); |
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cpu_fprintf(f, "CR0=%08x CR2=%016llx CR3=%016llx CR4=%08x\n",
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(uint32_t)env->cr[0],
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env->cr[2],
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env->cr[3],
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(uint32_t)env->cr[4]);
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} else
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#endif
|
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{
|
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for(i = 0; i < 6; i++) { |
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SegmentCache *sc = &env->segs[i]; |
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cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
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seg_name[i], |
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sc->selector, |
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(uint32_t)sc->base, |
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sc->limit, |
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sc->flags); |
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} |
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cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
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env->ldt.selector, |
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(uint32_t)env->ldt.base, |
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env->ldt.limit, |
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env->ldt.flags); |
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cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
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env->tr.selector, |
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(uint32_t)env->tr.base, |
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env->tr.limit, |
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env->tr.flags); |
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cpu_fprintf(f, "GDT= %08x %08x\n",
|
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(uint32_t)env->gdt.base, env->gdt.limit); |
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cpu_fprintf(f, "IDT= %08x %08x\n",
|
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(uint32_t)env->idt.base, env->idt.limit); |
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cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
|
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(uint32_t)env->cr[0],
|
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(uint32_t)env->cr[2],
|
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(uint32_t)env->cr[3],
|
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(uint32_t)env->cr[4]);
|
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} |
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if (flags & X86_DUMP_CCOP) {
|
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if ((unsigned)env->cc_op < CC_OP_NB) |
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snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]); |
| 368 |
else
|
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); |
| 370 |
#ifdef TARGET_X86_64
|
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if (env->hflags & HF_CS64_MASK) {
|
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cpu_fprintf(f, "CCS=%016llx CCD=%016llx CCO=%-8s\n",
|
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env->cc_src, env->cc_dst, |
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cc_op_name); |
| 375 |
} else
|
| 376 |
#endif
|
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{
|
| 378 |
cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
|
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(uint32_t)env->cc_src, (uint32_t)env->cc_dst, |
| 380 |
cc_op_name); |
| 381 |
} |
| 382 |
} |
| 383 |
if (flags & X86_DUMP_FPU) {
|
| 384 |
cpu_fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
|
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(double)env->fpregs[0].d, |
| 386 |
(double)env->fpregs[1].d, |
| 387 |
(double)env->fpregs[2].d, |
| 388 |
(double)env->fpregs[3].d); |
| 389 |
cpu_fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
|
| 390 |
(double)env->fpregs[4].d, |
| 391 |
(double)env->fpregs[5].d, |
| 392 |
(double)env->fpregs[7].d, |
| 393 |
(double)env->fpregs[8].d); |
| 394 |
} |
| 395 |
} |
| 396 |
|
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/***********************************************************/
|
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/* x86 mmu */
|
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/* XXX: add PGE support */
|
| 400 |
|
| 401 |
void cpu_x86_set_a20(CPUX86State *env, int a20_state) |
| 402 |
{
|
| 403 |
a20_state = (a20_state != 0);
|
| 404 |
if (a20_state != ((env->a20_mask >> 20) & 1)) { |
| 405 |
#if defined(DEBUG_MMU)
|
| 406 |
printf("A20 update: a20=%d\n", a20_state);
|
| 407 |
#endif
|
| 408 |
/* if the cpu is currently executing code, we must unlink it and
|
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all the potentially executing TB */
|
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cpu_interrupt(env, CPU_INTERRUPT_EXITTB); |
| 411 |
|
| 412 |
/* when a20 is changed, all the MMU mappings are invalid, so
|
| 413 |
we must flush everything */
|
| 414 |
tlb_flush(env, 1);
|
| 415 |
env->a20_mask = 0xffefffff | (a20_state << 20); |
| 416 |
} |
| 417 |
} |
| 418 |
|
| 419 |
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
|
| 420 |
{
|
| 421 |
int pe_state;
|
| 422 |
|
| 423 |
#if defined(DEBUG_MMU)
|
| 424 |
printf("CR0 update: CR0=0x%08x\n", new_cr0);
|
| 425 |
#endif
|
| 426 |
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
|
| 427 |
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
|
| 428 |
tlb_flush(env, 1);
|
| 429 |
} |
| 430 |
|
| 431 |
#ifdef TARGET_X86_64
|
| 432 |
if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) && |
| 433 |
(env->efer & MSR_EFER_LME)) {
|
| 434 |
/* enter in long mode */
|
| 435 |
/* XXX: generate an exception */
|
| 436 |
if (!(env->cr[4] & CR4_PAE_MASK)) |
| 437 |
return;
|
| 438 |
env->efer |= MSR_EFER_LMA; |
| 439 |
env->hflags |= HF_LMA_MASK; |
| 440 |
} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) && |
| 441 |
(env->efer & MSR_EFER_LMA)) {
|
| 442 |
/* exit long mode */
|
| 443 |
env->efer &= ~MSR_EFER_LMA; |
| 444 |
env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK); |
| 445 |
env->eip &= 0xffffffff;
|
| 446 |
} |
| 447 |
#endif
|
| 448 |
env->cr[0] = new_cr0 | CR0_ET_MASK;
|
| 449 |
|
| 450 |
/* update PE flag in hidden flags */
|
| 451 |
pe_state = (env->cr[0] & CR0_PE_MASK);
|
| 452 |
env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT); |
| 453 |
/* ensure that ADDSEG is always set in real mode */
|
| 454 |
env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
|
| 455 |
/* update FPU flags */
|
| 456 |
env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | |
| 457 |
((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
|
| 458 |
} |
| 459 |
|
| 460 |
/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
|
| 461 |
the PDPT */
|
| 462 |
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
|
| 463 |
{
|
| 464 |
env->cr[3] = new_cr3;
|
| 465 |
if (env->cr[0] & CR0_PG_MASK) { |
| 466 |
#if defined(DEBUG_MMU)
|
| 467 |
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); |
| 468 |
#endif
|
| 469 |
tlb_flush(env, 0);
|
| 470 |
} |
| 471 |
} |
| 472 |
|
| 473 |
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
|
| 474 |
{
|
| 475 |
#if defined(DEBUG_MMU)
|
| 476 |
printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]); |
| 477 |
#endif
|
| 478 |
if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
|
| 479 |
(env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
|
| 480 |
tlb_flush(env, 1);
|
| 481 |
} |
| 482 |
/* SSE handling */
|
| 483 |
if (!(env->cpuid_features & CPUID_SSE))
|
| 484 |
new_cr4 &= ~CR4_OSFXSR_MASK; |
| 485 |
if (new_cr4 & CR4_OSFXSR_MASK)
|
| 486 |
env->hflags |= HF_OSFXSR_MASK; |
| 487 |
else
|
| 488 |
env->hflags &= ~HF_OSFXSR_MASK; |
| 489 |
|
| 490 |
env->cr[4] = new_cr4;
|
| 491 |
} |
| 492 |
|
| 493 |
/* XXX: also flush 4MB pages */
|
| 494 |
void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
|
| 495 |
{
|
| 496 |
tlb_flush_page(env, addr); |
| 497 |
} |
| 498 |
|
| 499 |
#if defined(CONFIG_USER_ONLY)
|
| 500 |
|
| 501 |
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
| 502 |
int is_write, int is_user, int is_softmmu) |
| 503 |
{
|
| 504 |
/* user mode only emulation */
|
| 505 |
is_write &= 1;
|
| 506 |
env->cr[2] = addr;
|
| 507 |
env->error_code = (is_write << PG_ERROR_W_BIT); |
| 508 |
env->error_code |= PG_ERROR_U_MASK; |
| 509 |
return 1; |
| 510 |
} |
| 511 |
|
| 512 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 513 |
{
|
| 514 |
return addr;
|
| 515 |
} |
| 516 |
|
| 517 |
#else
|
| 518 |
|
| 519 |
/* return value:
|
| 520 |
-1 = cannot handle fault
|
| 521 |
0 = nothing more to do
|
| 522 |
1 = generate PF fault
|
| 523 |
2 = soft MMU activation required for this block
|
| 524 |
*/
|
| 525 |
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
| 526 |
int is_write, int is_user, int is_softmmu) |
| 527 |
{
|
| 528 |
uint32_t pdpe_addr, pde_addr, pte_addr; |
| 529 |
uint32_t pde, pte, ptep, pdpe; |
| 530 |
int error_code, is_dirty, prot, page_size, ret;
|
| 531 |
unsigned long paddr, page_offset; |
| 532 |
target_ulong vaddr, virt_addr; |
| 533 |
|
| 534 |
#if defined(DEBUG_MMU)
|
| 535 |
printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n", |
| 536 |
addr, is_write, is_user, env->eip); |
| 537 |
#endif
|
| 538 |
is_write &= 1;
|
| 539 |
|
| 540 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
| 541 |
pte = addr; |
| 542 |
virt_addr = addr & TARGET_PAGE_MASK; |
| 543 |
prot = PAGE_READ | PAGE_WRITE; |
| 544 |
page_size = 4096;
|
| 545 |
goto do_mapping;
|
| 546 |
} |
| 547 |
|
| 548 |
if (env->cr[4] & CR4_PAE_MASK) { |
| 549 |
/* XXX: we only use 32 bit physical addresses */
|
| 550 |
#ifdef TARGET_X86_64
|
| 551 |
if (env->hflags & HF_LMA_MASK) {
|
| 552 |
uint32_t pml4e_addr, pml4e; |
| 553 |
int32_t sext; |
| 554 |
|
| 555 |
/* XXX: handle user + rw rights */
|
| 556 |
/* XXX: handle NX flag */
|
| 557 |
/* test virtual address sign extension */
|
| 558 |
sext = (int64_t)addr >> 47;
|
| 559 |
if (sext != 0 && sext != -1) { |
| 560 |
error_code = 0;
|
| 561 |
goto do_fault;
|
| 562 |
} |
| 563 |
|
| 564 |
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & |
| 565 |
env->a20_mask; |
| 566 |
pml4e = ldl_phys(pml4e_addr); |
| 567 |
if (!(pml4e & PG_PRESENT_MASK)) {
|
| 568 |
error_code = 0;
|
| 569 |
goto do_fault;
|
| 570 |
} |
| 571 |
if (!(pml4e & PG_ACCESSED_MASK)) {
|
| 572 |
pml4e |= PG_ACCESSED_MASK; |
| 573 |
stl_phys_notdirty(pml4e_addr, pml4e); |
| 574 |
} |
| 575 |
|
| 576 |
pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) & |
| 577 |
env->a20_mask; |
| 578 |
pdpe = ldl_phys(pdpe_addr); |
| 579 |
if (!(pdpe & PG_PRESENT_MASK)) {
|
| 580 |
error_code = 0;
|
| 581 |
goto do_fault;
|
| 582 |
} |
| 583 |
if (!(pdpe & PG_ACCESSED_MASK)) {
|
| 584 |
pdpe |= PG_ACCESSED_MASK; |
| 585 |
stl_phys_notdirty(pdpe_addr, pdpe); |
| 586 |
} |
| 587 |
} else
|
| 588 |
#endif
|
| 589 |
{
|
| 590 |
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 30) << 3)) & |
| 591 |
env->a20_mask; |
| 592 |
pdpe = ldl_phys(pdpe_addr); |
| 593 |
if (!(pdpe & PG_PRESENT_MASK)) {
|
| 594 |
error_code = 0;
|
| 595 |
goto do_fault;
|
| 596 |
} |
| 597 |
} |
| 598 |
|
| 599 |
pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) & |
| 600 |
env->a20_mask; |
| 601 |
pde = ldl_phys(pde_addr); |
| 602 |
if (!(pde & PG_PRESENT_MASK)) {
|
| 603 |
error_code = 0;
|
| 604 |
goto do_fault;
|
| 605 |
} |
| 606 |
if (pde & PG_PSE_MASK) {
|
| 607 |
/* 2 MB page */
|
| 608 |
page_size = 2048 * 1024; |
| 609 |
goto handle_big_page;
|
| 610 |
} else {
|
| 611 |
/* 4 KB page */
|
| 612 |
if (!(pde & PG_ACCESSED_MASK)) {
|
| 613 |
pde |= PG_ACCESSED_MASK; |
| 614 |
stl_phys_notdirty(pde_addr, pde); |
| 615 |
} |
| 616 |
pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) & |
| 617 |
env->a20_mask; |
| 618 |
goto handle_4k_page;
|
| 619 |
} |
| 620 |
} else {
|
| 621 |
/* page directory entry */
|
| 622 |
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & |
| 623 |
env->a20_mask; |
| 624 |
pde = ldl_phys(pde_addr); |
| 625 |
if (!(pde & PG_PRESENT_MASK)) {
|
| 626 |
error_code = 0;
|
| 627 |
goto do_fault;
|
| 628 |
} |
| 629 |
/* if PSE bit is set, then we use a 4MB page */
|
| 630 |
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { |
| 631 |
page_size = 4096 * 1024; |
| 632 |
handle_big_page:
|
| 633 |
if (is_user) {
|
| 634 |
if (!(pde & PG_USER_MASK))
|
| 635 |
goto do_fault_protect;
|
| 636 |
if (is_write && !(pde & PG_RW_MASK))
|
| 637 |
goto do_fault_protect;
|
| 638 |
} else {
|
| 639 |
if ((env->cr[0] & CR0_WP_MASK) && |
| 640 |
is_write && !(pde & PG_RW_MASK)) |
| 641 |
goto do_fault_protect;
|
| 642 |
} |
| 643 |
is_dirty = is_write && !(pde & PG_DIRTY_MASK); |
| 644 |
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
|
| 645 |
pde |= PG_ACCESSED_MASK; |
| 646 |
if (is_dirty)
|
| 647 |
pde |= PG_DIRTY_MASK; |
| 648 |
stl_phys_notdirty(pde_addr, pde); |
| 649 |
} |
| 650 |
|
| 651 |
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */ |
| 652 |
ptep = pte; |
| 653 |
virt_addr = addr & ~(page_size - 1);
|
| 654 |
} else {
|
| 655 |
if (!(pde & PG_ACCESSED_MASK)) {
|
| 656 |
pde |= PG_ACCESSED_MASK; |
| 657 |
stl_phys_notdirty(pde_addr, pde); |
| 658 |
} |
| 659 |
|
| 660 |
/* page directory entry */
|
| 661 |
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & |
| 662 |
env->a20_mask; |
| 663 |
handle_4k_page:
|
| 664 |
pte = ldl_phys(pte_addr); |
| 665 |
if (!(pte & PG_PRESENT_MASK)) {
|
| 666 |
error_code = 0;
|
| 667 |
goto do_fault;
|
| 668 |
} |
| 669 |
/* combine pde and pte user and rw protections */
|
| 670 |
ptep = pte & pde; |
| 671 |
if (is_user) {
|
| 672 |
if (!(ptep & PG_USER_MASK))
|
| 673 |
goto do_fault_protect;
|
| 674 |
if (is_write && !(ptep & PG_RW_MASK))
|
| 675 |
goto do_fault_protect;
|
| 676 |
} else {
|
| 677 |
if ((env->cr[0] & CR0_WP_MASK) && |
| 678 |
is_write && !(ptep & PG_RW_MASK)) |
| 679 |
goto do_fault_protect;
|
| 680 |
} |
| 681 |
is_dirty = is_write && !(pte & PG_DIRTY_MASK); |
| 682 |
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
| 683 |
pte |= PG_ACCESSED_MASK; |
| 684 |
if (is_dirty)
|
| 685 |
pte |= PG_DIRTY_MASK; |
| 686 |
stl_phys_notdirty(pte_addr, pte); |
| 687 |
} |
| 688 |
page_size = 4096;
|
| 689 |
virt_addr = addr & ~0xfff;
|
| 690 |
} |
| 691 |
|
| 692 |
/* the page can be put in the TLB */
|
| 693 |
prot = PAGE_READ; |
| 694 |
if (pte & PG_DIRTY_MASK) {
|
| 695 |
/* only set write access if already dirty... otherwise wait
|
| 696 |
for dirty access */
|
| 697 |
if (is_user) {
|
| 698 |
if (ptep & PG_RW_MASK)
|
| 699 |
prot |= PAGE_WRITE; |
| 700 |
} else {
|
| 701 |
if (!(env->cr[0] & CR0_WP_MASK) || |
| 702 |
(ptep & PG_RW_MASK)) |
| 703 |
prot |= PAGE_WRITE; |
| 704 |
} |
| 705 |
} |
| 706 |
} |
| 707 |
do_mapping:
|
| 708 |
pte = pte & env->a20_mask; |
| 709 |
|
| 710 |
/* Even if 4MB pages, we map only one 4KB page in the cache to
|
| 711 |
avoid filling it too fast */
|
| 712 |
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
| 713 |
paddr = (pte & TARGET_PAGE_MASK) + page_offset; |
| 714 |
vaddr = virt_addr + page_offset; |
| 715 |
|
| 716 |
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
| 717 |
return ret;
|
| 718 |
do_fault_protect:
|
| 719 |
error_code = PG_ERROR_P_MASK; |
| 720 |
do_fault:
|
| 721 |
env->cr[2] = addr;
|
| 722 |
env->error_code = (is_write << PG_ERROR_W_BIT) | error_code; |
| 723 |
if (is_user)
|
| 724 |
env->error_code |= PG_ERROR_U_MASK; |
| 725 |
return 1; |
| 726 |
} |
| 727 |
|
| 728 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 729 |
{
|
| 730 |
uint32_t pde_addr, pte_addr; |
| 731 |
uint32_t pde, pte, paddr, page_offset, page_size; |
| 732 |
|
| 733 |
if (env->cr[4] & CR4_PAE_MASK) { |
| 734 |
uint32_t pdpe_addr, pde_addr, pte_addr; |
| 735 |
uint32_t pdpe; |
| 736 |
|
| 737 |
/* XXX: we only use 32 bit physical addresses */
|
| 738 |
#ifdef TARGET_X86_64
|
| 739 |
if (env->hflags & HF_LMA_MASK) {
|
| 740 |
uint32_t pml4e_addr, pml4e; |
| 741 |
int32_t sext; |
| 742 |
|
| 743 |
/* test virtual address sign extension */
|
| 744 |
sext = (int64_t)addr >> 47;
|
| 745 |
if (sext != 0 && sext != -1) |
| 746 |
return -1; |
| 747 |
|
| 748 |
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & |
| 749 |
env->a20_mask; |
| 750 |
pml4e = ldl_phys(pml4e_addr); |
| 751 |
if (!(pml4e & PG_PRESENT_MASK))
|
| 752 |
return -1; |
| 753 |
|
| 754 |
pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) & |
| 755 |
env->a20_mask; |
| 756 |
pdpe = ldl_phys(pdpe_addr); |
| 757 |
if (!(pdpe & PG_PRESENT_MASK))
|
| 758 |
return -1; |
| 759 |
} else
|
| 760 |
#endif
|
| 761 |
{
|
| 762 |
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 30) << 3)) & |
| 763 |
env->a20_mask; |
| 764 |
pdpe = ldl_phys(pdpe_addr); |
| 765 |
if (!(pdpe & PG_PRESENT_MASK))
|
| 766 |
return -1; |
| 767 |
} |
| 768 |
|
| 769 |
pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) & |
| 770 |
env->a20_mask; |
| 771 |
pde = ldl_phys(pde_addr); |
| 772 |
if (!(pde & PG_PRESENT_MASK)) {
|
| 773 |
return -1; |
| 774 |
} |
| 775 |
if (pde & PG_PSE_MASK) {
|
| 776 |
/* 2 MB page */
|
| 777 |
page_size = 2048 * 1024; |
| 778 |
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */ |
| 779 |
} else {
|
| 780 |
/* 4 KB page */
|
| 781 |
pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) & |
| 782 |
env->a20_mask; |
| 783 |
page_size = 4096;
|
| 784 |
pte = ldl_phys(pte_addr); |
| 785 |
} |
| 786 |
} else {
|
| 787 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
| 788 |
pte = addr; |
| 789 |
page_size = 4096;
|
| 790 |
} else {
|
| 791 |
/* page directory entry */
|
| 792 |
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask; |
| 793 |
pde = ldl_phys(pde_addr); |
| 794 |
if (!(pde & PG_PRESENT_MASK))
|
| 795 |
return -1; |
| 796 |
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { |
| 797 |
pte = pde & ~0x003ff000; /* align to 4MB */ |
| 798 |
page_size = 4096 * 1024; |
| 799 |
} else {
|
| 800 |
/* page directory entry */
|
| 801 |
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask; |
| 802 |
pte = ldl_phys(pte_addr); |
| 803 |
if (!(pte & PG_PRESENT_MASK))
|
| 804 |
return -1; |
| 805 |
page_size = 4096;
|
| 806 |
} |
| 807 |
} |
| 808 |
pte = pte & env->a20_mask; |
| 809 |
} |
| 810 |
|
| 811 |
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
| 812 |
paddr = (pte & TARGET_PAGE_MASK) + page_offset; |
| 813 |
return paddr;
|
| 814 |
} |
| 815 |
#endif /* !CONFIG_USER_ONLY */ |
| 816 |
|
| 817 |
#if defined(USE_CODE_COPY)
|
| 818 |
struct fpstate {
|
| 819 |
uint16_t fpuc; |
| 820 |
uint16_t dummy1; |
| 821 |
uint16_t fpus; |
| 822 |
uint16_t dummy2; |
| 823 |
uint16_t fptag; |
| 824 |
uint16_t dummy3; |
| 825 |
|
| 826 |
uint32_t fpip; |
| 827 |
uint32_t fpcs; |
| 828 |
uint32_t fpoo; |
| 829 |
uint32_t fpos; |
| 830 |
uint8_t fpregs1[8 * 10]; |
| 831 |
}; |
| 832 |
|
| 833 |
void restore_native_fp_state(CPUState *env)
|
| 834 |
{
|
| 835 |
int fptag, i, j;
|
| 836 |
struct fpstate fp1, *fp = &fp1;
|
| 837 |
|
| 838 |
fp->fpuc = env->fpuc; |
| 839 |
fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
| 840 |
fptag = 0;
|
| 841 |
for (i=7; i>=0; i--) { |
| 842 |
fptag <<= 2;
|
| 843 |
if (env->fptags[i]) {
|
| 844 |
fptag |= 3;
|
| 845 |
} else {
|
| 846 |
/* the FPU automatically computes it */
|
| 847 |
} |
| 848 |
} |
| 849 |
fp->fptag = fptag; |
| 850 |
j = env->fpstt; |
| 851 |
for(i = 0;i < 8; i++) { |
| 852 |
memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10); |
| 853 |
j = (j + 1) & 7; |
| 854 |
} |
| 855 |
asm volatile ("frstor %0" : "=m" (*fp)); |
| 856 |
env->native_fp_regs = 1;
|
| 857 |
} |
| 858 |
|
| 859 |
void save_native_fp_state(CPUState *env)
|
| 860 |
{
|
| 861 |
int fptag, i, j;
|
| 862 |
uint16_t fpuc; |
| 863 |
struct fpstate fp1, *fp = &fp1;
|
| 864 |
|
| 865 |
asm volatile ("fsave %0" : : "m" (*fp)); |
| 866 |
env->fpuc = fp->fpuc; |
| 867 |
env->fpstt = (fp->fpus >> 11) & 7; |
| 868 |
env->fpus = fp->fpus & ~0x3800;
|
| 869 |
fptag = fp->fptag; |
| 870 |
for(i = 0;i < 8; i++) { |
| 871 |
env->fptags[i] = ((fptag & 3) == 3); |
| 872 |
fptag >>= 2;
|
| 873 |
} |
| 874 |
j = env->fpstt; |
| 875 |
for(i = 0;i < 8; i++) { |
| 876 |
memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10); |
| 877 |
j = (j + 1) & 7; |
| 878 |
} |
| 879 |
/* we must restore the default rounding state */
|
| 880 |
/* XXX: we do not restore the exception state */
|
| 881 |
fpuc = 0x037f | (env->fpuc & (3 << 10)); |
| 882 |
asm volatile("fldcw %0" : : "m" (fpuc)); |
| 883 |
env->native_fp_regs = 0;
|
| 884 |
} |
| 885 |
#endif
|