Revision 558fa836
| b/target-i386/cpu.h | ||
|---|---|---|
| 298 | 298 |
#define CPUID_PBE (1 << 31) |
| 299 | 299 |
|
| 300 | 300 |
#define CPUID_EXT_SSE3 (1 << 0) |
| 301 |
#define CPUID_EXT_DTES64 (1 << 2) |
|
| 301 | 302 |
#define CPUID_EXT_MONITOR (1 << 3) |
| 302 | 303 |
#define CPUID_EXT_DSCPL (1 << 4) |
| 303 | 304 |
#define CPUID_EXT_VMX (1 << 5) |
| ... | ... | |
| 308 | 309 |
#define CPUID_EXT_CID (1 << 10) |
| 309 | 310 |
#define CPUID_EXT_CX16 (1 << 13) |
| 310 | 311 |
#define CPUID_EXT_XTPR (1 << 14) |
| 311 |
#define CPUID_EXT_DCA (1 << 17) |
|
| 312 |
#define CPUID_EXT_POPCNT (1 << 22) |
|
| 312 |
#define CPUID_EXT_PDCM (1 << 15) |
|
| 313 |
#define CPUID_EXT_DCA (1 << 18) |
|
| 314 |
#define CPUID_EXT_SSE41 (1 << 19) |
|
| 315 |
#define CPUID_EXT_SSE42 (1 << 20) |
|
| 316 |
#define CPUID_EXT_X2APIC (1 << 21) |
|
| 317 |
#define CPUID_EXT_MOVBE (1 << 22) |
|
| 318 |
#define CPUID_EXT_POPCNT (1 << 23) |
|
| 319 |
#define CPUID_EXT_XSAVE (1 << 26) |
|
| 320 |
#define CPUID_EXT_OSXSAVE (1 << 27) |
|
| 313 | 321 |
|
| 314 | 322 |
#define CPUID_EXT2_SYSCALL (1 << 11) |
| 315 | 323 |
#define CPUID_EXT2_MP (1 << 19) |
| b/target-i386/helper.c | ||
|---|---|---|
| 167 | 167 |
}, |
| 168 | 168 |
{
|
| 169 | 169 |
.name = "core2duo", |
| 170 |
/* original is on level 10 */ |
|
| 171 |
.level = 5, |
|
| 170 |
.level = 10, |
|
| 172 | 171 |
.family = 6, |
| 173 | 172 |
.model = 15, |
| 174 | 173 |
.stepping = 11, |
| 175 |
/* the original CPU does have many more features that are |
|
| 176 |
* not implemented yet */ |
|
| 174 |
/* The original CPU also implements these features: |
|
| 175 |
CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT, |
|
| 176 |
CPUID_TM, CPUID_PBE */ |
|
| 177 | 177 |
.features = PPRO_FEATURES | |
| 178 | 178 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
| 179 | 179 |
CPUID_PSE36, |
| 180 |
/* The original CPU also implements these ext features: |
|
| 181 |
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST, |
|
| 182 |
CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ |
|
| 180 | 183 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3, |
| 181 |
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
|
|
| 182 |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
| 184 |
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
| 185 |
/* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
|
|
| 183 | 186 |
.xlevel = 0x8000000A, |
| 184 | 187 |
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", |
| 185 | 188 |
}, |
| ... | ... | |
| 240 | 243 |
.family = 6, |
| 241 | 244 |
.model = 2, |
| 242 | 245 |
.stepping = 3, |
| 243 |
.features = PPRO_FEATURES | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
|
|
| 246 |
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, |
|
| 244 | 247 |
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
| 245 | 248 |
.xlevel = 0x80000008, |
| 246 | 249 |
/* XXX: put another string ? */ |
| b/target-i386/op_helper.c | ||
|---|---|---|
| 1956 | 1956 |
ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
| 1957 | 1957 |
EDX = 0; |
| 1958 | 1958 |
break; |
| 1959 |
case 6: |
|
| 1960 |
/* Thermal and Power Leaf */ |
|
| 1961 |
EAX = 0; |
|
| 1962 |
EBX = 0; |
|
| 1963 |
ECX = 0; |
|
| 1964 |
EDX = 0; |
|
| 1965 |
break; |
|
| 1966 |
case 9: |
|
| 1967 |
/* Direct Cache Access Information Leaf */ |
|
| 1968 |
EAX = 0; /* Bits 0-31 in DCA_CAP MSR */ |
|
| 1969 |
EBX = 0; |
|
| 1970 |
ECX = 0; |
|
| 1971 |
EDX = 0; |
|
| 1972 |
break; |
|
| 1973 |
case 0xA: |
|
| 1974 |
/* Architectural Performance Monitoring Leaf */ |
|
| 1975 |
EAX = 0; |
|
| 1976 |
EBX = 0; |
|
| 1977 |
ECX = 0; |
|
| 1978 |
EDX = 0; |
|
| 1979 |
break; |
|
| 1959 | 1980 |
case 0x80000000: |
| 1960 | 1981 |
EAX = env->cpuid_xlevel; |
| 1961 | 1982 |
EBX = env->cpuid_vendor1; |
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