root / hw / eccmemctl.c @ 562183de
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1 | 7eb0c8e8 | blueswir1 | /*
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2 | 7eb0c8e8 | blueswir1 | * QEMU Sparc Sun4m ECC memory controller emulation
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3 | 7eb0c8e8 | blueswir1 | *
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4 | 7eb0c8e8 | blueswir1 | * Copyright (c) 2007 Robert Reif
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5 | 7eb0c8e8 | blueswir1 | *
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6 | 7eb0c8e8 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 7eb0c8e8 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 7eb0c8e8 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 7eb0c8e8 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 7eb0c8e8 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 7eb0c8e8 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 7eb0c8e8 | blueswir1 | *
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13 | 7eb0c8e8 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 7eb0c8e8 | blueswir1 | * all copies or substantial portions of the Software.
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15 | 7eb0c8e8 | blueswir1 | *
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16 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 7eb0c8e8 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 7eb0c8e8 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 7eb0c8e8 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 7eb0c8e8 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 7eb0c8e8 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE.
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23 | 7eb0c8e8 | blueswir1 | */
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24 | 7eb0c8e8 | blueswir1 | #include "hw.h" |
25 | 7eb0c8e8 | blueswir1 | #include "sun4m.h" |
26 | 7eb0c8e8 | blueswir1 | #include "sysemu.h" |
27 | 7eb0c8e8 | blueswir1 | |
28 | 7eb0c8e8 | blueswir1 | //#define DEBUG_ECC
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29 | 7eb0c8e8 | blueswir1 | |
30 | 7eb0c8e8 | blueswir1 | #ifdef DEBUG_ECC
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31 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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32 | 001faf32 | Blue Swirl | do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0) |
33 | 7eb0c8e8 | blueswir1 | #else
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34 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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35 | 7eb0c8e8 | blueswir1 | #endif
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36 | 7eb0c8e8 | blueswir1 | |
37 | 7eb0c8e8 | blueswir1 | /* There are 3 versions of this chip used in SMP sun4m systems:
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38 | 7eb0c8e8 | blueswir1 | * MCC (version 0, implementation 0) SS-600MP
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39 | 7eb0c8e8 | blueswir1 | * EMC (version 0, implementation 1) SS-10
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40 | 7eb0c8e8 | blueswir1 | * SMC (version 0, implementation 2) SS-10SX and SS-20
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41 | 7eb0c8e8 | blueswir1 | */
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42 | 7eb0c8e8 | blueswir1 | |
43 | 0bb3602c | blueswir1 | #define ECC_MCC 0x00000000 |
44 | 0bb3602c | blueswir1 | #define ECC_EMC 0x10000000 |
45 | 0bb3602c | blueswir1 | #define ECC_SMC 0x20000000 |
46 | 0bb3602c | blueswir1 | |
47 | 8f2ad0a3 | blueswir1 | /* Register indexes */
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48 | 8f2ad0a3 | blueswir1 | #define ECC_MER 0 /* Memory Enable Register */ |
49 | 8f2ad0a3 | blueswir1 | #define ECC_MDR 1 /* Memory Delay Register */ |
50 | 8f2ad0a3 | blueswir1 | #define ECC_MFSR 2 /* Memory Fault Status Register */ |
51 | 8f2ad0a3 | blueswir1 | #define ECC_VCR 3 /* Video Configuration Register */ |
52 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
53 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
54 | 8f2ad0a3 | blueswir1 | #define ECC_DR 6 /* Diagnostic Register */ |
55 | 8f2ad0a3 | blueswir1 | #define ECC_ECR0 7 /* Event Count Register 0 */ |
56 | 8f2ad0a3 | blueswir1 | #define ECC_ECR1 8 /* Event Count Register 1 */ |
57 | 7eb0c8e8 | blueswir1 | |
58 | 7eb0c8e8 | blueswir1 | /* ECC fault control register */
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59 | dd53ded3 | blueswir1 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
60 | 77f193da | blueswir1 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
61 | 77f193da | blueswir1 | correctable errors */
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62 | dd53ded3 | blueswir1 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
63 | dd53ded3 | blueswir1 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
64 | dd53ded3 | blueswir1 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
65 | dd53ded3 | blueswir1 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
66 | dd53ded3 | blueswir1 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
67 | dd53ded3 | blueswir1 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
68 | dd53ded3 | blueswir1 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
69 | dd53ded3 | blueswir1 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
70 | 0bb3602c | blueswir1 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
71 | dd53ded3 | blueswir1 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
72 | 0bb3602c | blueswir1 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
73 | 77f193da | blueswir1 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
74 | dd53ded3 | blueswir1 | #define ECC_MER_VER 0x0f000000 /* Version */ |
75 | dd53ded3 | blueswir1 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
76 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
77 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
78 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
79 | dd53ded3 | blueswir1 | |
80 | dd53ded3 | blueswir1 | /* ECC memory delay register */
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81 | dd53ded3 | blueswir1 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
82 | dd53ded3 | blueswir1 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
83 | dd53ded3 | blueswir1 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
84 | dd53ded3 | blueswir1 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
85 | dd53ded3 | blueswir1 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
86 | dd53ded3 | blueswir1 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
87 | dd53ded3 | blueswir1 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
88 | dd53ded3 | blueswir1 | #define ECC_MDR_MASK 0x7fffffff |
89 | 7eb0c8e8 | blueswir1 | |
90 | 7eb0c8e8 | blueswir1 | /* ECC fault status register */
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91 | dd53ded3 | blueswir1 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
92 | dd53ded3 | blueswir1 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
93 | dd53ded3 | blueswir1 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
94 | dd53ded3 | blueswir1 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
95 | dd53ded3 | blueswir1 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
96 | dd53ded3 | blueswir1 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
97 | dd53ded3 | blueswir1 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
98 | dd53ded3 | blueswir1 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
99 | 7eb0c8e8 | blueswir1 | |
100 | 7eb0c8e8 | blueswir1 | /* ECC fault address register 0 */
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101 | dd53ded3 | blueswir1 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
102 | dd53ded3 | blueswir1 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
103 | dd53ded3 | blueswir1 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
104 | dd53ded3 | blueswir1 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
105 | dd53ded3 | blueswir1 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
106 | dd53ded3 | blueswir1 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
107 | dd53ded3 | blueswir1 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
108 | dd53ded3 | blueswir1 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
109 | dd53ded3 | blueswir1 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
110 | 7eb0c8e8 | blueswir1 | |
111 | 7eb0c8e8 | blueswir1 | /* ECC diagnostic register */
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112 | dd53ded3 | blueswir1 | #define ECC_DR_CBX 0x00000001 |
113 | dd53ded3 | blueswir1 | #define ECC_DR_CB0 0x00000002 |
114 | dd53ded3 | blueswir1 | #define ECC_DR_CB1 0x00000004 |
115 | dd53ded3 | blueswir1 | #define ECC_DR_CB2 0x00000008 |
116 | dd53ded3 | blueswir1 | #define ECC_DR_CB4 0x00000010 |
117 | dd53ded3 | blueswir1 | #define ECC_DR_CB8 0x00000020 |
118 | dd53ded3 | blueswir1 | #define ECC_DR_CB16 0x00000040 |
119 | dd53ded3 | blueswir1 | #define ECC_DR_CB32 0x00000080 |
120 | dd53ded3 | blueswir1 | #define ECC_DR_DMODE 0x00000c00 |
121 | dd53ded3 | blueswir1 | |
122 | dd53ded3 | blueswir1 | #define ECC_NREGS 9 |
123 | 7eb0c8e8 | blueswir1 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
124 | dd53ded3 | blueswir1 | |
125 | dd53ded3 | blueswir1 | #define ECC_DIAG_SIZE 4 |
126 | dd53ded3 | blueswir1 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
127 | 7eb0c8e8 | blueswir1 | |
128 | 7eb0c8e8 | blueswir1 | typedef struct ECCState { |
129 | e42c20b4 | blueswir1 | qemu_irq irq; |
130 | 7eb0c8e8 | blueswir1 | uint32_t regs[ECC_NREGS]; |
131 | dd53ded3 | blueswir1 | uint8_t diag[ECC_DIAG_SIZE]; |
132 | 0bb3602c | blueswir1 | uint32_t version; |
133 | 7eb0c8e8 | blueswir1 | } ECCState; |
134 | 7eb0c8e8 | blueswir1 | |
135 | 7eb0c8e8 | blueswir1 | static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
136 | 7eb0c8e8 | blueswir1 | { |
137 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
138 | 7eb0c8e8 | blueswir1 | |
139 | e64d7d59 | blueswir1 | switch (addr >> 2) { |
140 | dd53ded3 | blueswir1 | case ECC_MER:
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141 | 0bb3602c | blueswir1 | if (s->version == ECC_MCC)
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142 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
143 | 0bb3602c | blueswir1 | else if (s->version == ECC_EMC) |
144 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
145 | 0bb3602c | blueswir1 | else if (s->version == ECC_SMC) |
146 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
147 | dd53ded3 | blueswir1 | DPRINTF("Write memory enable %08x\n", val);
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148 | 7eb0c8e8 | blueswir1 | break;
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149 | dd53ded3 | blueswir1 | case ECC_MDR:
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150 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
151 | dd53ded3 | blueswir1 | DPRINTF("Write memory delay %08x\n", val);
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152 | 7eb0c8e8 | blueswir1 | break;
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153 | dd53ded3 | blueswir1 | case ECC_MFSR:
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154 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MFSR] = val; |
155 | 0bb3602c | blueswir1 | qemu_irq_lower(s->irq); |
156 | dd53ded3 | blueswir1 | DPRINTF("Write memory fault status %08x\n", val);
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157 | 7eb0c8e8 | blueswir1 | break;
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158 | dd53ded3 | blueswir1 | case ECC_VCR:
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159 | 8f2ad0a3 | blueswir1 | s->regs[ECC_VCR] = val; |
160 | dd53ded3 | blueswir1 | DPRINTF("Write slot configuration %08x\n", val);
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161 | 7eb0c8e8 | blueswir1 | break;
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162 | dd53ded3 | blueswir1 | case ECC_DR:
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163 | 8f2ad0a3 | blueswir1 | s->regs[ECC_DR] = val; |
164 | 0bb3602c | blueswir1 | DPRINTF("Write diagnostic %08x\n", val);
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165 | dd53ded3 | blueswir1 | break;
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166 | dd53ded3 | blueswir1 | case ECC_ECR0:
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167 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
168 | dd53ded3 | blueswir1 | DPRINTF("Write event count 1 %08x\n", val);
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169 | 7eb0c8e8 | blueswir1 | break;
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170 | dd53ded3 | blueswir1 | case ECC_ECR1:
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171 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
172 | dd53ded3 | blueswir1 | DPRINTF("Write event count 2 %08x\n", val);
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173 | 7eb0c8e8 | blueswir1 | break;
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174 | 7eb0c8e8 | blueswir1 | } |
175 | 7eb0c8e8 | blueswir1 | } |
176 | 7eb0c8e8 | blueswir1 | |
177 | 7eb0c8e8 | blueswir1 | static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
178 | 7eb0c8e8 | blueswir1 | { |
179 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
180 | 7eb0c8e8 | blueswir1 | uint32_t ret = 0;
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181 | 7eb0c8e8 | blueswir1 | |
182 | e64d7d59 | blueswir1 | switch (addr >> 2) { |
183 | dd53ded3 | blueswir1 | case ECC_MER:
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184 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MER]; |
185 | dd53ded3 | blueswir1 | DPRINTF("Read memory enable %08x\n", ret);
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186 | 7eb0c8e8 | blueswir1 | break;
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187 | dd53ded3 | blueswir1 | case ECC_MDR:
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188 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MDR]; |
189 | dd53ded3 | blueswir1 | DPRINTF("Read memory delay %08x\n", ret);
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190 | 7eb0c8e8 | blueswir1 | break;
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191 | dd53ded3 | blueswir1 | case ECC_MFSR:
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192 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFSR]; |
193 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault status %08x\n", ret);
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194 | 7eb0c8e8 | blueswir1 | break;
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195 | dd53ded3 | blueswir1 | case ECC_VCR:
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196 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_VCR]; |
197 | dd53ded3 | blueswir1 | DPRINTF("Read slot configuration %08x\n", ret);
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198 | 7eb0c8e8 | blueswir1 | break;
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199 | dd53ded3 | blueswir1 | case ECC_MFAR0:
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200 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR0]; |
201 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault address 0 %08x\n", ret);
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202 | 7eb0c8e8 | blueswir1 | break;
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203 | dd53ded3 | blueswir1 | case ECC_MFAR1:
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204 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR1]; |
205 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault address 1 %08x\n", ret);
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206 | 7eb0c8e8 | blueswir1 | break;
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207 | dd53ded3 | blueswir1 | case ECC_DR:
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208 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_DR]; |
209 | dd53ded3 | blueswir1 | DPRINTF("Read diagnostic %08x\n", ret);
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210 | 7eb0c8e8 | blueswir1 | break;
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211 | dd53ded3 | blueswir1 | case ECC_ECR0:
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212 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
213 | dd53ded3 | blueswir1 | DPRINTF("Read event count 1 %08x\n", ret);
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214 | dd53ded3 | blueswir1 | break;
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215 | dd53ded3 | blueswir1 | case ECC_ECR1:
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216 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
217 | dd53ded3 | blueswir1 | DPRINTF("Read event count 2 %08x\n", ret);
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218 | 7eb0c8e8 | blueswir1 | break;
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219 | 7eb0c8e8 | blueswir1 | } |
220 | 7eb0c8e8 | blueswir1 | return ret;
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221 | 7eb0c8e8 | blueswir1 | } |
222 | 7eb0c8e8 | blueswir1 | |
223 | 7eb0c8e8 | blueswir1 | static CPUReadMemoryFunc *ecc_mem_read[3] = { |
224 | 7c560456 | blueswir1 | NULL,
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225 | 7c560456 | blueswir1 | NULL,
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226 | 7eb0c8e8 | blueswir1 | ecc_mem_readl, |
227 | 7eb0c8e8 | blueswir1 | }; |
228 | 7eb0c8e8 | blueswir1 | |
229 | 7eb0c8e8 | blueswir1 | static CPUWriteMemoryFunc *ecc_mem_write[3] = { |
230 | 7c560456 | blueswir1 | NULL,
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231 | 7c560456 | blueswir1 | NULL,
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232 | 7eb0c8e8 | blueswir1 | ecc_mem_writel, |
233 | 7eb0c8e8 | blueswir1 | }; |
234 | 7eb0c8e8 | blueswir1 | |
235 | dd53ded3 | blueswir1 | static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
236 | dd53ded3 | blueswir1 | uint32_t val) |
237 | dd53ded3 | blueswir1 | { |
238 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
239 | dd53ded3 | blueswir1 | |
240 | e64d7d59 | blueswir1 | DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); |
241 | dd53ded3 | blueswir1 | s->diag[addr & ECC_DIAG_MASK] = val; |
242 | dd53ded3 | blueswir1 | } |
243 | dd53ded3 | blueswir1 | |
244 | dd53ded3 | blueswir1 | static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
245 | dd53ded3 | blueswir1 | { |
246 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
247 | e64d7d59 | blueswir1 | uint32_t ret = s->diag[(int)addr];
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248 | e64d7d59 | blueswir1 | |
249 | e64d7d59 | blueswir1 | DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); |
250 | dd53ded3 | blueswir1 | return ret;
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251 | dd53ded3 | blueswir1 | } |
252 | dd53ded3 | blueswir1 | |
253 | dd53ded3 | blueswir1 | static CPUReadMemoryFunc *ecc_diag_mem_read[3] = { |
254 | dd53ded3 | blueswir1 | ecc_diag_mem_readb, |
255 | dd53ded3 | blueswir1 | NULL,
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256 | dd53ded3 | blueswir1 | NULL,
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257 | dd53ded3 | blueswir1 | }; |
258 | dd53ded3 | blueswir1 | |
259 | dd53ded3 | blueswir1 | static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = { |
260 | dd53ded3 | blueswir1 | ecc_diag_mem_writeb, |
261 | dd53ded3 | blueswir1 | NULL,
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262 | dd53ded3 | blueswir1 | NULL,
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263 | dd53ded3 | blueswir1 | }; |
264 | dd53ded3 | blueswir1 | |
265 | 7eb0c8e8 | blueswir1 | static int ecc_load(QEMUFile *f, void *opaque, int version_id) |
266 | 7eb0c8e8 | blueswir1 | { |
267 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
268 | 7eb0c8e8 | blueswir1 | int i;
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269 | 7eb0c8e8 | blueswir1 | |
270 | 0bb3602c | blueswir1 | if (version_id != 3) |
271 | 7eb0c8e8 | blueswir1 | return -EINVAL;
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272 | 7eb0c8e8 | blueswir1 | |
273 | 7eb0c8e8 | blueswir1 | for (i = 0; i < ECC_NREGS; i++) |
274 | 7eb0c8e8 | blueswir1 | qemu_get_be32s(f, &s->regs[i]); |
275 | 7eb0c8e8 | blueswir1 | |
276 | dd53ded3 | blueswir1 | for (i = 0; i < ECC_DIAG_SIZE; i++) |
277 | dd53ded3 | blueswir1 | qemu_get_8s(f, &s->diag[i]); |
278 | dd53ded3 | blueswir1 | |
279 | 0bb3602c | blueswir1 | qemu_get_be32s(f, &s->version); |
280 | 0bb3602c | blueswir1 | |
281 | 7eb0c8e8 | blueswir1 | return 0; |
282 | 7eb0c8e8 | blueswir1 | } |
283 | 7eb0c8e8 | blueswir1 | |
284 | 7eb0c8e8 | blueswir1 | static void ecc_save(QEMUFile *f, void *opaque) |
285 | 7eb0c8e8 | blueswir1 | { |
286 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
287 | 7eb0c8e8 | blueswir1 | int i;
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288 | 7eb0c8e8 | blueswir1 | |
289 | 7eb0c8e8 | blueswir1 | for (i = 0; i < ECC_NREGS; i++) |
290 | 7eb0c8e8 | blueswir1 | qemu_put_be32s(f, &s->regs[i]); |
291 | dd53ded3 | blueswir1 | |
292 | dd53ded3 | blueswir1 | for (i = 0; i < ECC_DIAG_SIZE; i++) |
293 | dd53ded3 | blueswir1 | qemu_put_8s(f, &s->diag[i]); |
294 | 0bb3602c | blueswir1 | |
295 | 0bb3602c | blueswir1 | qemu_put_be32s(f, &s->version); |
296 | 7eb0c8e8 | blueswir1 | } |
297 | 7eb0c8e8 | blueswir1 | |
298 | 7eb0c8e8 | blueswir1 | static void ecc_reset(void *opaque) |
299 | 7eb0c8e8 | blueswir1 | { |
300 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
301 | 7eb0c8e8 | blueswir1 | |
302 | 0bb3602c | blueswir1 | if (s->version == ECC_MCC)
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303 | 0bb3602c | blueswir1 | s->regs[ECC_MER] &= ECC_MER_REU; |
304 | 0bb3602c | blueswir1 | else
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305 | 0bb3602c | blueswir1 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
306 | 0bb3602c | blueswir1 | ECC_MER_DCI); |
307 | dd53ded3 | blueswir1 | s->regs[ECC_MDR] = 0x20;
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308 | dd53ded3 | blueswir1 | s->regs[ECC_MFSR] = 0;
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309 | dd53ded3 | blueswir1 | s->regs[ECC_VCR] = 0;
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310 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR0] = 0x07c00000;
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311 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR1] = 0;
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312 | dd53ded3 | blueswir1 | s->regs[ECC_DR] = 0;
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313 | dd53ded3 | blueswir1 | s->regs[ECC_ECR0] = 0;
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314 | dd53ded3 | blueswir1 | s->regs[ECC_ECR1] = 0;
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315 | 7eb0c8e8 | blueswir1 | } |
316 | 7eb0c8e8 | blueswir1 | |
317 | e42c20b4 | blueswir1 | void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
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318 | 7eb0c8e8 | blueswir1 | { |
319 | 7eb0c8e8 | blueswir1 | int ecc_io_memory;
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320 | 7eb0c8e8 | blueswir1 | ECCState *s; |
321 | 7eb0c8e8 | blueswir1 | |
322 | 7eb0c8e8 | blueswir1 | s = qemu_mallocz(sizeof(ECCState));
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323 | 7eb0c8e8 | blueswir1 | |
324 | 0bb3602c | blueswir1 | s->version = version; |
325 | 7eb0c8e8 | blueswir1 | s->regs[0] = version;
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326 | e42c20b4 | blueswir1 | s->irq = irq; |
327 | 7eb0c8e8 | blueswir1 | |
328 | 7eb0c8e8 | blueswir1 | ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
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329 | 7eb0c8e8 | blueswir1 | cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); |
330 | 0bb3602c | blueswir1 | if (version == ECC_MCC) { // SS-600MP only |
331 | dd53ded3 | blueswir1 | ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
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332 | dd53ded3 | blueswir1 | ecc_diag_mem_write, s); |
333 | dd53ded3 | blueswir1 | cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
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334 | dd53ded3 | blueswir1 | ecc_io_memory); |
335 | dd53ded3 | blueswir1 | } |
336 | 0bb3602c | blueswir1 | register_savevm("ECC", base, 3, ecc_save, ecc_load, s); |
337 | 8217606e | Jan Kiszka | qemu_register_reset(ecc_reset, 0, s);
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338 | 7eb0c8e8 | blueswir1 | ecc_reset(s); |
339 | 7eb0c8e8 | blueswir1 | return s;
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340 | 7eb0c8e8 | blueswir1 | } |