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1 | 75dd595b | aurel32 | /*
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2 | 75dd595b | aurel32 | * Qemu PowerPC 440 chip emulation
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3 | 75dd595b | aurel32 | *
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4 | 75dd595b | aurel32 | * Copyright 2007 IBM Corporation.
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5 | 75dd595b | aurel32 | * Authors:
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6 | 75dd595b | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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7 | 75dd595b | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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8 | 75dd595b | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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9 | 75dd595b | aurel32 | *
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10 | 75dd595b | aurel32 | * This work is licensed under the GNU GPL license version 2 or later.
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11 | 75dd595b | aurel32 | *
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12 | 75dd595b | aurel32 | */
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13 | 75dd595b | aurel32 | |
14 | 75dd595b | aurel32 | #include "hw.h" |
15 | 75dd595b | aurel32 | #include "isa.h" |
16 | 75dd595b | aurel32 | #include "ppc.h" |
17 | 75dd595b | aurel32 | #include "ppc4xx.h" |
18 | 75dd595b | aurel32 | #include "ppc440.h" |
19 | 75dd595b | aurel32 | #include "ppc405.h" |
20 | 75dd595b | aurel32 | #include "sysemu.h" |
21 | 75dd595b | aurel32 | #include "kvm.h" |
22 | 75dd595b | aurel32 | |
23 | 75dd595b | aurel32 | #define PPC440EP_PCI_CONFIG 0xeec00000 |
24 | 75dd595b | aurel32 | #define PPC440EP_PCI_INTACK 0xeed00000 |
25 | 75dd595b | aurel32 | #define PPC440EP_PCI_SPECIAL 0xeed00000 |
26 | 75dd595b | aurel32 | #define PPC440EP_PCI_REGS 0xef400000 |
27 | 75dd595b | aurel32 | #define PPC440EP_PCI_IO 0xe8000000 |
28 | 75dd595b | aurel32 | #define PPC440EP_PCI_IOLEN 0x00010000 |
29 | 75dd595b | aurel32 | |
30 | 75dd595b | aurel32 | #define PPC440EP_SDRAM_NR_BANKS 4 |
31 | 75dd595b | aurel32 | |
32 | 75dd595b | aurel32 | static const unsigned int ppc440ep_sdram_bank_sizes[] = { |
33 | 75dd595b | aurel32 | 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 |
34 | 75dd595b | aurel32 | }; |
35 | 75dd595b | aurel32 | |
36 | 75dd595b | aurel32 | CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, |
37 | 75dd595b | aurel32 | const unsigned int pci_irq_nrs[4], int do_init) |
38 | 75dd595b | aurel32 | { |
39 | 75dd595b | aurel32 | target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
40 | 75dd595b | aurel32 | target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; |
41 | 75dd595b | aurel32 | CPUState *env; |
42 | 75dd595b | aurel32 | ppc4xx_mmio_t *mmio; |
43 | 75dd595b | aurel32 | qemu_irq *pic; |
44 | 75dd595b | aurel32 | qemu_irq *irqs; |
45 | 75dd595b | aurel32 | qemu_irq *pci_irqs; |
46 | 75dd595b | aurel32 | |
47 | 75dd595b | aurel32 | env = cpu_ppc_init("440EP");
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48 | 75dd595b | aurel32 | if (!env && kvm_enabled()) {
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49 | 75dd595b | aurel32 | /* XXX Since qemu doesn't yet emulate 440, we just say it's a 405.
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50 | 75dd595b | aurel32 | * Since KVM doesn't use qemu's CPU emulation it seems to be working
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51 | 75dd595b | aurel32 | * OK. */
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52 | 75dd595b | aurel32 | env = cpu_ppc_init("405");
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53 | 75dd595b | aurel32 | } |
54 | 75dd595b | aurel32 | if (!env) {
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55 | 75dd595b | aurel32 | fprintf(stderr, "Unable to initialize CPU!\n");
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56 | 75dd595b | aurel32 | exit(1);
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57 | 75dd595b | aurel32 | } |
58 | 75dd595b | aurel32 | |
59 | 75dd595b | aurel32 | ppc_dcr_init(env, NULL, NULL); |
60 | 75dd595b | aurel32 | |
61 | 75dd595b | aurel32 | /* interrupt controller */
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62 | 75dd595b | aurel32 | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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63 | 75dd595b | aurel32 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
64 | 75dd595b | aurel32 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
65 | 75dd595b | aurel32 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
66 | 75dd595b | aurel32 | |
67 | 75dd595b | aurel32 | /* SDRAM controller */
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68 | 75dd595b | aurel32 | memset(ram_bases, 0, sizeof(ram_bases)); |
69 | 75dd595b | aurel32 | memset(ram_sizes, 0, sizeof(ram_sizes)); |
70 | 75dd595b | aurel32 | *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, |
71 | 75dd595b | aurel32 | ram_bases, ram_sizes, |
72 | 75dd595b | aurel32 | ppc440ep_sdram_bank_sizes); |
73 | 75dd595b | aurel32 | /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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74 | 75dd595b | aurel32 | ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
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75 | 75dd595b | aurel32 | ram_sizes, do_init); |
76 | 75dd595b | aurel32 | |
77 | 75dd595b | aurel32 | /* PCI */
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78 | 75dd595b | aurel32 | pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4); |
79 | 75dd595b | aurel32 | pci_irqs[0] = pic[pci_irq_nrs[0]]; |
80 | 75dd595b | aurel32 | pci_irqs[1] = pic[pci_irq_nrs[1]]; |
81 | 75dd595b | aurel32 | pci_irqs[2] = pic[pci_irq_nrs[2]]; |
82 | 75dd595b | aurel32 | pci_irqs[3] = pic[pci_irq_nrs[3]]; |
83 | 75dd595b | aurel32 | *pcip = ppc4xx_pci_init(env, pci_irqs, |
84 | 75dd595b | aurel32 | PPC440EP_PCI_CONFIG, |
85 | 75dd595b | aurel32 | PPC440EP_PCI_INTACK, |
86 | 75dd595b | aurel32 | PPC440EP_PCI_SPECIAL, |
87 | 75dd595b | aurel32 | PPC440EP_PCI_REGS); |
88 | 75dd595b | aurel32 | if (!*pcip)
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89 | 75dd595b | aurel32 | printf("couldn't create PCI controller!\n");
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90 | 75dd595b | aurel32 | |
91 | 75dd595b | aurel32 | isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); |
92 | 75dd595b | aurel32 | |
93 | 75dd595b | aurel32 | /* MMIO -- most "miscellaneous" devices live above 0xef600000. */
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94 | 75dd595b | aurel32 | mmio = ppc4xx_mmio_init(env, 0xef600000);
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95 | 75dd595b | aurel32 | |
96 | 75dd595b | aurel32 | if (serial_hds[0]) |
97 | 75dd595b | aurel32 | ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
98 | 75dd595b | aurel32 | |
99 | 75dd595b | aurel32 | if (serial_hds[1]) |
100 | 75dd595b | aurel32 | ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
101 | 75dd595b | aurel32 | |
102 | 75dd595b | aurel32 | return env;
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103 | 75dd595b | aurel32 | } |