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/*
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* QEMU ETRAX DMA Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include <sys/time.h> |
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#include "hw.h" |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "etraxfs_dma.h" |
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#define D(x)
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#define RW_DATA (0x0 / 4) |
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#define RW_SAVED_DATA (0x58 / 4) |
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#define RW_SAVED_DATA_BUF (0x5c / 4) |
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#define RW_GROUP (0x60 / 4) |
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#define RW_GROUP_DOWN (0x7c / 4) |
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#define RW_CMD (0x80 / 4) |
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#define RW_CFG (0x84 / 4) |
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#define RW_STAT (0x88 / 4) |
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#define RW_INTR_MASK (0x8c / 4) |
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#define RW_ACK_INTR (0x90 / 4) |
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#define R_INTR (0x94 / 4) |
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#define R_MASKED_INTR (0x98 / 4) |
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#define RW_STREAM_CMD (0x9c / 4) |
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#define DMA_REG_MAX (0x100 / 4) |
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group { |
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struct dma_descr_group *next;
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unsigned eol : 1; |
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unsigned tol : 1; |
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unsigned bol : 1; |
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unsigned : 1; |
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unsigned intr : 1; |
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unsigned : 2; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md : 16; |
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down; |
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} dma_descr_group; |
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context { |
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struct dma_descr_context *next;
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unsigned eol : 1; |
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unsigned : 3; |
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unsigned intr : 1; |
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unsigned : 1; |
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unsigned store_mode : 1; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md0 : 16; |
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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struct dma_descr_data *saved_data;
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char *saved_data_buf;
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} dma_descr_context; |
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data { |
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struct dma_descr_data *next;
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char *buf;
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unsigned eol : 1; |
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unsigned : 2; |
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unsigned out_eop : 1; |
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unsigned intr : 1; |
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unsigned wait : 1; |
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unsigned : 2; |
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unsigned : 3; |
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unsigned in_eop : 1; |
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unsigned : 4; |
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unsigned md : 16; |
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char *after;
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} dma_descr_data; |
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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}; |
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enum dma_ch_state
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{ |
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RST = 1,
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STOPPED = 2,
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RUNNING = 4
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}; |
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struct fs_dma_channel
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{ |
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qemu_irq irq; |
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struct etraxfs_dma_client *client;
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/* Internal status. */
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int stream_cmd_src;
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enum dma_ch_state state;
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unsigned int input : 1; |
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unsigned int eol : 1; |
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struct dma_descr_group current_g;
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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uint32_t regs[DMA_REG_MAX]; |
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}; |
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struct fs_dma_ctrl
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{ |
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int map;
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CPUState *env; |
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int nr_channels;
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struct fs_dma_channel *channels;
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QEMUBH *bh; |
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}; |
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static void DMA_run(void *opaque); |
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static int channel_out_run(struct fs_dma_ctrl *ctrl, int c); |
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static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
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{ |
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return ctrl->channels[c].regs[reg];
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} |
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static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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return channel_reg(ctrl, c, RW_CFG) & 2; |
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} |
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static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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return (channel_reg(ctrl, c, RW_CFG) & 1) |
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&& ctrl->channels[c].client; |
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} |
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static inline int fs_channel(target_phys_addr_t addr) |
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{ |
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/* Every channel has a 0x2000 ctrl register map. */
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return addr >> 13; |
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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} |
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static void dump_c(int ch, struct dma_descr_context *c) |
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{ |
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", c->next);
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printf("saved_data=%p\n", c->saved_data);
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printf("saved_data_buf=%p\n", c->saved_data_buf);
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printf("eol=%x\n", (uint32_t) c->eol);
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} |
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static void dump_d(int ch, struct dma_descr_data *d) |
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{ |
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", d->next);
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printf("buf=%p\n", d->buf);
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printf("after=%p\n", d->after);
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printf("intr=%x\n", (uint32_t) d->intr);
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printf("out_eop=%x\n", (uint32_t) d->out_eop);
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printf("in_eop=%x\n", (uint32_t) d->in_eop);
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printf("eol=%x\n", (uint32_t) d->eol);
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} |
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#endif
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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D(dump_c(c, &ctrl->channels[c].current_c)); |
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/* I guess this should update the current pos. */
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
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} |
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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ctrl->channels[c].regs[RW_DATA] = addr; |
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} |
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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} |
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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} |
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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/* FIXME: */
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} |
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static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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if (ctrl->channels[c].client)
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{ |
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ctrl->channels[c].eol = 0;
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ctrl->channels[c].state = RUNNING; |
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if (!ctrl->channels[c].input)
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channel_out_run(ctrl, c); |
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} else
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printf("WARNING: starting DMA ch %d with no client\n", c);
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qemu_bh_schedule_idle(ctrl->bh); |
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} |
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static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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if (!channel_en(ctrl, c)
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|| channel_stopped(ctrl, c) |
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|| ctrl->channels[c].state != RUNNING |
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/* Only reload the current data descriptor if it has eol set. */
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|| !ctrl->channels[c].current_d.eol) { |
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D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
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c, ctrl->channels[c].state, |
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channel_stopped(ctrl, c), |
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channel_en(ctrl,c), |
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ctrl->channels[c].eol)); |
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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return;
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} |
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/* Reload the current descriptor. */
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channel_load_d(ctrl, c); |
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %p\n", c,
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ctrl->channels[c].current_d.next)); |
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
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channel_load_d(ctrl, c); |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
357 |
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channel_start(ctrl, c); |
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} |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
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} |
363 |
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
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{ |
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unsigned int cmd = v & ((1 << 10) - 1); |
367 |
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D(printf("%s ch=%d cmd=%x\n",
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__func__, c, cmd)); |
370 |
if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c); |
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if (cmd & regk_dma_burst)
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channel_start(ctrl, c); |
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} |
375 |
|
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if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c); |
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} |
379 |
} |
380 |
|
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static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
382 |
{ |
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D(printf("%s %d\n", __func__, c));
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ctrl->channels[c].regs[R_INTR] &= |
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~(ctrl->channels[c].regs[RW_ACK_INTR]); |
386 |
|
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ctrl->channels[c].regs[R_MASKED_INTR] = |
388 |
ctrl->channels[c].regs[R_INTR] |
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& ctrl->channels[c].regs[RW_INTR_MASK]; |
390 |
|
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D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
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c, |
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ctrl->channels[c].regs[R_MASKED_INTR])); |
394 |
|
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qemu_set_irq(ctrl->channels[c].irq, |
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!!ctrl->channels[c].regs[R_MASKED_INTR]); |
397 |
} |
398 |
|
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static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
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{ |
401 |
uint32_t len; |
402 |
uint32_t saved_data_buf; |
403 |
unsigned char buf[2 * 1024]; |
404 |
|
405 |
if (ctrl->channels[c].eol)
|
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return 0; |
407 |
|
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do {
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D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
|
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c, |
411 |
(uint32_t)ctrl->channels[c].current_d.buf, |
412 |
(uint32_t)ctrl->channels[c].current_d.after, |
413 |
saved_data_buf)); |
414 |
|
415 |
channel_load_d(ctrl, c); |
416 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
417 |
len = (uint32_t)(unsigned long) |
418 |
ctrl->channels[c].current_d.after; |
419 |
len -= saved_data_buf; |
420 |
|
421 |
if (len > sizeof buf) |
422 |
len = sizeof buf;
|
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cpu_physical_memory_read (saved_data_buf, buf, len); |
424 |
|
425 |
D(printf("channel %d pushes %x %u bytes\n", c,
|
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saved_data_buf, len)); |
427 |
|
428 |
if (ctrl->channels[c].client->client.push)
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ctrl->channels[c].client->client.push( |
430 |
ctrl->channels[c].client->client.opaque, |
431 |
buf, len); |
432 |
else
|
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printf("WARNING: DMA ch%d dataloss,"
|
434 |
" no attached client.\n", c);
|
435 |
|
436 |
saved_data_buf += len; |
437 |
|
438 |
if (saved_data_buf == (uint32_t)(unsigned long) |
439 |
ctrl->channels[c].current_d.after) { |
440 |
/* Done. Step to next. */
|
441 |
if (ctrl->channels[c].current_d.out_eop) {
|
442 |
/* TODO: signal eop to the client. */
|
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D(printf("signal eop\n"));
|
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} |
445 |
if (ctrl->channels[c].current_d.intr) {
|
446 |
/* TODO: signal eop to the client. */
|
447 |
/* data intr. */
|
448 |
D(printf("signal intr %d eol=%d\n",
|
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len, ctrl->channels[c].current_d.eol)); |
450 |
ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
451 |
channel_update_irq(ctrl, c); |
452 |
} |
453 |
channel_store_d(ctrl, c); |
454 |
if (ctrl->channels[c].current_d.eol) {
|
455 |
D(printf("channel %d EOL\n", c));
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ctrl->channels[c].eol = 1;
|
457 |
|
458 |
/* Mark the context as disabled. */
|
459 |
ctrl->channels[c].current_c.dis = 1;
|
460 |
channel_store_c(ctrl, c); |
461 |
|
462 |
channel_stop(ctrl, c); |
463 |
} else {
|
464 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
465 |
(uint32_t)(unsigned long)ctrl-> |
466 |
channels[c].current_d.next; |
467 |
/* Load new descriptor. */
|
468 |
channel_load_d(ctrl, c); |
469 |
saved_data_buf = (uint32_t)(unsigned long) |
470 |
ctrl->channels[c].current_d.buf; |
471 |
} |
472 |
|
473 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
474 |
saved_data_buf; |
475 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
476 |
} |
477 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
478 |
} while (!ctrl->channels[c].eol);
|
479 |
return 1; |
480 |
} |
481 |
|
482 |
static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
483 |
unsigned char *buf, int buflen, int eop) |
484 |
{ |
485 |
uint32_t len; |
486 |
uint32_t saved_data_buf; |
487 |
|
488 |
if (ctrl->channels[c].eol == 1) |
489 |
return 0; |
490 |
|
491 |
channel_load_d(ctrl, c); |
492 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
493 |
len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
494 |
len -= saved_data_buf; |
495 |
|
496 |
if (len > buflen)
|
497 |
len = buflen; |
498 |
|
499 |
cpu_physical_memory_write (saved_data_buf, buf, len); |
500 |
saved_data_buf += len; |
501 |
|
502 |
if (saved_data_buf ==
|
503 |
(uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
504 |
|| eop) { |
505 |
uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
506 |
|
507 |
D(printf("in dscr end len=%d\n",
|
508 |
ctrl->channels[c].current_d.after |
509 |
- ctrl->channels[c].current_d.buf)); |
510 |
ctrl->channels[c].current_d.after = |
511 |
(void *)(unsigned long) saved_data_buf; |
512 |
|
513 |
/* Done. Step to next. */
|
514 |
if (ctrl->channels[c].current_d.intr) {
|
515 |
/* TODO: signal eop to the client. */
|
516 |
/* data intr. */
|
517 |
ctrl->channels[c].regs[R_INTR] |= 3;
|
518 |
} |
519 |
if (eop) {
|
520 |
ctrl->channels[c].current_d.in_eop = 1;
|
521 |
ctrl->channels[c].regs[R_INTR] |= 8;
|
522 |
} |
523 |
if (r_intr != ctrl->channels[c].regs[R_INTR])
|
524 |
channel_update_irq(ctrl, c); |
525 |
|
526 |
channel_store_d(ctrl, c); |
527 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
528 |
|
529 |
if (ctrl->channels[c].current_d.eol) {
|
530 |
D(printf("channel %d EOL\n", c));
|
531 |
ctrl->channels[c].eol = 1;
|
532 |
|
533 |
/* Mark the context as disabled. */
|
534 |
ctrl->channels[c].current_c.dis = 1;
|
535 |
channel_store_c(ctrl, c); |
536 |
|
537 |
channel_stop(ctrl, c); |
538 |
} else {
|
539 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
540 |
(uint32_t)(unsigned long)ctrl-> |
541 |
channels[c].current_d.next; |
542 |
/* Load new descriptor. */
|
543 |
channel_load_d(ctrl, c); |
544 |
saved_data_buf = (uint32_t)(unsigned long) |
545 |
ctrl->channels[c].current_d.buf; |
546 |
} |
547 |
} |
548 |
|
549 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
550 |
return len;
|
551 |
} |
552 |
|
553 |
static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
554 |
{ |
555 |
if (ctrl->channels[c].client->client.pull) {
|
556 |
ctrl->channels[c].client->client.pull( |
557 |
ctrl->channels[c].client->client.opaque); |
558 |
return 1; |
559 |
} else
|
560 |
return 0; |
561 |
} |
562 |
|
563 |
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
564 |
{ |
565 |
hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr); |
566 |
return 0; |
567 |
} |
568 |
|
569 |
static uint32_t
|
570 |
dma_readl (void *opaque, target_phys_addr_t addr)
|
571 |
{ |
572 |
struct fs_dma_ctrl *ctrl = opaque;
|
573 |
int c;
|
574 |
uint32_t r = 0;
|
575 |
|
576 |
/* Make addr relative to this channel and bounded to nr regs. */
|
577 |
c = fs_channel(addr); |
578 |
addr &= 0xff;
|
579 |
addr >>= 2;
|
580 |
switch (addr)
|
581 |
{ |
582 |
case RW_STAT:
|
583 |
r = ctrl->channels[c].state & 7;
|
584 |
r |= ctrl->channels[c].eol << 5;
|
585 |
r |= ctrl->channels[c].stream_cmd_src << 8;
|
586 |
break;
|
587 |
|
588 |
default:
|
589 |
r = ctrl->channels[c].regs[addr]; |
590 |
D(printf ("%s c=%d addr=%x\n",
|
591 |
__func__, c, addr)); |
592 |
break;
|
593 |
} |
594 |
return r;
|
595 |
} |
596 |
|
597 |
static void |
598 |
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
599 |
{ |
600 |
hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr); |
601 |
} |
602 |
|
603 |
static void |
604 |
dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
605 |
{ |
606 |
if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) { |
607 |
if (ctrl->channels[c].regs[RW_CFG] & 2) |
608 |
ctrl->channels[c].state = STOPPED; |
609 |
if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
610 |
ctrl->channels[c].state = RST; |
611 |
} |
612 |
} |
613 |
|
614 |
static void |
615 |
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
616 |
{ |
617 |
struct fs_dma_ctrl *ctrl = opaque;
|
618 |
int c;
|
619 |
|
620 |
/* Make addr relative to this channel and bounded to nr regs. */
|
621 |
c = fs_channel(addr); |
622 |
addr &= 0xff;
|
623 |
addr >>= 2;
|
624 |
switch (addr)
|
625 |
{ |
626 |
case RW_DATA:
|
627 |
ctrl->channels[c].regs[addr] = value; |
628 |
break;
|
629 |
|
630 |
case RW_CFG:
|
631 |
ctrl->channels[c].regs[addr] = value; |
632 |
dma_update_state(ctrl, c); |
633 |
break;
|
634 |
case RW_CMD:
|
635 |
/* continue. */
|
636 |
if (value & ~1) |
637 |
printf("Invalid store to ch=%d RW_CMD %x\n",
|
638 |
c, value); |
639 |
ctrl->channels[c].regs[addr] = value; |
640 |
channel_continue(ctrl, c); |
641 |
break;
|
642 |
|
643 |
case RW_SAVED_DATA:
|
644 |
case RW_SAVED_DATA_BUF:
|
645 |
case RW_GROUP:
|
646 |
case RW_GROUP_DOWN:
|
647 |
ctrl->channels[c].regs[addr] = value; |
648 |
break;
|
649 |
|
650 |
case RW_ACK_INTR:
|
651 |
case RW_INTR_MASK:
|
652 |
ctrl->channels[c].regs[addr] = value; |
653 |
channel_update_irq(ctrl, c); |
654 |
if (addr == RW_ACK_INTR)
|
655 |
ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
656 |
break;
|
657 |
|
658 |
case RW_STREAM_CMD:
|
659 |
if (value & ~1023) |
660 |
printf("Invalid store to ch=%d "
|
661 |
"RW_STREAMCMD %x\n",
|
662 |
c, value); |
663 |
ctrl->channels[c].regs[addr] = value; |
664 |
D(printf("stream_cmd ch=%d\n", c));
|
665 |
channel_stream_cmd(ctrl, c, value); |
666 |
break;
|
667 |
|
668 |
default:
|
669 |
D(printf ("%s c=%d %x %x\n", __func__, c, addr));
|
670 |
break;
|
671 |
} |
672 |
} |
673 |
|
674 |
static CPUReadMemoryFunc *dma_read[] = {
|
675 |
&dma_rinvalid, |
676 |
&dma_rinvalid, |
677 |
&dma_readl, |
678 |
}; |
679 |
|
680 |
static CPUWriteMemoryFunc *dma_write[] = {
|
681 |
&dma_winvalid, |
682 |
&dma_winvalid, |
683 |
&dma_writel, |
684 |
}; |
685 |
|
686 |
static int etraxfs_dmac_run(void *opaque) |
687 |
{ |
688 |
struct fs_dma_ctrl *ctrl = opaque;
|
689 |
int i;
|
690 |
int p = 0; |
691 |
|
692 |
for (i = 0; |
693 |
i < ctrl->nr_channels; |
694 |
i++) |
695 |
{ |
696 |
if (ctrl->channels[i].state == RUNNING)
|
697 |
{ |
698 |
if (ctrl->channels[i].input) {
|
699 |
p += channel_in_run(ctrl, i); |
700 |
} else {
|
701 |
p += channel_out_run(ctrl, i); |
702 |
} |
703 |
} |
704 |
} |
705 |
return p;
|
706 |
} |
707 |
|
708 |
int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
709 |
void *buf, int len, int eop) |
710 |
{ |
711 |
return channel_in_process(client->ctrl, client->channel,
|
712 |
buf, len, eop); |
713 |
} |
714 |
|
715 |
/* Connect an IRQ line with a channel. */
|
716 |
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
717 |
{ |
718 |
struct fs_dma_ctrl *ctrl = opaque;
|
719 |
ctrl->channels[c].irq = *line; |
720 |
ctrl->channels[c].input = input; |
721 |
} |
722 |
|
723 |
void etraxfs_dmac_connect_client(void *opaque, int c, |
724 |
struct etraxfs_dma_client *cl)
|
725 |
{ |
726 |
struct fs_dma_ctrl *ctrl = opaque;
|
727 |
cl->ctrl = ctrl; |
728 |
cl->channel = c; |
729 |
ctrl->channels[c].client = cl; |
730 |
} |
731 |
|
732 |
|
733 |
static void DMA_run(void *opaque) |
734 |
{ |
735 |
struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
736 |
int p = 1; |
737 |
|
738 |
if (vm_running)
|
739 |
p = etraxfs_dmac_run(etraxfs_dmac); |
740 |
|
741 |
if (p)
|
742 |
qemu_bh_schedule_idle(etraxfs_dmac->bh); |
743 |
} |
744 |
|
745 |
void *etraxfs_dmac_init(CPUState *env,
|
746 |
target_phys_addr_t base, int nr_channels)
|
747 |
{ |
748 |
struct fs_dma_ctrl *ctrl = NULL; |
749 |
|
750 |
ctrl = qemu_mallocz(sizeof *ctrl);
|
751 |
|
752 |
ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
753 |
|
754 |
ctrl->env = env; |
755 |
ctrl->nr_channels = nr_channels; |
756 |
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
757 |
|
758 |
ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
|
759 |
cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
|
760 |
return ctrl;
|
761 |
} |