Revision 5631e69c target-openrisc/translate.c
| b/target-openrisc/translate.c | ||
|---|---|---|
| 707 | 707 |
uint32_t L6, K5; |
| 708 | 708 |
#endif |
| 709 | 709 |
uint32_t I16, I5, I11, N26, tmp; |
| 710 |
TCGMemOp mop; |
|
| 711 |
|
|
| 710 | 712 |
op0 = extract32(insn, 26, 6); |
| 711 | 713 |
op1 = extract32(insn, 24, 2); |
| 712 | 714 |
ra = extract32(insn, 16, 5); |
| ... | ... | |
| 838 | 840 |
/*#ifdef TARGET_OPENRISC64 |
| 839 | 841 |
case 0x20: l.ld |
| 840 | 842 |
LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
|
| 841 |
{
|
|
| 842 |
check_ob64s(dc); |
|
| 843 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
|
| 844 |
tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 845 |
tcg_gen_qemu_ld64(cpu_R[rd], t0, dc->mem_idx); |
|
| 846 |
tcg_temp_free_i64(t0); |
|
| 847 |
} |
|
| 848 |
break; |
|
| 843 |
check_ob64s(dc); |
|
| 844 |
mop = MO_TEQ; |
|
| 845 |
goto do_load; |
|
| 849 | 846 |
#endif*/ |
| 850 | 847 |
|
| 851 | 848 |
case 0x21: /* l.lwz */ |
| 852 | 849 |
LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
|
| 853 |
{
|
|
| 854 |
TCGv t0 = tcg_temp_new(); |
|
| 855 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 856 |
tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx); |
|
| 857 |
tcg_temp_free(t0); |
|
| 858 |
} |
|
| 859 |
break; |
|
| 850 |
mop = MO_TEUL; |
|
| 851 |
goto do_load; |
|
| 860 | 852 |
|
| 861 | 853 |
case 0x22: /* l.lws */ |
| 862 | 854 |
LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
|
| 863 |
{
|
|
| 864 |
TCGv t0 = tcg_temp_new(); |
|
| 865 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 866 |
tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx); |
|
| 867 |
tcg_temp_free(t0); |
|
| 868 |
} |
|
| 869 |
break; |
|
| 855 |
mop = MO_TESL; |
|
| 856 |
goto do_load; |
|
| 870 | 857 |
|
| 871 | 858 |
case 0x23: /* l.lbz */ |
| 872 | 859 |
LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
|
| 873 |
{
|
|
| 874 |
TCGv t0 = tcg_temp_new(); |
|
| 875 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 876 |
tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx); |
|
| 877 |
tcg_temp_free(t0); |
|
| 878 |
} |
|
| 879 |
break; |
|
| 860 |
mop = MO_UB; |
|
| 861 |
goto do_load; |
|
| 880 | 862 |
|
| 881 | 863 |
case 0x24: /* l.lbs */ |
| 882 | 864 |
LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
|
| 883 |
{
|
|
| 884 |
TCGv t0 = tcg_temp_new(); |
|
| 885 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 886 |
tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx); |
|
| 887 |
tcg_temp_free(t0); |
|
| 888 |
} |
|
| 889 |
break; |
|
| 865 |
mop = MO_SB; |
|
| 866 |
goto do_load; |
|
| 890 | 867 |
|
| 891 | 868 |
case 0x25: /* l.lhz */ |
| 892 | 869 |
LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
|
| 893 |
{
|
|
| 894 |
TCGv t0 = tcg_temp_new(); |
|
| 895 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
|
| 896 |
tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx); |
|
| 897 |
tcg_temp_free(t0); |
|
| 898 |
} |
|
| 899 |
break; |
|
| 870 |
mop = MO_TEUW; |
|
| 871 |
goto do_load; |
|
| 900 | 872 |
|
| 901 | 873 |
case 0x26: /* l.lhs */ |
| 902 | 874 |
LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
|
| 875 |
mop = MO_TESW; |
|
| 876 |
goto do_load; |
|
| 877 |
|
|
| 878 |
do_load: |
|
| 903 | 879 |
{
|
| 904 | 880 |
TCGv t0 = tcg_temp_new(); |
| 905 | 881 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); |
| 906 |
tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
|
|
| 882 |
tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
|
|
| 907 | 883 |
tcg_temp_free(t0); |
| 908 | 884 |
} |
| 909 | 885 |
break; |
| ... | ... | |
| 1042 | 1018 |
/*#ifdef TARGET_OPENRISC64 |
| 1043 | 1019 |
case 0x34: l.sd |
| 1044 | 1020 |
LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
|
| 1045 |
{
|
|
| 1046 |
check_ob64s(dc); |
|
| 1047 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
|
| 1048 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); |
|
| 1049 |
tcg_gen_qemu_st64(cpu_R[rb], t0, dc->mem_idx); |
|
| 1050 |
tcg_temp_free_i64(t0); |
|
| 1051 |
} |
|
| 1052 |
break; |
|
| 1021 |
check_ob64s(dc); |
|
| 1022 |
mop = MO_TEQ; |
|
| 1023 |
goto do_store; |
|
| 1053 | 1024 |
#endif*/ |
| 1054 | 1025 |
|
| 1055 | 1026 |
case 0x35: /* l.sw */ |
| 1056 | 1027 |
LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
|
| 1057 |
{
|
|
| 1058 |
TCGv t0 = tcg_temp_new(); |
|
| 1059 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); |
|
| 1060 |
tcg_gen_qemu_st32(cpu_R[rb], t0, dc->mem_idx); |
|
| 1061 |
tcg_temp_free(t0); |
|
| 1062 |
} |
|
| 1063 |
break; |
|
| 1028 |
mop = MO_TEUL; |
|
| 1029 |
goto do_store; |
|
| 1064 | 1030 |
|
| 1065 | 1031 |
case 0x36: /* l.sb */ |
| 1066 | 1032 |
LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
|
| 1067 |
{
|
|
| 1068 |
TCGv t0 = tcg_temp_new(); |
|
| 1069 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); |
|
| 1070 |
tcg_gen_qemu_st8(cpu_R[rb], t0, dc->mem_idx); |
|
| 1071 |
tcg_temp_free(t0); |
|
| 1072 |
} |
|
| 1073 |
break; |
|
| 1033 |
mop = MO_UB; |
|
| 1034 |
goto do_store; |
|
| 1074 | 1035 |
|
| 1075 | 1036 |
case 0x37: /* l.sh */ |
| 1076 | 1037 |
LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
|
| 1038 |
mop = MO_TEUW; |
|
| 1039 |
goto do_store; |
|
| 1040 |
|
|
| 1041 |
do_store: |
|
| 1077 | 1042 |
{
|
| 1078 | 1043 |
TCGv t0 = tcg_temp_new(); |
| 1079 | 1044 |
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); |
| 1080 |
tcg_gen_qemu_st16(cpu_R[rb], t0, dc->mem_idx);
|
|
| 1045 |
tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
|
|
| 1081 | 1046 |
tcg_temp_free(t0); |
| 1082 | 1047 |
} |
| 1083 | 1048 |
break; |
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