root / hw / sun4m.c @ 563e3c6e
History | View | Annotate | Download (52.8 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU Sun4m & Sun4d & Sun4c System Emulator
|
| 3 |
*
|
| 4 |
* Copyright (c) 2003-2005 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "hw.h" |
| 25 |
#include "qemu-timer.h" |
| 26 |
#include "sun4m.h" |
| 27 |
#include "nvram.h" |
| 28 |
#include "sparc32_dma.h" |
| 29 |
#include "fdc.h" |
| 30 |
#include "sysemu.h" |
| 31 |
#include "net.h" |
| 32 |
#include "boards.h" |
| 33 |
#include "firmware_abi.h" |
| 34 |
#include "scsi.h" |
| 35 |
#include "pc.h" |
| 36 |
#include "isa.h" |
| 37 |
|
| 38 |
//#define DEBUG_IRQ
|
| 39 |
|
| 40 |
/*
|
| 41 |
* Sun4m architecture was used in the following machines:
|
| 42 |
*
|
| 43 |
* SPARCserver 6xxMP/xx
|
| 44 |
* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
|
| 45 |
* SPARCclassic X (4/10)
|
| 46 |
* SPARCstation LX/ZX (4/30)
|
| 47 |
* SPARCstation Voyager
|
| 48 |
* SPARCstation 10/xx, SPARCserver 10/xx
|
| 49 |
* SPARCstation 5, SPARCserver 5
|
| 50 |
* SPARCstation 20/xx, SPARCserver 20
|
| 51 |
* SPARCstation 4
|
| 52 |
*
|
| 53 |
* Sun4d architecture was used in the following machines:
|
| 54 |
*
|
| 55 |
* SPARCcenter 2000
|
| 56 |
* SPARCserver 1000
|
| 57 |
*
|
| 58 |
* Sun4c architecture was used in the following machines:
|
| 59 |
* SPARCstation 1/1+, SPARCserver 1/1+
|
| 60 |
* SPARCstation SLC
|
| 61 |
* SPARCstation IPC
|
| 62 |
* SPARCstation ELC
|
| 63 |
* SPARCstation IPX
|
| 64 |
*
|
| 65 |
* See for example: http://www.sunhelp.org/faq/sunref1.html
|
| 66 |
*/
|
| 67 |
|
| 68 |
#ifdef DEBUG_IRQ
|
| 69 |
#define DPRINTF(fmt, args...) \
|
| 70 |
do { printf("CPUIRQ: " fmt , ##args); } while (0) |
| 71 |
#else
|
| 72 |
#define DPRINTF(fmt, args...)
|
| 73 |
#endif
|
| 74 |
|
| 75 |
#define KERNEL_LOAD_ADDR 0x00004000 |
| 76 |
#define CMDLINE_ADDR 0x007ff000 |
| 77 |
#define INITRD_LOAD_ADDR 0x00800000 |
| 78 |
#define PROM_SIZE_MAX (512 * 1024) |
| 79 |
#define PROM_VADDR 0xffd00000 |
| 80 |
#define PROM_FILENAME "openbios-sparc32" |
| 81 |
|
| 82 |
// Control plane, 8-bit and 24-bit planes
|
| 83 |
#define TCX_SIZE (9 * 1024 * 1024) |
| 84 |
|
| 85 |
#define MAX_CPUS 16 |
| 86 |
#define MAX_PILS 16 |
| 87 |
|
| 88 |
struct hwdef {
|
| 89 |
target_phys_addr_t iommu_base, slavio_base; |
| 90 |
target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
| 91 |
target_phys_addr_t serial_base, fd_base; |
| 92 |
target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
| 93 |
target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
| 94 |
target_phys_addr_t ecc_base; |
| 95 |
uint32_t ecc_version; |
| 96 |
target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
| 97 |
long vram_size, nvram_size;
|
| 98 |
// IRQ numbers are not PIL ones, but master interrupt controller
|
| 99 |
// register bit numbers
|
| 100 |
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
|
| 101 |
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
|
| 102 |
int machine_id; // For NVRAM |
| 103 |
uint32_t iommu_version; |
| 104 |
uint32_t intbit_to_level[32];
|
| 105 |
uint64_t max_mem; |
| 106 |
const char * const default_cpu_model; |
| 107 |
}; |
| 108 |
|
| 109 |
#define MAX_IOUNITS 5 |
| 110 |
|
| 111 |
struct sun4d_hwdef {
|
| 112 |
target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
| 113 |
target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
| 114 |
target_phys_addr_t serial_base; |
| 115 |
target_phys_addr_t espdma_base, esp_base; |
| 116 |
target_phys_addr_t ledma_base, le_base; |
| 117 |
target_phys_addr_t tcx_base; |
| 118 |
target_phys_addr_t sbi_base; |
| 119 |
unsigned long vram_size, nvram_size; |
| 120 |
// IRQ numbers are not PIL ones, but SBI register bit numbers
|
| 121 |
int esp_irq, le_irq, clock_irq, clock1_irq;
|
| 122 |
int ser_irq, ms_kb_irq, me_irq;
|
| 123 |
int machine_id; // For NVRAM |
| 124 |
uint32_t iounit_version; |
| 125 |
uint64_t max_mem; |
| 126 |
const char * const default_cpu_model; |
| 127 |
}; |
| 128 |
|
| 129 |
int DMA_get_channel_mode (int nchan) |
| 130 |
{
|
| 131 |
return 0; |
| 132 |
} |
| 133 |
int DMA_read_memory (int nchan, void *buf, int pos, int size) |
| 134 |
{
|
| 135 |
return 0; |
| 136 |
} |
| 137 |
int DMA_write_memory (int nchan, void *buf, int pos, int size) |
| 138 |
{
|
| 139 |
return 0; |
| 140 |
} |
| 141 |
void DMA_hold_DREQ (int nchan) {} |
| 142 |
void DMA_release_DREQ (int nchan) {} |
| 143 |
void DMA_schedule(int nchan) {} |
| 144 |
void DMA_run (void) {} |
| 145 |
void DMA_init (int high_page_enable) {} |
| 146 |
void DMA_register_channel (int nchan, |
| 147 |
DMA_transfer_handler transfer_handler, |
| 148 |
void *opaque)
|
| 149 |
{
|
| 150 |
} |
| 151 |
|
| 152 |
static int nvram_boot_set(void *opaque, const char *boot_device) |
| 153 |
{
|
| 154 |
unsigned int i; |
| 155 |
uint8_t image[sizeof(ohwcfg_v3_t)];
|
| 156 |
ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
| 157 |
m48t59_t *nvram = (m48t59_t *)opaque; |
| 158 |
|
| 159 |
for (i = 0; i < sizeof(image); i++) |
| 160 |
image[i] = m48t59_read(nvram, i) & 0xff;
|
| 161 |
|
| 162 |
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
| 163 |
boot_device); |
| 164 |
header->nboot_devices = strlen(boot_device) & 0xff;
|
| 165 |
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
| 166 |
|
| 167 |
for (i = 0; i < sizeof(image); i++) |
| 168 |
m48t59_write(nvram, i, image[i]); |
| 169 |
|
| 170 |
return 0; |
| 171 |
} |
| 172 |
|
| 173 |
extern int nographic; |
| 174 |
|
| 175 |
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
| 176 |
const char *boot_devices, ram_addr_t RAM_size, |
| 177 |
uint32_t kernel_size, |
| 178 |
int width, int height, int depth, |
| 179 |
int machine_id, const char *arch) |
| 180 |
{
|
| 181 |
unsigned int i; |
| 182 |
uint32_t start, end; |
| 183 |
uint8_t image[0x1ff0];
|
| 184 |
ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
| 185 |
struct sparc_arch_cfg *sparc_header;
|
| 186 |
struct OpenBIOS_nvpart_v1 *part_header;
|
| 187 |
|
| 188 |
memset(image, '\0', sizeof(image)); |
| 189 |
|
| 190 |
// Try to match PPC NVRAM
|
| 191 |
pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
| 192 |
"QEMU_BIOS");
|
| 193 |
header->struct_version = cpu_to_be32(3); /* structure v3 */ |
| 194 |
|
| 195 |
header->nvram_size = cpu_to_be16(0x2000);
|
| 196 |
header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
|
| 197 |
header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
| 198 |
pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
| 199 |
header->nb_cpus = smp_cpus & 0xff;
|
| 200 |
header->RAM0_base = 0;
|
| 201 |
header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
| 202 |
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
| 203 |
boot_devices); |
| 204 |
header->nboot_devices = strlen(boot_devices) & 0xff;
|
| 205 |
header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
| 206 |
header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
| 207 |
if (cmdline) {
|
| 208 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
| 209 |
header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
| 210 |
header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
| 211 |
} |
| 212 |
// XXX add initrd_image, initrd_size
|
| 213 |
header->width = cpu_to_be16(width); |
| 214 |
header->height = cpu_to_be16(height); |
| 215 |
header->depth = cpu_to_be16(depth); |
| 216 |
if (nographic)
|
| 217 |
header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
| 218 |
|
| 219 |
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
| 220 |
|
| 221 |
// Architecture specific header
|
| 222 |
start = sizeof(ohwcfg_v3_t);
|
| 223 |
sparc_header = (struct sparc_arch_cfg *)&image[start];
|
| 224 |
sparc_header->valid = 0;
|
| 225 |
start += sizeof(struct sparc_arch_cfg); |
| 226 |
|
| 227 |
// OpenBIOS nvram variables
|
| 228 |
// Variable partition
|
| 229 |
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
| 230 |
part_header->signature = OPENBIOS_PART_SYSTEM; |
| 231 |
pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
| 232 |
|
| 233 |
end = start + sizeof(struct OpenBIOS_nvpart_v1); |
| 234 |
for (i = 0; i < nb_prom_envs; i++) |
| 235 |
end = OpenBIOS_set_var(image, end, prom_envs[i]); |
| 236 |
|
| 237 |
// End marker
|
| 238 |
image[end++] = '\0';
|
| 239 |
|
| 240 |
end = start + ((end - start + 15) & ~15); |
| 241 |
OpenBIOS_finish_partition(part_header, end - start); |
| 242 |
|
| 243 |
// free partition
|
| 244 |
start = end; |
| 245 |
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
| 246 |
part_header->signature = OPENBIOS_PART_FREE; |
| 247 |
pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
| 248 |
|
| 249 |
end = 0x1fd0;
|
| 250 |
OpenBIOS_finish_partition(part_header, end - start); |
| 251 |
|
| 252 |
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); |
| 253 |
|
| 254 |
for (i = 0; i < sizeof(image); i++) |
| 255 |
m48t59_write(nvram, i, image[i]); |
| 256 |
|
| 257 |
qemu_register_boot_set(nvram_boot_set, nvram); |
| 258 |
} |
| 259 |
|
| 260 |
static void *slavio_intctl; |
| 261 |
|
| 262 |
void pic_info(void) |
| 263 |
{
|
| 264 |
if (slavio_intctl)
|
| 265 |
slavio_pic_info(slavio_intctl); |
| 266 |
} |
| 267 |
|
| 268 |
void irq_info(void) |
| 269 |
{
|
| 270 |
if (slavio_intctl)
|
| 271 |
slavio_irq_info(slavio_intctl); |
| 272 |
} |
| 273 |
|
| 274 |
void cpu_check_irqs(CPUState *env)
|
| 275 |
{
|
| 276 |
if (env->pil_in && (env->interrupt_index == 0 || |
| 277 |
(env->interrupt_index & ~15) == TT_EXTINT)) {
|
| 278 |
unsigned int i; |
| 279 |
|
| 280 |
for (i = 15; i > 0; i--) { |
| 281 |
if (env->pil_in & (1 << i)) { |
| 282 |
int old_interrupt = env->interrupt_index;
|
| 283 |
|
| 284 |
env->interrupt_index = TT_EXTINT | i; |
| 285 |
if (old_interrupt != env->interrupt_index) {
|
| 286 |
DPRINTF("Set CPU IRQ %d\n", i);
|
| 287 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 288 |
} |
| 289 |
break;
|
| 290 |
} |
| 291 |
} |
| 292 |
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
| 293 |
DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
| 294 |
env->interrupt_index = 0;
|
| 295 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 296 |
} |
| 297 |
} |
| 298 |
|
| 299 |
static void cpu_set_irq(void *opaque, int irq, int level) |
| 300 |
{
|
| 301 |
CPUState *env = opaque; |
| 302 |
|
| 303 |
if (level) {
|
| 304 |
DPRINTF("Raise CPU IRQ %d\n", irq);
|
| 305 |
env->halted = 0;
|
| 306 |
env->pil_in |= 1 << irq;
|
| 307 |
cpu_check_irqs(env); |
| 308 |
} else {
|
| 309 |
DPRINTF("Lower CPU IRQ %d\n", irq);
|
| 310 |
env->pil_in &= ~(1 << irq);
|
| 311 |
cpu_check_irqs(env); |
| 312 |
} |
| 313 |
} |
| 314 |
|
| 315 |
static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
| 316 |
{
|
| 317 |
} |
| 318 |
|
| 319 |
static void *slavio_misc; |
| 320 |
|
| 321 |
void qemu_system_powerdown(void) |
| 322 |
{
|
| 323 |
slavio_set_power_fail(slavio_misc, 1);
|
| 324 |
} |
| 325 |
|
| 326 |
static void main_cpu_reset(void *opaque) |
| 327 |
{
|
| 328 |
CPUState *env = opaque; |
| 329 |
|
| 330 |
cpu_reset(env); |
| 331 |
env->halted = 0;
|
| 332 |
} |
| 333 |
|
| 334 |
static void secondary_cpu_reset(void *opaque) |
| 335 |
{
|
| 336 |
CPUState *env = opaque; |
| 337 |
|
| 338 |
cpu_reset(env); |
| 339 |
env->halted = 1;
|
| 340 |
} |
| 341 |
|
| 342 |
static unsigned long sun4m_load_kernel(const char *kernel_filename, |
| 343 |
const char *initrd_filename, |
| 344 |
ram_addr_t RAM_size) |
| 345 |
{
|
| 346 |
int linux_boot;
|
| 347 |
unsigned int i; |
| 348 |
long initrd_size, kernel_size;
|
| 349 |
|
| 350 |
linux_boot = (kernel_filename != NULL);
|
| 351 |
|
| 352 |
kernel_size = 0;
|
| 353 |
if (linux_boot) {
|
| 354 |
kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
| 355 |
NULL);
|
| 356 |
if (kernel_size < 0) |
| 357 |
kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
| 358 |
RAM_size - KERNEL_LOAD_ADDR); |
| 359 |
if (kernel_size < 0) |
| 360 |
kernel_size = load_image_targphys(kernel_filename, |
| 361 |
KERNEL_LOAD_ADDR, |
| 362 |
RAM_size - KERNEL_LOAD_ADDR); |
| 363 |
if (kernel_size < 0) { |
| 364 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
| 365 |
kernel_filename); |
| 366 |
exit(1);
|
| 367 |
} |
| 368 |
|
| 369 |
/* load initrd */
|
| 370 |
initrd_size = 0;
|
| 371 |
if (initrd_filename) {
|
| 372 |
initrd_size = load_image_targphys(initrd_filename, |
| 373 |
INITRD_LOAD_ADDR, |
| 374 |
RAM_size - INITRD_LOAD_ADDR); |
| 375 |
if (initrd_size < 0) { |
| 376 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
| 377 |
initrd_filename); |
| 378 |
exit(1);
|
| 379 |
} |
| 380 |
} |
| 381 |
if (initrd_size > 0) { |
| 382 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
| 383 |
if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
| 384 |
stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
| 385 |
stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
| 386 |
break;
|
| 387 |
} |
| 388 |
} |
| 389 |
} |
| 390 |
} |
| 391 |
return kernel_size;
|
| 392 |
} |
| 393 |
|
| 394 |
static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
| 395 |
const char *boot_device, |
| 396 |
DisplayState *ds, const char *kernel_filename, |
| 397 |
const char *kernel_cmdline, |
| 398 |
const char *initrd_filename, const char *cpu_model) |
| 399 |
|
| 400 |
{
|
| 401 |
CPUState *env, *envs[MAX_CPUS]; |
| 402 |
unsigned int i; |
| 403 |
void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
| 404 |
qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
| 405 |
*espdma_irq, *ledma_irq; |
| 406 |
qemu_irq *esp_reset, *le_reset; |
| 407 |
qemu_irq *fdc_tc; |
| 408 |
unsigned long prom_offset, kernel_size; |
| 409 |
int ret;
|
| 410 |
char buf[1024]; |
| 411 |
BlockDriverState *fd[MAX_FD]; |
| 412 |
int drive_index;
|
| 413 |
|
| 414 |
/* init CPUs */
|
| 415 |
if (!cpu_model)
|
| 416 |
cpu_model = hwdef->default_cpu_model; |
| 417 |
|
| 418 |
for(i = 0; i < smp_cpus; i++) { |
| 419 |
env = cpu_init(cpu_model); |
| 420 |
if (!env) {
|
| 421 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
| 422 |
exit(1);
|
| 423 |
} |
| 424 |
cpu_sparc_set_id(env, i); |
| 425 |
envs[i] = env; |
| 426 |
if (i == 0) { |
| 427 |
qemu_register_reset(main_cpu_reset, env); |
| 428 |
} else {
|
| 429 |
qemu_register_reset(secondary_cpu_reset, env); |
| 430 |
env->halted = 1;
|
| 431 |
} |
| 432 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
| 433 |
env->prom_addr = hwdef->slavio_base; |
| 434 |
} |
| 435 |
|
| 436 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
| 437 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
| 438 |
|
| 439 |
|
| 440 |
/* allocate RAM */
|
| 441 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
| 442 |
fprintf(stderr, |
| 443 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
| 444 |
(unsigned int)(RAM_size / (1024 * 1024)), |
| 445 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
| 446 |
exit(1);
|
| 447 |
} |
| 448 |
cpu_register_physical_memory(0, RAM_size, 0); |
| 449 |
|
| 450 |
/* load boot prom */
|
| 451 |
prom_offset = RAM_size + hwdef->vram_size; |
| 452 |
cpu_register_physical_memory(hwdef->slavio_base, |
| 453 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
| 454 |
TARGET_PAGE_MASK, |
| 455 |
prom_offset | IO_MEM_ROM); |
| 456 |
|
| 457 |
if (bios_name == NULL) |
| 458 |
bios_name = PROM_FILENAME; |
| 459 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
| 460 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
| 461 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
| 462 |
ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
| 463 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 464 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
| 465 |
buf); |
| 466 |
exit(1);
|
| 467 |
} |
| 468 |
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
| 469 |
|
| 470 |
/* set up devices */
|
| 471 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
| 472 |
hwdef->intctl_base + 0x10000ULL,
|
| 473 |
&hwdef->intbit_to_level[0],
|
| 474 |
&slavio_irq, &slavio_cpu_irq, |
| 475 |
cpu_irqs, |
| 476 |
hwdef->clock_irq); |
| 477 |
|
| 478 |
if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
| 479 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
| 480 |
|
| 481 |
cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
|
| 482 |
prom_offset | IO_MEM_ROM); |
| 483 |
cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data, |
| 484 |
sizeof(idreg_data));
|
| 485 |
} |
| 486 |
|
| 487 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
| 488 |
slavio_irq[hwdef->me_irq]); |
| 489 |
|
| 490 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
| 491 |
iommu, &espdma_irq, &esp_reset); |
| 492 |
|
| 493 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
| 494 |
slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
| 495 |
&le_reset); |
| 496 |
|
| 497 |
if (graphic_depth != 8 && graphic_depth != 24) { |
| 498 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
| 499 |
exit (1);
|
| 500 |
} |
| 501 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
| 502 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
| 503 |
|
| 504 |
if (nd_table[0].model == NULL |
| 505 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
| 506 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
| 507 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
| 508 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
| 509 |
exit (1);
|
| 510 |
} else {
|
| 511 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
| 512 |
exit (1);
|
| 513 |
} |
| 514 |
|
| 515 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
| 516 |
hwdef->nvram_size, 8);
|
| 517 |
|
| 518 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
| 519 |
slavio_cpu_irq, smp_cpus); |
| 520 |
|
| 521 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
| 522 |
nographic); |
| 523 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
| 524 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
| 525 |
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
| 526 |
serial_hds[1], serial_hds[0]); |
| 527 |
|
| 528 |
slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
| 529 |
hwdef->aux1_base, hwdef->aux2_base, |
| 530 |
slavio_irq[hwdef->me_irq], envs[0],
|
| 531 |
&fdc_tc); |
| 532 |
|
| 533 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
| 534 |
/* there is zero or one floppy drive */
|
| 535 |
memset(fd, 0, sizeof(fd)); |
| 536 |
drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
| 537 |
if (drive_index != -1) |
| 538 |
fd[0] = drives_table[drive_index].bdrv;
|
| 539 |
|
| 540 |
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
| 541 |
fdc_tc); |
| 542 |
} |
| 543 |
|
| 544 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
| 545 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
| 546 |
exit(1);
|
| 547 |
} |
| 548 |
|
| 549 |
main_esp = esp_init(hwdef->esp_base, 2,
|
| 550 |
espdma_memory_read, espdma_memory_write, |
| 551 |
espdma, *espdma_irq, esp_reset); |
| 552 |
|
| 553 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
| 554 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
| 555 |
if (drive_index == -1) |
| 556 |
continue;
|
| 557 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
| 558 |
} |
| 559 |
|
| 560 |
if (hwdef->cs_base != (target_phys_addr_t)-1) |
| 561 |
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
| 562 |
|
| 563 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
| 564 |
RAM_size); |
| 565 |
|
| 566 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
| 567 |
boot_device, RAM_size, kernel_size, graphic_width, |
| 568 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
|
| 569 |
|
| 570 |
if (hwdef->ecc_base != (target_phys_addr_t)-1) |
| 571 |
ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
| 572 |
hwdef->ecc_version); |
| 573 |
} |
| 574 |
|
| 575 |
static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
| 576 |
const char *boot_device, |
| 577 |
DisplayState *ds, const char *kernel_filename, |
| 578 |
const char *kernel_cmdline, |
| 579 |
const char *initrd_filename, const char *cpu_model) |
| 580 |
{
|
| 581 |
CPUState *env; |
| 582 |
unsigned int i; |
| 583 |
void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
| 584 |
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
| 585 |
qemu_irq *esp_reset, *le_reset; |
| 586 |
qemu_irq *fdc_tc; |
| 587 |
unsigned long prom_offset, kernel_size; |
| 588 |
int ret;
|
| 589 |
char buf[1024]; |
| 590 |
BlockDriverState *fd[MAX_FD]; |
| 591 |
int drive_index;
|
| 592 |
|
| 593 |
/* init CPU */
|
| 594 |
if (!cpu_model)
|
| 595 |
cpu_model = hwdef->default_cpu_model; |
| 596 |
|
| 597 |
env = cpu_init(cpu_model); |
| 598 |
if (!env) {
|
| 599 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
| 600 |
exit(1);
|
| 601 |
} |
| 602 |
|
| 603 |
cpu_sparc_set_id(env, 0);
|
| 604 |
|
| 605 |
qemu_register_reset(main_cpu_reset, env); |
| 606 |
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
| 607 |
env->prom_addr = hwdef->slavio_base; |
| 608 |
|
| 609 |
/* allocate RAM */
|
| 610 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
| 611 |
fprintf(stderr, |
| 612 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
| 613 |
(unsigned int)(RAM_size / (1024 * 1024)), |
| 614 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
| 615 |
exit(1);
|
| 616 |
} |
| 617 |
cpu_register_physical_memory(0, RAM_size, 0); |
| 618 |
|
| 619 |
/* load boot prom */
|
| 620 |
prom_offset = RAM_size + hwdef->vram_size; |
| 621 |
cpu_register_physical_memory(hwdef->slavio_base, |
| 622 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
| 623 |
TARGET_PAGE_MASK, |
| 624 |
prom_offset | IO_MEM_ROM); |
| 625 |
|
| 626 |
if (bios_name == NULL) |
| 627 |
bios_name = PROM_FILENAME; |
| 628 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
| 629 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
| 630 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
| 631 |
ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
| 632 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 633 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
| 634 |
buf); |
| 635 |
exit(1);
|
| 636 |
} |
| 637 |
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
| 638 |
|
| 639 |
/* set up devices */
|
| 640 |
slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, |
| 641 |
&slavio_irq, cpu_irqs); |
| 642 |
|
| 643 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
| 644 |
slavio_irq[hwdef->me_irq]); |
| 645 |
|
| 646 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
| 647 |
iommu, &espdma_irq, &esp_reset); |
| 648 |
|
| 649 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
| 650 |
slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
| 651 |
&le_reset); |
| 652 |
|
| 653 |
if (graphic_depth != 8 && graphic_depth != 24) { |
| 654 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
| 655 |
exit (1);
|
| 656 |
} |
| 657 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
| 658 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
| 659 |
|
| 660 |
if (nd_table[0].model == NULL |
| 661 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
| 662 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
| 663 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
| 664 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
| 665 |
exit (1);
|
| 666 |
} else {
|
| 667 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
| 668 |
exit (1);
|
| 669 |
} |
| 670 |
|
| 671 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
| 672 |
hwdef->nvram_size, 2);
|
| 673 |
|
| 674 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
| 675 |
nographic); |
| 676 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
| 677 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
| 678 |
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
| 679 |
serial_hds[1], serial_hds[0]); |
| 680 |
|
| 681 |
slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
|
| 682 |
hwdef->aux1_base, hwdef->aux2_base, |
| 683 |
slavio_irq[hwdef->me_irq], env, &fdc_tc); |
| 684 |
|
| 685 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
| 686 |
/* there is zero or one floppy drive */
|
| 687 |
fd[1] = fd[0] = NULL; |
| 688 |
drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
| 689 |
if (drive_index != -1) |
| 690 |
fd[0] = drives_table[drive_index].bdrv;
|
| 691 |
|
| 692 |
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
| 693 |
fdc_tc); |
| 694 |
} |
| 695 |
|
| 696 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
| 697 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
| 698 |
exit(1);
|
| 699 |
} |
| 700 |
|
| 701 |
main_esp = esp_init(hwdef->esp_base, 2,
|
| 702 |
espdma_memory_read, espdma_memory_write, |
| 703 |
espdma, *espdma_irq, esp_reset); |
| 704 |
|
| 705 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
| 706 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
| 707 |
if (drive_index == -1) |
| 708 |
continue;
|
| 709 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
| 710 |
} |
| 711 |
|
| 712 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
| 713 |
RAM_size); |
| 714 |
|
| 715 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
| 716 |
boot_device, RAM_size, kernel_size, graphic_width, |
| 717 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
|
| 718 |
} |
| 719 |
|
| 720 |
static const struct hwdef hwdefs[] = { |
| 721 |
/* SS-5 */
|
| 722 |
{
|
| 723 |
.iommu_base = 0x10000000,
|
| 724 |
.tcx_base = 0x50000000,
|
| 725 |
.cs_base = 0x6c000000,
|
| 726 |
.slavio_base = 0x70000000,
|
| 727 |
.ms_kb_base = 0x71000000,
|
| 728 |
.serial_base = 0x71100000,
|
| 729 |
.nvram_base = 0x71200000,
|
| 730 |
.fd_base = 0x71400000,
|
| 731 |
.counter_base = 0x71d00000,
|
| 732 |
.intctl_base = 0x71e00000,
|
| 733 |
.idreg_base = 0x78000000,
|
| 734 |
.dma_base = 0x78400000,
|
| 735 |
.esp_base = 0x78800000,
|
| 736 |
.le_base = 0x78c00000,
|
| 737 |
.apc_base = 0x6a000000,
|
| 738 |
.aux1_base = 0x71900000,
|
| 739 |
.aux2_base = 0x71910000,
|
| 740 |
.ecc_base = -1,
|
| 741 |
.sun4c_intctl_base = -1,
|
| 742 |
.sun4c_counter_base = -1,
|
| 743 |
.vram_size = 0x00100000,
|
| 744 |
.nvram_size = 0x2000,
|
| 745 |
.esp_irq = 18,
|
| 746 |
.le_irq = 16,
|
| 747 |
.clock_irq = 7,
|
| 748 |
.clock1_irq = 19,
|
| 749 |
.ms_kb_irq = 14,
|
| 750 |
.ser_irq = 15,
|
| 751 |
.fd_irq = 22,
|
| 752 |
.me_irq = 30,
|
| 753 |
.cs_irq = 5,
|
| 754 |
.machine_id = 0x80,
|
| 755 |
.iommu_version = 0x05000000,
|
| 756 |
.intbit_to_level = {
|
| 757 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 758 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 759 |
}, |
| 760 |
.max_mem = 0x10000000,
|
| 761 |
.default_cpu_model = "Fujitsu MB86904",
|
| 762 |
}, |
| 763 |
/* SS-10 */
|
| 764 |
{
|
| 765 |
.iommu_base = 0xfe0000000ULL,
|
| 766 |
.tcx_base = 0xe20000000ULL,
|
| 767 |
.cs_base = -1,
|
| 768 |
.slavio_base = 0xff0000000ULL,
|
| 769 |
.ms_kb_base = 0xff1000000ULL,
|
| 770 |
.serial_base = 0xff1100000ULL,
|
| 771 |
.nvram_base = 0xff1200000ULL,
|
| 772 |
.fd_base = 0xff1700000ULL,
|
| 773 |
.counter_base = 0xff1300000ULL,
|
| 774 |
.intctl_base = 0xff1400000ULL,
|
| 775 |
.idreg_base = 0xef0000000ULL,
|
| 776 |
.dma_base = 0xef0400000ULL,
|
| 777 |
.esp_base = 0xef0800000ULL,
|
| 778 |
.le_base = 0xef0c00000ULL,
|
| 779 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
| 780 |
.aux1_base = 0xff1800000ULL,
|
| 781 |
.aux2_base = 0xff1a01000ULL,
|
| 782 |
.ecc_base = 0xf00000000ULL,
|
| 783 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
| 784 |
.sun4c_intctl_base = -1,
|
| 785 |
.sun4c_counter_base = -1,
|
| 786 |
.vram_size = 0x00100000,
|
| 787 |
.nvram_size = 0x2000,
|
| 788 |
.esp_irq = 18,
|
| 789 |
.le_irq = 16,
|
| 790 |
.clock_irq = 7,
|
| 791 |
.clock1_irq = 19,
|
| 792 |
.ms_kb_irq = 14,
|
| 793 |
.ser_irq = 15,
|
| 794 |
.fd_irq = 22,
|
| 795 |
.me_irq = 30,
|
| 796 |
.cs_irq = -1,
|
| 797 |
.ecc_irq = 28,
|
| 798 |
.machine_id = 0x72,
|
| 799 |
.iommu_version = 0x03000000,
|
| 800 |
.intbit_to_level = {
|
| 801 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 802 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 803 |
}, |
| 804 |
.max_mem = 0xf00000000ULL,
|
| 805 |
.default_cpu_model = "TI SuperSparc II",
|
| 806 |
}, |
| 807 |
/* SS-600MP */
|
| 808 |
{
|
| 809 |
.iommu_base = 0xfe0000000ULL,
|
| 810 |
.tcx_base = 0xe20000000ULL,
|
| 811 |
.cs_base = -1,
|
| 812 |
.slavio_base = 0xff0000000ULL,
|
| 813 |
.ms_kb_base = 0xff1000000ULL,
|
| 814 |
.serial_base = 0xff1100000ULL,
|
| 815 |
.nvram_base = 0xff1200000ULL,
|
| 816 |
.fd_base = -1,
|
| 817 |
.counter_base = 0xff1300000ULL,
|
| 818 |
.intctl_base = 0xff1400000ULL,
|
| 819 |
.idreg_base = -1,
|
| 820 |
.dma_base = 0xef0081000ULL,
|
| 821 |
.esp_base = 0xef0080000ULL,
|
| 822 |
.le_base = 0xef0060000ULL,
|
| 823 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
| 824 |
.aux1_base = 0xff1800000ULL,
|
| 825 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
| 826 |
.ecc_base = 0xf00000000ULL,
|
| 827 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
| 828 |
.sun4c_intctl_base = -1,
|
| 829 |
.sun4c_counter_base = -1,
|
| 830 |
.vram_size = 0x00100000,
|
| 831 |
.nvram_size = 0x2000,
|
| 832 |
.esp_irq = 18,
|
| 833 |
.le_irq = 16,
|
| 834 |
.clock_irq = 7,
|
| 835 |
.clock1_irq = 19,
|
| 836 |
.ms_kb_irq = 14,
|
| 837 |
.ser_irq = 15,
|
| 838 |
.fd_irq = 22,
|
| 839 |
.me_irq = 30,
|
| 840 |
.cs_irq = -1,
|
| 841 |
.ecc_irq = 28,
|
| 842 |
.machine_id = 0x71,
|
| 843 |
.iommu_version = 0x01000000,
|
| 844 |
.intbit_to_level = {
|
| 845 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 846 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 847 |
}, |
| 848 |
.max_mem = 0xf00000000ULL,
|
| 849 |
.default_cpu_model = "TI SuperSparc II",
|
| 850 |
}, |
| 851 |
/* SS-20 */
|
| 852 |
{
|
| 853 |
.iommu_base = 0xfe0000000ULL,
|
| 854 |
.tcx_base = 0xe20000000ULL,
|
| 855 |
.cs_base = -1,
|
| 856 |
.slavio_base = 0xff0000000ULL,
|
| 857 |
.ms_kb_base = 0xff1000000ULL,
|
| 858 |
.serial_base = 0xff1100000ULL,
|
| 859 |
.nvram_base = 0xff1200000ULL,
|
| 860 |
.fd_base = 0xff1700000ULL,
|
| 861 |
.counter_base = 0xff1300000ULL,
|
| 862 |
.intctl_base = 0xff1400000ULL,
|
| 863 |
.idreg_base = 0xef0000000ULL,
|
| 864 |
.dma_base = 0xef0400000ULL,
|
| 865 |
.esp_base = 0xef0800000ULL,
|
| 866 |
.le_base = 0xef0c00000ULL,
|
| 867 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
| 868 |
.aux1_base = 0xff1800000ULL,
|
| 869 |
.aux2_base = 0xff1a01000ULL,
|
| 870 |
.ecc_base = 0xf00000000ULL,
|
| 871 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
| 872 |
.sun4c_intctl_base = -1,
|
| 873 |
.sun4c_counter_base = -1,
|
| 874 |
.vram_size = 0x00100000,
|
| 875 |
.nvram_size = 0x2000,
|
| 876 |
.esp_irq = 18,
|
| 877 |
.le_irq = 16,
|
| 878 |
.clock_irq = 7,
|
| 879 |
.clock1_irq = 19,
|
| 880 |
.ms_kb_irq = 14,
|
| 881 |
.ser_irq = 15,
|
| 882 |
.fd_irq = 22,
|
| 883 |
.me_irq = 30,
|
| 884 |
.cs_irq = -1,
|
| 885 |
.ecc_irq = 28,
|
| 886 |
.machine_id = 0x72,
|
| 887 |
.iommu_version = 0x13000000,
|
| 888 |
.intbit_to_level = {
|
| 889 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 890 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 891 |
}, |
| 892 |
.max_mem = 0xf00000000ULL,
|
| 893 |
.default_cpu_model = "TI SuperSparc II",
|
| 894 |
}, |
| 895 |
/* SS-2 */
|
| 896 |
{
|
| 897 |
.iommu_base = 0xf8000000,
|
| 898 |
.tcx_base = 0xfe000000,
|
| 899 |
.cs_base = -1,
|
| 900 |
.slavio_base = 0xf6000000,
|
| 901 |
.ms_kb_base = 0xf0000000,
|
| 902 |
.serial_base = 0xf1000000,
|
| 903 |
.nvram_base = 0xf2000000,
|
| 904 |
.fd_base = 0xf7200000,
|
| 905 |
.counter_base = -1,
|
| 906 |
.intctl_base = -1,
|
| 907 |
.dma_base = 0xf8400000,
|
| 908 |
.esp_base = 0xf8800000,
|
| 909 |
.le_base = 0xf8c00000,
|
| 910 |
.apc_base = -1,
|
| 911 |
.aux1_base = 0xf7400003,
|
| 912 |
.aux2_base = -1,
|
| 913 |
.sun4c_intctl_base = 0xf5000000,
|
| 914 |
.sun4c_counter_base = 0xf3000000,
|
| 915 |
.vram_size = 0x00100000,
|
| 916 |
.nvram_size = 0x800,
|
| 917 |
.esp_irq = 2,
|
| 918 |
.le_irq = 3,
|
| 919 |
.clock_irq = 5,
|
| 920 |
.clock1_irq = 7,
|
| 921 |
.ms_kb_irq = 1,
|
| 922 |
.ser_irq = 1,
|
| 923 |
.fd_irq = 1,
|
| 924 |
.me_irq = 1,
|
| 925 |
.cs_irq = -1,
|
| 926 |
.machine_id = 0x55,
|
| 927 |
.max_mem = 0x10000000,
|
| 928 |
.default_cpu_model = "Cypress CY7C601",
|
| 929 |
}, |
| 930 |
/* Voyager */
|
| 931 |
{
|
| 932 |
.iommu_base = 0x10000000,
|
| 933 |
.tcx_base = 0x50000000,
|
| 934 |
.cs_base = -1,
|
| 935 |
.slavio_base = 0x70000000,
|
| 936 |
.ms_kb_base = 0x71000000,
|
| 937 |
.serial_base = 0x71100000,
|
| 938 |
.nvram_base = 0x71200000,
|
| 939 |
.fd_base = 0x71400000,
|
| 940 |
.counter_base = 0x71d00000,
|
| 941 |
.intctl_base = 0x71e00000,
|
| 942 |
.idreg_base = 0x78000000,
|
| 943 |
.dma_base = 0x78400000,
|
| 944 |
.esp_base = 0x78800000,
|
| 945 |
.le_base = 0x78c00000,
|
| 946 |
.apc_base = 0x71300000, // pmc |
| 947 |
.aux1_base = 0x71900000,
|
| 948 |
.aux2_base = 0x71910000,
|
| 949 |
.ecc_base = -1,
|
| 950 |
.sun4c_intctl_base = -1,
|
| 951 |
.sun4c_counter_base = -1,
|
| 952 |
.vram_size = 0x00100000,
|
| 953 |
.nvram_size = 0x2000,
|
| 954 |
.esp_irq = 18,
|
| 955 |
.le_irq = 16,
|
| 956 |
.clock_irq = 7,
|
| 957 |
.clock1_irq = 19,
|
| 958 |
.ms_kb_irq = 14,
|
| 959 |
.ser_irq = 15,
|
| 960 |
.fd_irq = 22,
|
| 961 |
.me_irq = 30,
|
| 962 |
.cs_irq = -1,
|
| 963 |
.machine_id = 0x80,
|
| 964 |
.iommu_version = 0x05000000,
|
| 965 |
.intbit_to_level = {
|
| 966 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 967 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 968 |
}, |
| 969 |
.max_mem = 0x10000000,
|
| 970 |
.default_cpu_model = "Fujitsu MB86904",
|
| 971 |
}, |
| 972 |
/* LX */
|
| 973 |
{
|
| 974 |
.iommu_base = 0x10000000,
|
| 975 |
.tcx_base = 0x50000000,
|
| 976 |
.cs_base = -1,
|
| 977 |
.slavio_base = 0x70000000,
|
| 978 |
.ms_kb_base = 0x71000000,
|
| 979 |
.serial_base = 0x71100000,
|
| 980 |
.nvram_base = 0x71200000,
|
| 981 |
.fd_base = 0x71400000,
|
| 982 |
.counter_base = 0x71d00000,
|
| 983 |
.intctl_base = 0x71e00000,
|
| 984 |
.idreg_base = 0x78000000,
|
| 985 |
.dma_base = 0x78400000,
|
| 986 |
.esp_base = 0x78800000,
|
| 987 |
.le_base = 0x78c00000,
|
| 988 |
.apc_base = -1,
|
| 989 |
.aux1_base = 0x71900000,
|
| 990 |
.aux2_base = 0x71910000,
|
| 991 |
.ecc_base = -1,
|
| 992 |
.sun4c_intctl_base = -1,
|
| 993 |
.sun4c_counter_base = -1,
|
| 994 |
.vram_size = 0x00100000,
|
| 995 |
.nvram_size = 0x2000,
|
| 996 |
.esp_irq = 18,
|
| 997 |
.le_irq = 16,
|
| 998 |
.clock_irq = 7,
|
| 999 |
.clock1_irq = 19,
|
| 1000 |
.ms_kb_irq = 14,
|
| 1001 |
.ser_irq = 15,
|
| 1002 |
.fd_irq = 22,
|
| 1003 |
.me_irq = 30,
|
| 1004 |
.cs_irq = -1,
|
| 1005 |
.machine_id = 0x80,
|
| 1006 |
.iommu_version = 0x04000000,
|
| 1007 |
.intbit_to_level = {
|
| 1008 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 1009 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 1010 |
}, |
| 1011 |
.max_mem = 0x10000000,
|
| 1012 |
.default_cpu_model = "TI MicroSparc I",
|
| 1013 |
}, |
| 1014 |
/* SS-4 */
|
| 1015 |
{
|
| 1016 |
.iommu_base = 0x10000000,
|
| 1017 |
.tcx_base = 0x50000000,
|
| 1018 |
.cs_base = 0x6c000000,
|
| 1019 |
.slavio_base = 0x70000000,
|
| 1020 |
.ms_kb_base = 0x71000000,
|
| 1021 |
.serial_base = 0x71100000,
|
| 1022 |
.nvram_base = 0x71200000,
|
| 1023 |
.fd_base = 0x71400000,
|
| 1024 |
.counter_base = 0x71d00000,
|
| 1025 |
.intctl_base = 0x71e00000,
|
| 1026 |
.idreg_base = 0x78000000,
|
| 1027 |
.dma_base = 0x78400000,
|
| 1028 |
.esp_base = 0x78800000,
|
| 1029 |
.le_base = 0x78c00000,
|
| 1030 |
.apc_base = 0x6a000000,
|
| 1031 |
.aux1_base = 0x71900000,
|
| 1032 |
.aux2_base = 0x71910000,
|
| 1033 |
.ecc_base = -1,
|
| 1034 |
.sun4c_intctl_base = -1,
|
| 1035 |
.sun4c_counter_base = -1,
|
| 1036 |
.vram_size = 0x00100000,
|
| 1037 |
.nvram_size = 0x2000,
|
| 1038 |
.esp_irq = 18,
|
| 1039 |
.le_irq = 16,
|
| 1040 |
.clock_irq = 7,
|
| 1041 |
.clock1_irq = 19,
|
| 1042 |
.ms_kb_irq = 14,
|
| 1043 |
.ser_irq = 15,
|
| 1044 |
.fd_irq = 22,
|
| 1045 |
.me_irq = 30,
|
| 1046 |
.cs_irq = 5,
|
| 1047 |
.machine_id = 0x80,
|
| 1048 |
.iommu_version = 0x05000000,
|
| 1049 |
.intbit_to_level = {
|
| 1050 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 1051 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 1052 |
}, |
| 1053 |
.max_mem = 0x10000000,
|
| 1054 |
.default_cpu_model = "Fujitsu MB86904",
|
| 1055 |
}, |
| 1056 |
/* SPARCClassic */
|
| 1057 |
{
|
| 1058 |
.iommu_base = 0x10000000,
|
| 1059 |
.tcx_base = 0x50000000,
|
| 1060 |
.cs_base = -1,
|
| 1061 |
.slavio_base = 0x70000000,
|
| 1062 |
.ms_kb_base = 0x71000000,
|
| 1063 |
.serial_base = 0x71100000,
|
| 1064 |
.nvram_base = 0x71200000,
|
| 1065 |
.fd_base = 0x71400000,
|
| 1066 |
.counter_base = 0x71d00000,
|
| 1067 |
.intctl_base = 0x71e00000,
|
| 1068 |
.idreg_base = 0x78000000,
|
| 1069 |
.dma_base = 0x78400000,
|
| 1070 |
.esp_base = 0x78800000,
|
| 1071 |
.le_base = 0x78c00000,
|
| 1072 |
.apc_base = 0x6a000000,
|
| 1073 |
.aux1_base = 0x71900000,
|
| 1074 |
.aux2_base = 0x71910000,
|
| 1075 |
.ecc_base = -1,
|
| 1076 |
.sun4c_intctl_base = -1,
|
| 1077 |
.sun4c_counter_base = -1,
|
| 1078 |
.vram_size = 0x00100000,
|
| 1079 |
.nvram_size = 0x2000,
|
| 1080 |
.esp_irq = 18,
|
| 1081 |
.le_irq = 16,
|
| 1082 |
.clock_irq = 7,
|
| 1083 |
.clock1_irq = 19,
|
| 1084 |
.ms_kb_irq = 14,
|
| 1085 |
.ser_irq = 15,
|
| 1086 |
.fd_irq = 22,
|
| 1087 |
.me_irq = 30,
|
| 1088 |
.cs_irq = -1,
|
| 1089 |
.machine_id = 0x80,
|
| 1090 |
.iommu_version = 0x05000000,
|
| 1091 |
.intbit_to_level = {
|
| 1092 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 1093 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 1094 |
}, |
| 1095 |
.max_mem = 0x10000000,
|
| 1096 |
.default_cpu_model = "TI MicroSparc I",
|
| 1097 |
}, |
| 1098 |
/* SPARCbook */
|
| 1099 |
{
|
| 1100 |
.iommu_base = 0x10000000,
|
| 1101 |
.tcx_base = 0x50000000, // XXX |
| 1102 |
.cs_base = -1,
|
| 1103 |
.slavio_base = 0x70000000,
|
| 1104 |
.ms_kb_base = 0x71000000,
|
| 1105 |
.serial_base = 0x71100000,
|
| 1106 |
.nvram_base = 0x71200000,
|
| 1107 |
.fd_base = 0x71400000,
|
| 1108 |
.counter_base = 0x71d00000,
|
| 1109 |
.intctl_base = 0x71e00000,
|
| 1110 |
.idreg_base = 0x78000000,
|
| 1111 |
.dma_base = 0x78400000,
|
| 1112 |
.esp_base = 0x78800000,
|
| 1113 |
.le_base = 0x78c00000,
|
| 1114 |
.apc_base = 0x6a000000,
|
| 1115 |
.aux1_base = 0x71900000,
|
| 1116 |
.aux2_base = 0x71910000,
|
| 1117 |
.ecc_base = -1,
|
| 1118 |
.sun4c_intctl_base = -1,
|
| 1119 |
.sun4c_counter_base = -1,
|
| 1120 |
.vram_size = 0x00100000,
|
| 1121 |
.nvram_size = 0x2000,
|
| 1122 |
.esp_irq = 18,
|
| 1123 |
.le_irq = 16,
|
| 1124 |
.clock_irq = 7,
|
| 1125 |
.clock1_irq = 19,
|
| 1126 |
.ms_kb_irq = 14,
|
| 1127 |
.ser_irq = 15,
|
| 1128 |
.fd_irq = 22,
|
| 1129 |
.me_irq = 30,
|
| 1130 |
.cs_irq = -1,
|
| 1131 |
.machine_id = 0x80,
|
| 1132 |
.iommu_version = 0x05000000,
|
| 1133 |
.intbit_to_level = {
|
| 1134 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
| 1135 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
| 1136 |
}, |
| 1137 |
.max_mem = 0x10000000,
|
| 1138 |
.default_cpu_model = "TI MicroSparc I",
|
| 1139 |
}, |
| 1140 |
}; |
| 1141 |
|
| 1142 |
/* SPARCstation 5 hardware initialisation */
|
| 1143 |
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1144 |
const char *boot_device, DisplayState *ds, |
| 1145 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1146 |
const char *initrd_filename, const char *cpu_model) |
| 1147 |
{
|
| 1148 |
sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
| 1149 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1150 |
} |
| 1151 |
|
| 1152 |
/* SPARCstation 10 hardware initialisation */
|
| 1153 |
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1154 |
const char *boot_device, DisplayState *ds, |
| 1155 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1156 |
const char *initrd_filename, const char *cpu_model) |
| 1157 |
{
|
| 1158 |
sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
| 1159 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1160 |
} |
| 1161 |
|
| 1162 |
/* SPARCserver 600MP hardware initialisation */
|
| 1163 |
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1164 |
const char *boot_device, DisplayState *ds, |
| 1165 |
const char *kernel_filename, |
| 1166 |
const char *kernel_cmdline, |
| 1167 |
const char *initrd_filename, const char *cpu_model) |
| 1168 |
{
|
| 1169 |
sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
| 1170 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1171 |
} |
| 1172 |
|
| 1173 |
/* SPARCstation 20 hardware initialisation */
|
| 1174 |
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1175 |
const char *boot_device, DisplayState *ds, |
| 1176 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1177 |
const char *initrd_filename, const char *cpu_model) |
| 1178 |
{
|
| 1179 |
sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
| 1180 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1181 |
} |
| 1182 |
|
| 1183 |
/* SPARCstation 2 hardware initialisation */
|
| 1184 |
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1185 |
const char *boot_device, DisplayState *ds, |
| 1186 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1187 |
const char *initrd_filename, const char *cpu_model) |
| 1188 |
{
|
| 1189 |
sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
| 1190 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1191 |
} |
| 1192 |
|
| 1193 |
/* SPARCstation Voyager hardware initialisation */
|
| 1194 |
static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1195 |
const char *boot_device, DisplayState *ds, |
| 1196 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1197 |
const char *initrd_filename, const char *cpu_model) |
| 1198 |
{
|
| 1199 |
sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
| 1200 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1201 |
} |
| 1202 |
|
| 1203 |
/* SPARCstation LX hardware initialisation */
|
| 1204 |
static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1205 |
const char *boot_device, DisplayState *ds, |
| 1206 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1207 |
const char *initrd_filename, const char *cpu_model) |
| 1208 |
{
|
| 1209 |
sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
| 1210 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1211 |
} |
| 1212 |
|
| 1213 |
/* SPARCstation 4 hardware initialisation */
|
| 1214 |
static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1215 |
const char *boot_device, DisplayState *ds, |
| 1216 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1217 |
const char *initrd_filename, const char *cpu_model) |
| 1218 |
{
|
| 1219 |
sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
| 1220 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1221 |
} |
| 1222 |
|
| 1223 |
/* SPARCClassic hardware initialisation */
|
| 1224 |
static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1225 |
const char *boot_device, DisplayState *ds, |
| 1226 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1227 |
const char *initrd_filename, const char *cpu_model) |
| 1228 |
{
|
| 1229 |
sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
| 1230 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1231 |
} |
| 1232 |
|
| 1233 |
/* SPARCbook hardware initialisation */
|
| 1234 |
static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1235 |
const char *boot_device, DisplayState *ds, |
| 1236 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1237 |
const char *initrd_filename, const char *cpu_model) |
| 1238 |
{
|
| 1239 |
sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
| 1240 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1241 |
} |
| 1242 |
|
| 1243 |
QEMUMachine ss5_machine = {
|
| 1244 |
.name = "SS-5",
|
| 1245 |
.desc = "Sun4m platform, SPARCstation 5",
|
| 1246 |
.init = ss5_init, |
| 1247 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1248 |
.nodisk_ok = 1,
|
| 1249 |
}; |
| 1250 |
|
| 1251 |
QEMUMachine ss10_machine = {
|
| 1252 |
.name = "SS-10",
|
| 1253 |
.desc = "Sun4m platform, SPARCstation 10",
|
| 1254 |
.init = ss10_init, |
| 1255 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1256 |
.nodisk_ok = 1,
|
| 1257 |
}; |
| 1258 |
|
| 1259 |
QEMUMachine ss600mp_machine = {
|
| 1260 |
.name = "SS-600MP",
|
| 1261 |
.desc = "Sun4m platform, SPARCserver 600MP",
|
| 1262 |
.init = ss600mp_init, |
| 1263 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1264 |
.nodisk_ok = 1,
|
| 1265 |
}; |
| 1266 |
|
| 1267 |
QEMUMachine ss20_machine = {
|
| 1268 |
.name = "SS-20",
|
| 1269 |
.desc = "Sun4m platform, SPARCstation 20",
|
| 1270 |
.init = ss20_init, |
| 1271 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1272 |
.nodisk_ok = 1,
|
| 1273 |
}; |
| 1274 |
|
| 1275 |
QEMUMachine ss2_machine = {
|
| 1276 |
.name = "SS-2",
|
| 1277 |
.desc = "Sun4c platform, SPARCstation 2",
|
| 1278 |
.init = ss2_init, |
| 1279 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1280 |
.nodisk_ok = 1,
|
| 1281 |
}; |
| 1282 |
|
| 1283 |
QEMUMachine voyager_machine = {
|
| 1284 |
.name = "Voyager",
|
| 1285 |
.desc = "Sun4m platform, SPARCstation Voyager",
|
| 1286 |
.init = vger_init, |
| 1287 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1288 |
.nodisk_ok = 1,
|
| 1289 |
}; |
| 1290 |
|
| 1291 |
QEMUMachine ss_lx_machine = {
|
| 1292 |
.name = "LX",
|
| 1293 |
.desc = "Sun4m platform, SPARCstation LX",
|
| 1294 |
.init = ss_lx_init, |
| 1295 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1296 |
.nodisk_ok = 1,
|
| 1297 |
}; |
| 1298 |
|
| 1299 |
QEMUMachine ss4_machine = {
|
| 1300 |
.name = "SS-4",
|
| 1301 |
.desc = "Sun4m platform, SPARCstation 4",
|
| 1302 |
.init = ss4_init, |
| 1303 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1304 |
.nodisk_ok = 1,
|
| 1305 |
}; |
| 1306 |
|
| 1307 |
QEMUMachine scls_machine = {
|
| 1308 |
.name = "SPARCClassic",
|
| 1309 |
.desc = "Sun4m platform, SPARCClassic",
|
| 1310 |
.init = scls_init, |
| 1311 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1312 |
.nodisk_ok = 1,
|
| 1313 |
}; |
| 1314 |
|
| 1315 |
QEMUMachine sbook_machine = {
|
| 1316 |
.name = "SPARCbook",
|
| 1317 |
.desc = "Sun4m platform, SPARCbook",
|
| 1318 |
.init = sbook_init, |
| 1319 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1320 |
.nodisk_ok = 1,
|
| 1321 |
}; |
| 1322 |
|
| 1323 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
| 1324 |
/* SS-1000 */
|
| 1325 |
{
|
| 1326 |
.iounit_bases = {
|
| 1327 |
0xfe0200000ULL,
|
| 1328 |
0xfe1200000ULL,
|
| 1329 |
0xfe2200000ULL,
|
| 1330 |
0xfe3200000ULL,
|
| 1331 |
-1,
|
| 1332 |
}, |
| 1333 |
.tcx_base = 0x820000000ULL,
|
| 1334 |
.slavio_base = 0xf00000000ULL,
|
| 1335 |
.ms_kb_base = 0xf00240000ULL,
|
| 1336 |
.serial_base = 0xf00200000ULL,
|
| 1337 |
.nvram_base = 0xf00280000ULL,
|
| 1338 |
.counter_base = 0xf00300000ULL,
|
| 1339 |
.espdma_base = 0x800081000ULL,
|
| 1340 |
.esp_base = 0x800080000ULL,
|
| 1341 |
.ledma_base = 0x800040000ULL,
|
| 1342 |
.le_base = 0x800060000ULL,
|
| 1343 |
.sbi_base = 0xf02800000ULL,
|
| 1344 |
.vram_size = 0x00100000,
|
| 1345 |
.nvram_size = 0x2000,
|
| 1346 |
.esp_irq = 3,
|
| 1347 |
.le_irq = 4,
|
| 1348 |
.clock_irq = 14,
|
| 1349 |
.clock1_irq = 10,
|
| 1350 |
.ms_kb_irq = 12,
|
| 1351 |
.ser_irq = 12,
|
| 1352 |
.machine_id = 0x80,
|
| 1353 |
.iounit_version = 0x03000000,
|
| 1354 |
.max_mem = 0xf00000000ULL,
|
| 1355 |
.default_cpu_model = "TI SuperSparc II",
|
| 1356 |
}, |
| 1357 |
/* SS-2000 */
|
| 1358 |
{
|
| 1359 |
.iounit_bases = {
|
| 1360 |
0xfe0200000ULL,
|
| 1361 |
0xfe1200000ULL,
|
| 1362 |
0xfe2200000ULL,
|
| 1363 |
0xfe3200000ULL,
|
| 1364 |
0xfe4200000ULL,
|
| 1365 |
}, |
| 1366 |
.tcx_base = 0x820000000ULL,
|
| 1367 |
.slavio_base = 0xf00000000ULL,
|
| 1368 |
.ms_kb_base = 0xf00240000ULL,
|
| 1369 |
.serial_base = 0xf00200000ULL,
|
| 1370 |
.nvram_base = 0xf00280000ULL,
|
| 1371 |
.counter_base = 0xf00300000ULL,
|
| 1372 |
.espdma_base = 0x800081000ULL,
|
| 1373 |
.esp_base = 0x800080000ULL,
|
| 1374 |
.ledma_base = 0x800040000ULL,
|
| 1375 |
.le_base = 0x800060000ULL,
|
| 1376 |
.sbi_base = 0xf02800000ULL,
|
| 1377 |
.vram_size = 0x00100000,
|
| 1378 |
.nvram_size = 0x2000,
|
| 1379 |
.esp_irq = 3,
|
| 1380 |
.le_irq = 4,
|
| 1381 |
.clock_irq = 14,
|
| 1382 |
.clock1_irq = 10,
|
| 1383 |
.ms_kb_irq = 12,
|
| 1384 |
.ser_irq = 12,
|
| 1385 |
.machine_id = 0x80,
|
| 1386 |
.iounit_version = 0x03000000,
|
| 1387 |
.max_mem = 0xf00000000ULL,
|
| 1388 |
.default_cpu_model = "TI SuperSparc II",
|
| 1389 |
}, |
| 1390 |
}; |
| 1391 |
|
| 1392 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
| 1393 |
const char *boot_device, |
| 1394 |
DisplayState *ds, const char *kernel_filename, |
| 1395 |
const char *kernel_cmdline, |
| 1396 |
const char *initrd_filename, const char *cpu_model) |
| 1397 |
{
|
| 1398 |
CPUState *env, *envs[MAX_CPUS]; |
| 1399 |
unsigned int i; |
| 1400 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
| 1401 |
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
| 1402 |
*espdma_irq, *ledma_irq; |
| 1403 |
qemu_irq *esp_reset, *le_reset; |
| 1404 |
unsigned long prom_offset, kernel_size; |
| 1405 |
int ret;
|
| 1406 |
char buf[1024]; |
| 1407 |
int drive_index;
|
| 1408 |
|
| 1409 |
/* init CPUs */
|
| 1410 |
if (!cpu_model)
|
| 1411 |
cpu_model = hwdef->default_cpu_model; |
| 1412 |
|
| 1413 |
for (i = 0; i < smp_cpus; i++) { |
| 1414 |
env = cpu_init(cpu_model); |
| 1415 |
if (!env) {
|
| 1416 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
| 1417 |
exit(1);
|
| 1418 |
} |
| 1419 |
cpu_sparc_set_id(env, i); |
| 1420 |
envs[i] = env; |
| 1421 |
if (i == 0) { |
| 1422 |
qemu_register_reset(main_cpu_reset, env); |
| 1423 |
} else {
|
| 1424 |
qemu_register_reset(secondary_cpu_reset, env); |
| 1425 |
env->halted = 1;
|
| 1426 |
} |
| 1427 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
| 1428 |
env->prom_addr = hwdef->slavio_base; |
| 1429 |
} |
| 1430 |
|
| 1431 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
| 1432 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
| 1433 |
|
| 1434 |
/* allocate RAM */
|
| 1435 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
| 1436 |
fprintf(stderr, |
| 1437 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
| 1438 |
(unsigned int)(RAM_size / (1024 * 1024)), |
| 1439 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
| 1440 |
exit(1);
|
| 1441 |
} |
| 1442 |
cpu_register_physical_memory(0, RAM_size, 0); |
| 1443 |
|
| 1444 |
/* load boot prom */
|
| 1445 |
prom_offset = RAM_size + hwdef->vram_size; |
| 1446 |
cpu_register_physical_memory(hwdef->slavio_base, |
| 1447 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
| 1448 |
TARGET_PAGE_MASK, |
| 1449 |
prom_offset | IO_MEM_ROM); |
| 1450 |
|
| 1451 |
if (bios_name == NULL) |
| 1452 |
bios_name = PROM_FILENAME; |
| 1453 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
| 1454 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
| 1455 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
| 1456 |
ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
| 1457 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 1458 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
| 1459 |
buf); |
| 1460 |
exit(1);
|
| 1461 |
} |
| 1462 |
|
| 1463 |
/* set up devices */
|
| 1464 |
sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
| 1465 |
|
| 1466 |
for (i = 0; i < MAX_IOUNITS; i++) |
| 1467 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
| 1468 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
| 1469 |
hwdef->iounit_version, |
| 1470 |
sbi_irq[hwdef->me_irq]); |
| 1471 |
|
| 1472 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
| 1473 |
iounits[0], &espdma_irq, &esp_reset);
|
| 1474 |
|
| 1475 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
| 1476 |
iounits[0], &ledma_irq, &le_reset);
|
| 1477 |
|
| 1478 |
if (graphic_depth != 8 && graphic_depth != 24) { |
| 1479 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
| 1480 |
exit (1);
|
| 1481 |
} |
| 1482 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
| 1483 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
| 1484 |
|
| 1485 |
if (nd_table[0].model == NULL |
| 1486 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
| 1487 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
| 1488 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
| 1489 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
| 1490 |
exit (1);
|
| 1491 |
} else {
|
| 1492 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
| 1493 |
exit (1);
|
| 1494 |
} |
| 1495 |
|
| 1496 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
| 1497 |
hwdef->nvram_size, 8);
|
| 1498 |
|
| 1499 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
| 1500 |
sbi_cpu_irq, smp_cpus); |
| 1501 |
|
| 1502 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
| 1503 |
nographic); |
| 1504 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
| 1505 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
| 1506 |
slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
| 1507 |
serial_hds[1], serial_hds[0]); |
| 1508 |
|
| 1509 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
| 1510 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
| 1511 |
exit(1);
|
| 1512 |
} |
| 1513 |
|
| 1514 |
main_esp = esp_init(hwdef->esp_base, 2,
|
| 1515 |
espdma_memory_read, espdma_memory_write, |
| 1516 |
espdma, *espdma_irq, esp_reset); |
| 1517 |
|
| 1518 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
| 1519 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
| 1520 |
if (drive_index == -1) |
| 1521 |
continue;
|
| 1522 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
| 1523 |
} |
| 1524 |
|
| 1525 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
| 1526 |
RAM_size); |
| 1527 |
|
| 1528 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
| 1529 |
boot_device, RAM_size, kernel_size, graphic_width, |
| 1530 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
|
| 1531 |
} |
| 1532 |
|
| 1533 |
/* SPARCserver 1000 hardware initialisation */
|
| 1534 |
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1535 |
const char *boot_device, DisplayState *ds, |
| 1536 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1537 |
const char *initrd_filename, const char *cpu_model) |
| 1538 |
{
|
| 1539 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
| 1540 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1541 |
} |
| 1542 |
|
| 1543 |
/* SPARCcenter 2000 hardware initialisation */
|
| 1544 |
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
| 1545 |
const char *boot_device, DisplayState *ds, |
| 1546 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1547 |
const char *initrd_filename, const char *cpu_model) |
| 1548 |
{
|
| 1549 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
| 1550 |
kernel_cmdline, initrd_filename, cpu_model); |
| 1551 |
} |
| 1552 |
|
| 1553 |
QEMUMachine ss1000_machine = {
|
| 1554 |
.name = "SS-1000",
|
| 1555 |
.desc = "Sun4d platform, SPARCserver 1000",
|
| 1556 |
.init = ss1000_init, |
| 1557 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1558 |
.nodisk_ok = 1,
|
| 1559 |
}; |
| 1560 |
|
| 1561 |
QEMUMachine ss2000_machine = {
|
| 1562 |
.name = "SS-2000",
|
| 1563 |
.desc = "Sun4d platform, SPARCcenter 2000",
|
| 1564 |
.init = ss2000_init, |
| 1565 |
.ram_require = PROM_SIZE_MAX + TCX_SIZE, |
| 1566 |
.nodisk_ok = 1,
|
| 1567 |
}; |