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1 | 3ef693a0 | bellard | /*
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2 | 3ef693a0 | bellard | * i386 virtual CPU header
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3 | 3ef693a0 | bellard | *
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4 | 3ef693a0 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 3ef693a0 | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 3ef693a0 | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 3ef693a0 | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 0ecfa993 | bellard | */
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20 | 367e86e8 | bellard | #ifndef CPU_I386_H
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21 | 367e86e8 | bellard | #define CPU_I386_H
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22 | 367e86e8 | bellard | |
23 | 04369ff2 | bellard | #include "config.h" |
24 | 0ecfa993 | bellard | #include <setjmp.h> |
25 | 0ecfa993 | bellard | |
26 | 367e86e8 | bellard | #define R_EAX 0 |
27 | 367e86e8 | bellard | #define R_ECX 1 |
28 | 367e86e8 | bellard | #define R_EDX 2 |
29 | 367e86e8 | bellard | #define R_EBX 3 |
30 | 367e86e8 | bellard | #define R_ESP 4 |
31 | 367e86e8 | bellard | #define R_EBP 5 |
32 | 367e86e8 | bellard | #define R_ESI 6 |
33 | 367e86e8 | bellard | #define R_EDI 7 |
34 | 367e86e8 | bellard | |
35 | 367e86e8 | bellard | #define R_AL 0 |
36 | 367e86e8 | bellard | #define R_CL 1 |
37 | 367e86e8 | bellard | #define R_DL 2 |
38 | 367e86e8 | bellard | #define R_BL 3 |
39 | 367e86e8 | bellard | #define R_AH 4 |
40 | 367e86e8 | bellard | #define R_CH 5 |
41 | 367e86e8 | bellard | #define R_DH 6 |
42 | 367e86e8 | bellard | #define R_BH 7 |
43 | 367e86e8 | bellard | |
44 | 367e86e8 | bellard | #define R_ES 0 |
45 | 367e86e8 | bellard | #define R_CS 1 |
46 | 367e86e8 | bellard | #define R_SS 2 |
47 | 367e86e8 | bellard | #define R_DS 3 |
48 | 367e86e8 | bellard | #define R_FS 4 |
49 | 367e86e8 | bellard | #define R_GS 5 |
50 | 367e86e8 | bellard | |
51 | fc2b4c48 | bellard | /* eflags masks */
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52 | 367e86e8 | bellard | #define CC_C 0x0001 |
53 | 367e86e8 | bellard | #define CC_P 0x0004 |
54 | 367e86e8 | bellard | #define CC_A 0x0010 |
55 | 367e86e8 | bellard | #define CC_Z 0x0040 |
56 | 367e86e8 | bellard | #define CC_S 0x0080 |
57 | 367e86e8 | bellard | #define CC_O 0x0800 |
58 | 367e86e8 | bellard | |
59 | fc2b4c48 | bellard | #define TF_MASK 0x00000100 |
60 | fc2b4c48 | bellard | #define IF_MASK 0x00000200 |
61 | fc2b4c48 | bellard | #define DF_MASK 0x00000400 |
62 | fc2b4c48 | bellard | #define IOPL_MASK 0x00003000 |
63 | fc2b4c48 | bellard | #define NT_MASK 0x00004000 |
64 | fc2b4c48 | bellard | #define RF_MASK 0x00010000 |
65 | fc2b4c48 | bellard | #define VM_MASK 0x00020000 |
66 | fc2b4c48 | bellard | #define AC_MASK 0x00040000 |
67 | fc2b4c48 | bellard | #define VIF_MASK 0x00080000 |
68 | fc2b4c48 | bellard | #define VIP_MASK 0x00100000 |
69 | fc2b4c48 | bellard | #define ID_MASK 0x00200000 |
70 | 367e86e8 | bellard | |
71 | bc8a22cc | bellard | #define EXCP00_DIVZ 0 |
72 | bc8a22cc | bellard | #define EXCP01_SSTP 1 |
73 | bc8a22cc | bellard | #define EXCP02_NMI 2 |
74 | bc8a22cc | bellard | #define EXCP03_INT3 3 |
75 | bc8a22cc | bellard | #define EXCP04_INTO 4 |
76 | bc8a22cc | bellard | #define EXCP05_BOUND 5 |
77 | bc8a22cc | bellard | #define EXCP06_ILLOP 6 |
78 | bc8a22cc | bellard | #define EXCP07_PREX 7 |
79 | bc8a22cc | bellard | #define EXCP08_DBLE 8 |
80 | bc8a22cc | bellard | #define EXCP09_XERR 9 |
81 | bc8a22cc | bellard | #define EXCP0A_TSS 10 |
82 | bc8a22cc | bellard | #define EXCP0B_NOSEG 11 |
83 | bc8a22cc | bellard | #define EXCP0C_STACK 12 |
84 | bc8a22cc | bellard | #define EXCP0D_GPF 13 |
85 | bc8a22cc | bellard | #define EXCP0E_PAGE 14 |
86 | bc8a22cc | bellard | #define EXCP10_COPR 16 |
87 | bc8a22cc | bellard | #define EXCP11_ALGN 17 |
88 | bc8a22cc | bellard | #define EXCP12_MCHK 18 |
89 | 0ecfa993 | bellard | |
90 | 9de5e440 | bellard | #define EXCP_INTERRUPT 256 /* async interruption */ |
91 | 0ecfa993 | bellard | |
92 | 367e86e8 | bellard | enum {
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93 | 367e86e8 | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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94 | 367e86e8 | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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95 | 367e86e8 | bellard | CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
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96 | 367e86e8 | bellard | |
97 | 367e86e8 | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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98 | 367e86e8 | bellard | CC_OP_ADDW, |
99 | 367e86e8 | bellard | CC_OP_ADDL, |
100 | 367e86e8 | bellard | |
101 | 4b74fe1f | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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102 | 4b74fe1f | bellard | CC_OP_ADCW, |
103 | 4b74fe1f | bellard | CC_OP_ADCL, |
104 | 4b74fe1f | bellard | |
105 | 367e86e8 | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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106 | 367e86e8 | bellard | CC_OP_SUBW, |
107 | 367e86e8 | bellard | CC_OP_SUBL, |
108 | 367e86e8 | bellard | |
109 | 4b74fe1f | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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110 | 4b74fe1f | bellard | CC_OP_SBBW, |
111 | 4b74fe1f | bellard | CC_OP_SBBL, |
112 | 4b74fe1f | bellard | |
113 | 367e86e8 | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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114 | 367e86e8 | bellard | CC_OP_LOGICW, |
115 | 367e86e8 | bellard | CC_OP_LOGICL, |
116 | 367e86e8 | bellard | |
117 | 4b74fe1f | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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118 | 367e86e8 | bellard | CC_OP_INCW, |
119 | 367e86e8 | bellard | CC_OP_INCL, |
120 | 367e86e8 | bellard | |
121 | 4b74fe1f | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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122 | 367e86e8 | bellard | CC_OP_DECW, |
123 | 367e86e8 | bellard | CC_OP_DECL, |
124 | 367e86e8 | bellard | |
125 | 367e86e8 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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126 | 367e86e8 | bellard | CC_OP_SHLW, |
127 | 367e86e8 | bellard | CC_OP_SHLL, |
128 | 367e86e8 | bellard | |
129 | 4b74fe1f | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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130 | 4b74fe1f | bellard | CC_OP_SARW, |
131 | 4b74fe1f | bellard | CC_OP_SARL, |
132 | 4b74fe1f | bellard | |
133 | 367e86e8 | bellard | CC_OP_NB, |
134 | 367e86e8 | bellard | }; |
135 | 367e86e8 | bellard | |
136 | 927f621e | bellard | #ifdef __i386__
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137 | 27362c82 | bellard | #define USE_X86LDOUBLE
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138 | 927f621e | bellard | #endif
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139 | 927f621e | bellard | |
140 | 927f621e | bellard | #ifdef USE_X86LDOUBLE
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141 | 927f621e | bellard | typedef long double CPU86_LDouble; |
142 | 927f621e | bellard | #else
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143 | 927f621e | bellard | typedef double CPU86_LDouble; |
144 | 927f621e | bellard | #endif
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145 | 927f621e | bellard | |
146 | 6dbad63e | bellard | typedef struct SegmentCache { |
147 | 6dbad63e | bellard | uint8_t *base; |
148 | 6dbad63e | bellard | unsigned long limit; |
149 | 6dbad63e | bellard | uint8_t seg_32bit; |
150 | 6dbad63e | bellard | } SegmentCache; |
151 | 6dbad63e | bellard | |
152 | 6dbad63e | bellard | typedef struct SegmentDescriptorTable { |
153 | 6dbad63e | bellard | uint8_t *base; |
154 | 6dbad63e | bellard | unsigned long limit; |
155 | 6dbad63e | bellard | /* this is the returned base when reading the register, just to
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156 | 6dbad63e | bellard | avoid that the emulated program modifies it */
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157 | 6dbad63e | bellard | unsigned long emu_base; |
158 | 6dbad63e | bellard | } SegmentDescriptorTable; |
159 | 6dbad63e | bellard | |
160 | ba1c6e37 | bellard | typedef struct CPUX86State { |
161 | 367e86e8 | bellard | /* standard registers */
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162 | 367e86e8 | bellard | uint32_t regs[8];
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163 | dab2ed99 | bellard | uint32_t eip; |
164 | fc2b4c48 | bellard | uint32_t eflags; /* eflags register. During CPU emulation, CC
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165 | fc2b4c48 | bellard | flags and DF are set to zero because they are
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166 | d34720fd | bellard | stored elsewhere */
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167 | 0ecfa993 | bellard | |
168 | 0ecfa993 | bellard | /* emulator internal eflags handling */
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169 | 367e86e8 | bellard | uint32_t cc_src; |
170 | 367e86e8 | bellard | uint32_t cc_dst; |
171 | 367e86e8 | bellard | uint32_t cc_op; |
172 | 367e86e8 | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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173 | 0ecfa993 | bellard | |
174 | 927f621e | bellard | /* FPU state */
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175 | 927f621e | bellard | unsigned int fpstt; /* top of stack index */ |
176 | 927f621e | bellard | unsigned int fpus; |
177 | 927f621e | bellard | unsigned int fpuc; |
178 | 0ecfa993 | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
179 | 0ecfa993 | bellard | CPU86_LDouble fpregs[8];
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180 | 0ecfa993 | bellard | |
181 | 367e86e8 | bellard | /* emulator internal variables */
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182 | 927f621e | bellard | CPU86_LDouble ft0; |
183 | d014c98c | bellard | union {
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184 | d014c98c | bellard | float f;
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185 | d014c98c | bellard | double d;
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186 | d014c98c | bellard | int i32;
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187 | d014c98c | bellard | int64_t i64; |
188 | d014c98c | bellard | } fp_convert; |
189 | d57c4e01 | bellard | |
190 | 6dbad63e | bellard | /* segments */
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191 | 6dbad63e | bellard | uint32_t segs[6]; /* selector values */ |
192 | 6dbad63e | bellard | SegmentCache seg_cache[6]; /* info taken from LDT/GDT */ |
193 | 6dbad63e | bellard | SegmentDescriptorTable gdt; |
194 | 6dbad63e | bellard | SegmentDescriptorTable ldt; |
195 | 6dbad63e | bellard | SegmentDescriptorTable idt; |
196 | 6dbad63e | bellard | |
197 | 9de5e440 | bellard | /* exception/interrupt handling */
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198 | 0ecfa993 | bellard | jmp_buf jmp_env; |
199 | 0ecfa993 | bellard | int exception_index;
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200 | 9ba5695c | bellard | int error_code;
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201 | 9ba5695c | bellard | uint32_t cr2; |
202 | 9de5e440 | bellard | int interrupt_request;
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203 | fc2b4c48 | bellard | |
204 | fc2b4c48 | bellard | /* user data */
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205 | fc2b4c48 | bellard | void *opaque;
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206 | ba1c6e37 | bellard | } CPUX86State; |
207 | 367e86e8 | bellard | |
208 | 04369ff2 | bellard | /* all CPU memory access use these macros */
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209 | 367e86e8 | bellard | static inline int ldub(void *ptr) |
210 | 367e86e8 | bellard | { |
211 | 367e86e8 | bellard | return *(uint8_t *)ptr;
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212 | 367e86e8 | bellard | } |
213 | 367e86e8 | bellard | |
214 | 367e86e8 | bellard | static inline int ldsb(void *ptr) |
215 | 367e86e8 | bellard | { |
216 | 367e86e8 | bellard | return *(int8_t *)ptr;
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217 | 367e86e8 | bellard | } |
218 | 367e86e8 | bellard | |
219 | 04369ff2 | bellard | static inline void stb(void *ptr, int v) |
220 | 04369ff2 | bellard | { |
221 | 04369ff2 | bellard | *(uint8_t *)ptr = v; |
222 | 04369ff2 | bellard | } |
223 | 04369ff2 | bellard | |
224 | 04369ff2 | bellard | #ifdef WORDS_BIGENDIAN
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225 | 04369ff2 | bellard | |
226 | 04369ff2 | bellard | /* conservative code for little endian unaligned accesses */
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227 | 04369ff2 | bellard | static inline int lduw(void *ptr) |
228 | 04369ff2 | bellard | { |
229 | 04369ff2 | bellard | #ifdef __powerpc__
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230 | 04369ff2 | bellard | int val;
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231 | 04369ff2 | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
232 | 04369ff2 | bellard | return val;
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233 | 04369ff2 | bellard | #else
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234 | 04369ff2 | bellard | uint8_t *p = ptr; |
235 | 04369ff2 | bellard | return p[0] | (p[1] << 8); |
236 | 04369ff2 | bellard | #endif
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237 | 04369ff2 | bellard | } |
238 | 04369ff2 | bellard | |
239 | 04369ff2 | bellard | static inline int ldsw(void *ptr) |
240 | 04369ff2 | bellard | { |
241 | 04369ff2 | bellard | #ifdef __powerpc__
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242 | 04369ff2 | bellard | int val;
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243 | 04369ff2 | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
244 | 04369ff2 | bellard | return (int16_t)val;
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245 | 04369ff2 | bellard | #else
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246 | 04369ff2 | bellard | uint8_t *p = ptr; |
247 | 04369ff2 | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
248 | 04369ff2 | bellard | #endif
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249 | 04369ff2 | bellard | } |
250 | 04369ff2 | bellard | |
251 | 04369ff2 | bellard | static inline int ldl(void *ptr) |
252 | 04369ff2 | bellard | { |
253 | 04369ff2 | bellard | #ifdef __powerpc__
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254 | 04369ff2 | bellard | int val;
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255 | 04369ff2 | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
256 | 04369ff2 | bellard | return val;
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257 | 04369ff2 | bellard | #else
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258 | 04369ff2 | bellard | uint8_t *p = ptr; |
259 | 04369ff2 | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
260 | 04369ff2 | bellard | #endif
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261 | 04369ff2 | bellard | } |
262 | 04369ff2 | bellard | |
263 | 04369ff2 | bellard | static inline uint64_t ldq(void *ptr) |
264 | 04369ff2 | bellard | { |
265 | 04369ff2 | bellard | uint8_t *p = ptr; |
266 | 04369ff2 | bellard | uint32_t v1, v2; |
267 | 04369ff2 | bellard | v1 = ldl(p); |
268 | 04369ff2 | bellard | v2 = ldl(p + 4);
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269 | 04369ff2 | bellard | return v1 | ((uint64_t)v2 << 32); |
270 | 04369ff2 | bellard | } |
271 | 04369ff2 | bellard | |
272 | 04369ff2 | bellard | static inline void stw(void *ptr, int v) |
273 | 04369ff2 | bellard | { |
274 | 04369ff2 | bellard | #ifdef __powerpc__
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275 | 04369ff2 | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
276 | 04369ff2 | bellard | #else
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277 | 04369ff2 | bellard | uint8_t *p = ptr; |
278 | 04369ff2 | bellard | p[0] = v;
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279 | 04369ff2 | bellard | p[1] = v >> 8; |
280 | 04369ff2 | bellard | #endif
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281 | 04369ff2 | bellard | } |
282 | 04369ff2 | bellard | |
283 | 04369ff2 | bellard | static inline void stl(void *ptr, int v) |
284 | 04369ff2 | bellard | { |
285 | 04369ff2 | bellard | #ifdef __powerpc__
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286 | 04369ff2 | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
287 | 04369ff2 | bellard | #else
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288 | 04369ff2 | bellard | uint8_t *p = ptr; |
289 | 04369ff2 | bellard | p[0] = v;
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290 | 04369ff2 | bellard | p[1] = v >> 8; |
291 | 04369ff2 | bellard | p[2] = v >> 16; |
292 | 04369ff2 | bellard | p[3] = v >> 24; |
293 | 04369ff2 | bellard | #endif
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294 | 04369ff2 | bellard | } |
295 | 04369ff2 | bellard | |
296 | 04369ff2 | bellard | static inline void stq(void *ptr, uint64_t v) |
297 | 04369ff2 | bellard | { |
298 | 04369ff2 | bellard | uint8_t *p = ptr; |
299 | 04369ff2 | bellard | stl(p, (uint32_t)v); |
300 | 04369ff2 | bellard | stl(p + 4, v >> 32); |
301 | 04369ff2 | bellard | } |
302 | 04369ff2 | bellard | |
303 | 04369ff2 | bellard | /* float access */
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304 | 04369ff2 | bellard | |
305 | 04369ff2 | bellard | static inline float ldfl(void *ptr) |
306 | 04369ff2 | bellard | { |
307 | 04369ff2 | bellard | union {
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308 | 04369ff2 | bellard | float f;
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309 | 04369ff2 | bellard | uint32_t i; |
310 | 04369ff2 | bellard | } u; |
311 | 04369ff2 | bellard | u.i = ldl(ptr); |
312 | 04369ff2 | bellard | return u.f;
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313 | 04369ff2 | bellard | } |
314 | 04369ff2 | bellard | |
315 | 04369ff2 | bellard | static inline double ldfq(void *ptr) |
316 | 04369ff2 | bellard | { |
317 | 04369ff2 | bellard | union {
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318 | 04369ff2 | bellard | double d;
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319 | 04369ff2 | bellard | uint64_t i; |
320 | 04369ff2 | bellard | } u; |
321 | 04369ff2 | bellard | u.i = ldq(ptr); |
322 | 04369ff2 | bellard | return u.d;
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323 | 04369ff2 | bellard | } |
324 | 04369ff2 | bellard | |
325 | 04369ff2 | bellard | static inline void stfl(void *ptr, float v) |
326 | 04369ff2 | bellard | { |
327 | 04369ff2 | bellard | union {
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328 | 04369ff2 | bellard | float f;
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329 | 04369ff2 | bellard | uint32_t i; |
330 | 04369ff2 | bellard | } u; |
331 | 04369ff2 | bellard | u.f = v; |
332 | 04369ff2 | bellard | stl(ptr, u.i); |
333 | 04369ff2 | bellard | } |
334 | 04369ff2 | bellard | |
335 | 04369ff2 | bellard | static inline void stfq(void *ptr, double v) |
336 | 04369ff2 | bellard | { |
337 | 04369ff2 | bellard | union {
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338 | 04369ff2 | bellard | double d;
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339 | 04369ff2 | bellard | uint64_t i; |
340 | 04369ff2 | bellard | } u; |
341 | 04369ff2 | bellard | u.d = v; |
342 | 04369ff2 | bellard | stq(ptr, u.i); |
343 | 04369ff2 | bellard | } |
344 | 04369ff2 | bellard | |
345 | 04369ff2 | bellard | #else
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346 | 04369ff2 | bellard | |
347 | 367e86e8 | bellard | static inline int lduw(void *ptr) |
348 | 367e86e8 | bellard | { |
349 | 367e86e8 | bellard | return *(uint16_t *)ptr;
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350 | 367e86e8 | bellard | } |
351 | 367e86e8 | bellard | |
352 | 367e86e8 | bellard | static inline int ldsw(void *ptr) |
353 | 367e86e8 | bellard | { |
354 | 367e86e8 | bellard | return *(int16_t *)ptr;
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355 | 367e86e8 | bellard | } |
356 | 367e86e8 | bellard | |
357 | 367e86e8 | bellard | static inline int ldl(void *ptr) |
358 | 367e86e8 | bellard | { |
359 | 367e86e8 | bellard | return *(uint32_t *)ptr;
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360 | 367e86e8 | bellard | } |
361 | 367e86e8 | bellard | |
362 | 927f621e | bellard | static inline uint64_t ldq(void *ptr) |
363 | 927f621e | bellard | { |
364 | 927f621e | bellard | return *(uint64_t *)ptr;
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365 | 927f621e | bellard | } |
366 | 367e86e8 | bellard | |
367 | 367e86e8 | bellard | static inline void stw(void *ptr, int v) |
368 | 367e86e8 | bellard | { |
369 | 367e86e8 | bellard | *(uint16_t *)ptr = v; |
370 | 367e86e8 | bellard | } |
371 | 367e86e8 | bellard | |
372 | 367e86e8 | bellard | static inline void stl(void *ptr, int v) |
373 | 367e86e8 | bellard | { |
374 | 367e86e8 | bellard | *(uint32_t *)ptr = v; |
375 | 367e86e8 | bellard | } |
376 | 367e86e8 | bellard | |
377 | 77f8dd5a | bellard | static inline void stq(void *ptr, uint64_t v) |
378 | 927f621e | bellard | { |
379 | 927f621e | bellard | *(uint64_t *)ptr = v; |
380 | 927f621e | bellard | } |
381 | 927f621e | bellard | |
382 | 927f621e | bellard | /* float access */
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383 | 927f621e | bellard | |
384 | 927f621e | bellard | static inline float ldfl(void *ptr) |
385 | 927f621e | bellard | { |
386 | 927f621e | bellard | return *(float *)ptr; |
387 | 927f621e | bellard | } |
388 | 927f621e | bellard | |
389 | 927f621e | bellard | static inline double ldfq(void *ptr) |
390 | 927f621e | bellard | { |
391 | 927f621e | bellard | return *(double *)ptr; |
392 | 927f621e | bellard | } |
393 | 927f621e | bellard | |
394 | 927f621e | bellard | static inline void stfl(void *ptr, float v) |
395 | 927f621e | bellard | { |
396 | 927f621e | bellard | *(float *)ptr = v;
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397 | 927f621e | bellard | } |
398 | 927f621e | bellard | |
399 | 927f621e | bellard | static inline void stfq(void *ptr, double v) |
400 | 927f621e | bellard | { |
401 | 927f621e | bellard | *(double *)ptr = v;
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402 | 927f621e | bellard | } |
403 | 04369ff2 | bellard | #endif
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404 | 927f621e | bellard | |
405 | 927f621e | bellard | #ifndef IN_OP_I386
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406 | 9ba5695c | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val); |
407 | 9ba5695c | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val); |
408 | 9ba5695c | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val); |
409 | 9ba5695c | bellard | int cpu_x86_inb(CPUX86State *env, int addr); |
410 | 9ba5695c | bellard | int cpu_x86_inw(CPUX86State *env, int addr); |
411 | 9ba5695c | bellard | int cpu_x86_inl(CPUX86State *env, int addr); |
412 | 927f621e | bellard | #endif
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413 | 367e86e8 | bellard | |
414 | ba1c6e37 | bellard | CPUX86State *cpu_x86_init(void);
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415 | ba1c6e37 | bellard | int cpu_x86_exec(CPUX86State *s);
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416 | 9de5e440 | bellard | void cpu_x86_interrupt(CPUX86State *s);
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417 | ba1c6e37 | bellard | void cpu_x86_close(CPUX86State *s);
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418 | ba1c6e37 | bellard | |
419 | 6dbad63e | bellard | /* needed to load some predefinied segment registers */
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420 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
421 | 6dbad63e | bellard | |
422 | d691f669 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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423 | 9de5e440 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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424 | 9de5e440 | bellard | is returned if the signal was handled by the virtual CPU. */
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425 | 9de5e440 | bellard | struct siginfo;
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426 | 9de5e440 | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
427 | 9de5e440 | bellard | void *puc);
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428 | 9de5e440 | bellard | |
429 | f351077e | bellard | /* used to debug */
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430 | f351077e | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
431 | f351077e | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
432 | f351077e | bellard | void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags); |
433 | f351077e | bellard | |
434 | ba1c6e37 | bellard | /* internal functions */
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435 | 6dbad63e | bellard | |
436 | 6dbad63e | bellard | #define GEN_FLAG_CODE32_SHIFT 0 |
437 | 6dbad63e | bellard | #define GEN_FLAG_ADDSEG_SHIFT 1 |
438 | dab2ed99 | bellard | #define GEN_FLAG_SS32_SHIFT 2 |
439 | fc2b4c48 | bellard | #define GEN_FLAG_VM_SHIFT 3 |
440 | fc2b4c48 | bellard | #define GEN_FLAG_ST_SHIFT 4 |
441 | 9ba5695c | bellard | #define GEN_FLAG_CPL_SHIFT 7 |
442 | 9ba5695c | bellard | #define GEN_FLAG_IOPL_SHIFT 9 |
443 | cabb4d61 | bellard | #define GEN_FLAG_TF_SHIFT 11 |
444 | dab2ed99 | bellard | |
445 | 1017ebe9 | bellard | int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size, |
446 | dab2ed99 | bellard | int *gen_code_size_ptr,
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447 | dab2ed99 | bellard | uint8_t *pc_start, uint8_t *cs_base, int flags);
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448 | 7d13299d | bellard | void cpu_x86_tblocks_init(void); |
449 | ba1c6e37 | bellard | |
450 | 367e86e8 | bellard | #endif /* CPU_I386_H */ |