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1 | dc99065b | bellard | /* Interface between the opcode library and its callers.
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2 | dc99065b | bellard | Written by Cygnus Support, 1993.
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3 | dc99065b | bellard | |
4 | dc99065b | bellard | The opcode library (libopcodes.a) provides instruction decoders for
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5 | dc99065b | bellard | a large variety of instruction sets, callable with an identical
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6 | dc99065b | bellard | interface, for making instruction-processing programs more independent
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7 | dc99065b | bellard | of the instruction set being processed. */
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8 | dc99065b | bellard | |
9 | dc99065b | bellard | #ifndef DIS_ASM_H
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10 | dc99065b | bellard | #define DIS_ASM_H
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11 | dc99065b | bellard | |
12 | dc99065b | bellard | #include <stdio.h> |
13 | 04369ff2 | bellard | #include <string.h> |
14 | 43d4145a | bellard | #include <inttypes.h> |
15 | 43d4145a | bellard | |
16 | 43d4145a | bellard | #define PARAMS(x) x
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17 | 43d4145a | bellard | typedef void *PTR; |
18 | 43d4145a | bellard | typedef uint64_t bfd_vma;
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19 | 43d4145a | bellard | typedef uint8_t bfd_byte;
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20 | 43d4145a | bellard | |
21 | 43d4145a | bellard | enum bfd_flavour {
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22 | 43d4145a | bellard | bfd_target_unknown_flavour, |
23 | 43d4145a | bellard | bfd_target_aout_flavour, |
24 | 43d4145a | bellard | bfd_target_coff_flavour, |
25 | 43d4145a | bellard | bfd_target_ecoff_flavour, |
26 | 43d4145a | bellard | bfd_target_elf_flavour, |
27 | 43d4145a | bellard | bfd_target_ieee_flavour, |
28 | 43d4145a | bellard | bfd_target_nlm_flavour, |
29 | 43d4145a | bellard | bfd_target_oasys_flavour, |
30 | 43d4145a | bellard | bfd_target_tekhex_flavour, |
31 | 43d4145a | bellard | bfd_target_srec_flavour, |
32 | 43d4145a | bellard | bfd_target_ihex_flavour, |
33 | 43d4145a | bellard | bfd_target_som_flavour, |
34 | 43d4145a | bellard | bfd_target_os9k_flavour, |
35 | 43d4145a | bellard | bfd_target_versados_flavour, |
36 | 43d4145a | bellard | bfd_target_msdos_flavour, |
37 | 43d4145a | bellard | bfd_target_evax_flavour |
38 | 43d4145a | bellard | }; |
39 | 43d4145a | bellard | |
40 | 43d4145a | bellard | enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
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41 | 43d4145a | bellard | |
42 | 43d4145a | bellard | enum bfd_architecture
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43 | 43d4145a | bellard | { |
44 | 43d4145a | bellard | bfd_arch_unknown, /* File arch not known */
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45 | 43d4145a | bellard | bfd_arch_obscure, /* Arch known, not one of these */
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46 | 43d4145a | bellard | bfd_arch_m68k, /* Motorola 68xxx */
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47 | 43d4145a | bellard | #define bfd_mach_m68000 1 |
48 | 43d4145a | bellard | #define bfd_mach_m68008 2 |
49 | 43d4145a | bellard | #define bfd_mach_m68010 3 |
50 | 43d4145a | bellard | #define bfd_mach_m68020 4 |
51 | 43d4145a | bellard | #define bfd_mach_m68030 5 |
52 | 43d4145a | bellard | #define bfd_mach_m68040 6 |
53 | 43d4145a | bellard | #define bfd_mach_m68060 7 |
54 | 43d4145a | bellard | bfd_arch_vax, /* DEC Vax */
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55 | 43d4145a | bellard | bfd_arch_i960, /* Intel 960 */
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56 | 43d4145a | bellard | /* The order of the following is important.
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57 | 43d4145a | bellard | lower number indicates a machine type that
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58 | 43d4145a | bellard | only accepts a subset of the instructions
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59 | 43d4145a | bellard | available to machines with higher numbers.
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60 | 43d4145a | bellard | The exception is the "ca", which is
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61 | 43d4145a | bellard | incompatible with all other machines except
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62 | 43d4145a | bellard | "core". */
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63 | 43d4145a | bellard | |
64 | 43d4145a | bellard | #define bfd_mach_i960_core 1 |
65 | 43d4145a | bellard | #define bfd_mach_i960_ka_sa 2 |
66 | 43d4145a | bellard | #define bfd_mach_i960_kb_sb 3 |
67 | 43d4145a | bellard | #define bfd_mach_i960_mc 4 |
68 | 43d4145a | bellard | #define bfd_mach_i960_xa 5 |
69 | 43d4145a | bellard | #define bfd_mach_i960_ca 6 |
70 | 43d4145a | bellard | #define bfd_mach_i960_jx 7 |
71 | 43d4145a | bellard | #define bfd_mach_i960_hx 8 |
72 | 43d4145a | bellard | |
73 | 43d4145a | bellard | bfd_arch_a29k, /* AMD 29000 */
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74 | 43d4145a | bellard | bfd_arch_sparc, /* SPARC */
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75 | 43d4145a | bellard | #define bfd_mach_sparc 1 |
76 | 43d4145a | bellard | /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
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77 | 43d4145a | bellard | #define bfd_mach_sparc_sparclet 2 |
78 | 43d4145a | bellard | #define bfd_mach_sparc_sparclite 3 |
79 | 43d4145a | bellard | #define bfd_mach_sparc_v8plus 4 |
80 | 43d4145a | bellard | #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns */ |
81 | 43d4145a | bellard | #define bfd_mach_sparc_v9 6 |
82 | 43d4145a | bellard | #define bfd_mach_sparc_v9a 7 /* with ultrasparc add'ns */ |
83 | 43d4145a | bellard | /* Nonzero if MACH has the v9 instruction set. */
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84 | 43d4145a | bellard | #define bfd_mach_sparc_v9_p(mach) \
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85 | 43d4145a | bellard | ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a) |
86 | 43d4145a | bellard | bfd_arch_mips, /* MIPS Rxxxx */
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87 | 43d4145a | bellard | #define bfd_mach_mips3000 3000 |
88 | 43d4145a | bellard | #define bfd_mach_mips3900 3900 |
89 | 43d4145a | bellard | #define bfd_mach_mips4000 4000 |
90 | 43d4145a | bellard | #define bfd_mach_mips4010 4010 |
91 | 43d4145a | bellard | #define bfd_mach_mips4100 4100 |
92 | 43d4145a | bellard | #define bfd_mach_mips4300 4300 |
93 | 43d4145a | bellard | #define bfd_mach_mips4400 4400 |
94 | 43d4145a | bellard | #define bfd_mach_mips4600 4600 |
95 | 43d4145a | bellard | #define bfd_mach_mips4650 4650 |
96 | 43d4145a | bellard | #define bfd_mach_mips5000 5000 |
97 | 43d4145a | bellard | #define bfd_mach_mips6000 6000 |
98 | 43d4145a | bellard | #define bfd_mach_mips8000 8000 |
99 | 43d4145a | bellard | #define bfd_mach_mips10000 10000 |
100 | 43d4145a | bellard | #define bfd_mach_mips16 16 |
101 | 43d4145a | bellard | bfd_arch_i386, /* Intel 386 */
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102 | 43d4145a | bellard | #define bfd_mach_i386_i386 0 |
103 | 43d4145a | bellard | #define bfd_mach_i386_i8086 1 |
104 | 43d4145a | bellard | bfd_arch_we32k, /* AT&T WE32xxx */
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105 | 43d4145a | bellard | bfd_arch_tahoe, /* CCI/Harris Tahoe */
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106 | 43d4145a | bellard | bfd_arch_i860, /* Intel 860 */
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107 | 43d4145a | bellard | bfd_arch_romp, /* IBM ROMP PC/RT */
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108 | 43d4145a | bellard | bfd_arch_alliant, /* Alliant */
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109 | 43d4145a | bellard | bfd_arch_convex, /* Convex */
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110 | 43d4145a | bellard | bfd_arch_m88k, /* Motorola 88xxx */
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111 | 43d4145a | bellard | bfd_arch_pyramid, /* Pyramid Technology */
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112 | 43d4145a | bellard | bfd_arch_h8300, /* Hitachi H8/300 */
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113 | 43d4145a | bellard | #define bfd_mach_h8300 1 |
114 | 43d4145a | bellard | #define bfd_mach_h8300h 2 |
115 | 43d4145a | bellard | #define bfd_mach_h8300s 3 |
116 | 43d4145a | bellard | bfd_arch_powerpc, /* PowerPC */
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117 | 43d4145a | bellard | bfd_arch_rs6000, /* IBM RS/6000 */
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118 | 43d4145a | bellard | bfd_arch_hppa, /* HP PA RISC */
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119 | 43d4145a | bellard | bfd_arch_d10v, /* Mitsubishi D10V */
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120 | 43d4145a | bellard | bfd_arch_z8k, /* Zilog Z8000 */
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121 | 43d4145a | bellard | #define bfd_mach_z8001 1 |
122 | 43d4145a | bellard | #define bfd_mach_z8002 2 |
123 | 43d4145a | bellard | bfd_arch_h8500, /* Hitachi H8/500 */
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124 | 43d4145a | bellard | bfd_arch_sh, /* Hitachi SH */
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125 | 43d4145a | bellard | #define bfd_mach_sh 0 |
126 | 43d4145a | bellard | #define bfd_mach_sh3 0x30 |
127 | 43d4145a | bellard | #define bfd_mach_sh3e 0x3e |
128 | 43d4145a | bellard | #define bfd_mach_sh4 0x40 |
129 | 43d4145a | bellard | bfd_arch_alpha, /* Dec Alpha */
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130 | 43d4145a | bellard | bfd_arch_arm, /* Advanced Risc Machines ARM */
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131 | 43d4145a | bellard | #define bfd_mach_arm_2 1 |
132 | 43d4145a | bellard | #define bfd_mach_arm_2a 2 |
133 | 43d4145a | bellard | #define bfd_mach_arm_3 3 |
134 | 43d4145a | bellard | #define bfd_mach_arm_3M 4 |
135 | 43d4145a | bellard | #define bfd_mach_arm_4 5 |
136 | 43d4145a | bellard | #define bfd_mach_arm_4T 6 |
137 | 43d4145a | bellard | bfd_arch_ns32k, /* National Semiconductors ns32000 */
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138 | 43d4145a | bellard | bfd_arch_w65, /* WDC 65816 */
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139 | 43d4145a | bellard | bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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140 | 43d4145a | bellard | bfd_arch_v850, /* NEC V850 */
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141 | 43d4145a | bellard | #define bfd_mach_v850 0 |
142 | 43d4145a | bellard | bfd_arch_arc, /* Argonaut RISC Core */
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143 | 43d4145a | bellard | #define bfd_mach_arc_base 0 |
144 | 43d4145a | bellard | bfd_arch_m32r, /* Mitsubishi M32R/D */
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145 | 43d4145a | bellard | #define bfd_mach_m32r 0 /* backwards compatibility */ |
146 | 43d4145a | bellard | bfd_arch_mn10200, /* Matsushita MN10200 */
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147 | 43d4145a | bellard | bfd_arch_mn10300, /* Matsushita MN10300 */
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148 | 43d4145a | bellard | bfd_arch_last |
149 | 43d4145a | bellard | }; |
150 | 43d4145a | bellard | |
151 | 43d4145a | bellard | typedef struct symbol_cache_entry |
152 | 43d4145a | bellard | { |
153 | 43d4145a | bellard | const char *name; |
154 | 43d4145a | bellard | union
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155 | 43d4145a | bellard | { |
156 | 43d4145a | bellard | PTR p; |
157 | 43d4145a | bellard | bfd_vma i; |
158 | 43d4145a | bellard | } udata; |
159 | 43d4145a | bellard | } asymbol; |
160 | dc99065b | bellard | |
161 | dc99065b | bellard | typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...)); |
162 | dc99065b | bellard | |
163 | dc99065b | bellard | enum dis_insn_type {
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164 | dc99065b | bellard | dis_noninsn, /* Not a valid instruction */
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165 | dc99065b | bellard | dis_nonbranch, /* Not a branch instruction */
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166 | dc99065b | bellard | dis_branch, /* Unconditional branch */
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167 | dc99065b | bellard | dis_condbranch, /* Conditional branch */
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168 | dc99065b | bellard | dis_jsr, /* Jump to subroutine */
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169 | dc99065b | bellard | dis_condjsr, /* Conditional jump to subroutine */
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170 | dc99065b | bellard | dis_dref, /* Data reference instruction */
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171 | dc99065b | bellard | dis_dref2 /* Two data references in instruction */
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172 | dc99065b | bellard | }; |
173 | dc99065b | bellard | |
174 | dc99065b | bellard | /* This struct is passed into the instruction decoding routine,
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175 | dc99065b | bellard | and is passed back out into each callback. The various fields are used
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176 | dc99065b | bellard | for conveying information from your main routine into your callbacks,
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177 | dc99065b | bellard | for passing information into the instruction decoders (such as the
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178 | dc99065b | bellard | addresses of the callback functions), or for passing information
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179 | dc99065b | bellard | back from the instruction decoders to their callers.
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180 | dc99065b | bellard | |
181 | dc99065b | bellard | It must be initialized before it is first passed; this can be done
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182 | dc99065b | bellard | by hand, or using one of the initialization macros below. */
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183 | dc99065b | bellard | |
184 | dc99065b | bellard | typedef struct disassemble_info { |
185 | dc99065b | bellard | fprintf_ftype fprintf_func; |
186 | dc99065b | bellard | FILE *stream; |
187 | dc99065b | bellard | PTR application_data; |
188 | dc99065b | bellard | |
189 | dc99065b | bellard | /* Target description. We could replace this with a pointer to the bfd,
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190 | dc99065b | bellard | but that would require one. There currently isn't any such requirement
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191 | dc99065b | bellard | so to avoid introducing one we record these explicitly. */
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192 | dc99065b | bellard | /* The bfd_flavour. This can be bfd_target_unknown_flavour. */
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193 | dc99065b | bellard | enum bfd_flavour flavour;
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194 | dc99065b | bellard | /* The bfd_arch value. */
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195 | dc99065b | bellard | enum bfd_architecture arch;
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196 | dc99065b | bellard | /* The bfd_mach value. */
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197 | dc99065b | bellard | unsigned long mach; |
198 | dc99065b | bellard | /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
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199 | dc99065b | bellard | enum bfd_endian endian;
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200 | dc99065b | bellard | |
201 | dc99065b | bellard | /* An array of pointers to symbols either at the location being disassembled
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202 | dc99065b | bellard | or at the start of the function being disassembled. The array is sorted
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203 | dc99065b | bellard | so that the first symbol is intended to be the one used. The others are
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204 | dc99065b | bellard | present for any misc. purposes. This is not set reliably, but if it is
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205 | dc99065b | bellard | not NULL, it is correct. */
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206 | dc99065b | bellard | asymbol **symbols; |
207 | dc99065b | bellard | /* Number of symbols in array. */
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208 | dc99065b | bellard | int num_symbols;
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209 | dc99065b | bellard | |
210 | dc99065b | bellard | /* For use by the disassembler.
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211 | dc99065b | bellard | The top 16 bits are reserved for public use (and are documented here).
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212 | dc99065b | bellard | The bottom 16 bits are for the internal use of the disassembler. */
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213 | dc99065b | bellard | unsigned long flags; |
214 | dc99065b | bellard | #define INSN_HAS_RELOC 0x80000000 |
215 | dc99065b | bellard | PTR private_data; |
216 | dc99065b | bellard | |
217 | dc99065b | bellard | /* Function used to get bytes to disassemble. MEMADDR is the
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218 | dc99065b | bellard | address of the stuff to be disassembled, MYADDR is the address to
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219 | dc99065b | bellard | put the bytes in, and LENGTH is the number of bytes to read.
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220 | dc99065b | bellard | INFO is a pointer to this struct.
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221 | dc99065b | bellard | Returns an errno value or 0 for success. */
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222 | dc99065b | bellard | int (*read_memory_func)
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223 | dc99065b | bellard | PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
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224 | dc99065b | bellard | struct disassemble_info *info));
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225 | dc99065b | bellard | |
226 | dc99065b | bellard | /* Function which should be called if we get an error that we can't
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227 | dc99065b | bellard | recover from. STATUS is the errno value from read_memory_func and
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228 | dc99065b | bellard | MEMADDR is the address that we were trying to read. INFO is a
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229 | dc99065b | bellard | pointer to this struct. */
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230 | dc99065b | bellard | void (*memory_error_func)
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231 | dc99065b | bellard | PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info)); |
232 | dc99065b | bellard | |
233 | dc99065b | bellard | /* Function called to print ADDR. */
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234 | dc99065b | bellard | void (*print_address_func)
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235 | dc99065b | bellard | PARAMS ((bfd_vma addr, struct disassemble_info *info));
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236 | dc99065b | bellard | |
237 | dc99065b | bellard | /* Function called to determine if there is a symbol at the given ADDR.
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238 | dc99065b | bellard | If there is, the function returns 1, otherwise it returns 0.
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239 | dc99065b | bellard | This is used by ports which support an overlay manager where
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240 | dc99065b | bellard | the overlay number is held in the top part of an address. In
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241 | dc99065b | bellard | some circumstances we want to include the overlay number in the
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242 | dc99065b | bellard | address, (normally because there is a symbol associated with
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243 | dc99065b | bellard | that address), but sometimes we want to mask out the overlay bits. */
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244 | dc99065b | bellard | int (* symbol_at_address_func)
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245 | dc99065b | bellard | PARAMS ((bfd_vma addr, struct disassemble_info * info));
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246 | dc99065b | bellard | |
247 | dc99065b | bellard | /* These are for buffer_read_memory. */
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248 | dc99065b | bellard | bfd_byte *buffer; |
249 | dc99065b | bellard | bfd_vma buffer_vma; |
250 | dc99065b | bellard | int buffer_length;
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251 | dc99065b | bellard | |
252 | dc99065b | bellard | /* This variable may be set by the instruction decoder. It suggests
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253 | dc99065b | bellard | the number of bytes objdump should display on a single line. If
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254 | dc99065b | bellard | the instruction decoder sets this, it should always set it to
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255 | dc99065b | bellard | the same value in order to get reasonable looking output. */
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256 | dc99065b | bellard | int bytes_per_line;
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257 | dc99065b | bellard | |
258 | dc99065b | bellard | /* the next two variables control the way objdump displays the raw data */
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259 | dc99065b | bellard | /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
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260 | dc99065b | bellard | /* output will look like this:
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261 | dc99065b | bellard | 00: 00000000 00000000
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262 | dc99065b | bellard | with the chunks displayed according to "display_endian". */
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263 | dc99065b | bellard | int bytes_per_chunk;
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264 | dc99065b | bellard | enum bfd_endian display_endian;
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265 | dc99065b | bellard | |
266 | dc99065b | bellard | /* Results from instruction decoders. Not all decoders yet support
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267 | dc99065b | bellard | this information. This info is set each time an instruction is
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268 | dc99065b | bellard | decoded, and is only valid for the last such instruction.
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269 | dc99065b | bellard | |
270 | dc99065b | bellard | To determine whether this decoder supports this information, set
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271 | dc99065b | bellard | insn_info_valid to 0, decode an instruction, then check it. */
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272 | dc99065b | bellard | |
273 | dc99065b | bellard | char insn_info_valid; /* Branch info has been set. */ |
274 | dc99065b | bellard | char branch_delay_insns; /* How many sequential insn's will run before |
275 | dc99065b | bellard | a branch takes effect. (0 = normal) */
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276 | dc99065b | bellard | char data_size; /* Size of data reference in insn, in bytes */ |
277 | dc99065b | bellard | enum dis_insn_type insn_type; /* Type of instruction */ |
278 | dc99065b | bellard | bfd_vma target; /* Target address of branch or dref, if known;
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279 | dc99065b | bellard | zero if unknown. */
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280 | dc99065b | bellard | bfd_vma target2; /* Second target address for dref2 */
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281 | dc99065b | bellard | |
282 | dc99065b | bellard | } disassemble_info; |
283 | dc99065b | bellard | |
284 | dc99065b | bellard | |
285 | dc99065b | bellard | /* Standard disassemblers. Disassemble one instruction at the given
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286 | dc99065b | bellard | target address. Return number of bytes processed. */
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287 | dc99065b | bellard | typedef int (*disassembler_ftype) |
288 | dc99065b | bellard | PARAMS((bfd_vma, disassemble_info *)); |
289 | dc99065b | bellard | |
290 | dc99065b | bellard | extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*)); |
291 | dc99065b | bellard | extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*)); |
292 | dc99065b | bellard | extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*)); |
293 | dc99065b | bellard | extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); |
294 | dc99065b | bellard | extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); |
295 | dc99065b | bellard | extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); |
296 | dc99065b | bellard | extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*)); |
297 | dc99065b | bellard | extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*)); |
298 | dc99065b | bellard | extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*)); |
299 | dc99065b | bellard | extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*)); |
300 | dc99065b | bellard | extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); |
301 | dc99065b | bellard | extern disassembler_ftype arc_get_disassembler PARAMS ((int, int)); |
302 | dc99065b | bellard | extern int print_insn_big_arm PARAMS ((bfd_vma, disassemble_info*)); |
303 | dc99065b | bellard | extern int print_insn_little_arm PARAMS ((bfd_vma, disassemble_info*)); |
304 | dc99065b | bellard | extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*)); |
305 | dc99065b | bellard | extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*)); |
306 | dc99065b | bellard | extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*)); |
307 | dc99065b | bellard | extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*)); |
308 | dc99065b | bellard | extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*)); |
309 | dc99065b | bellard | extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*)); |
310 | dc99065b | bellard | extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*)); |
311 | dc99065b | bellard | extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*)); |
312 | dc99065b | bellard | extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*)); |
313 | dc99065b | bellard | extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*)); |
314 | dc99065b | bellard | extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*)); |
315 | dc99065b | bellard | extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*)); |
316 | dc99065b | bellard | extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*)); |
317 | dc99065b | bellard | extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*)); |
318 | dc99065b | bellard | extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*)); |
319 | dc99065b | bellard | extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*)); |
320 | dc99065b | bellard | extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); |
321 | dc99065b | bellard | extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); |
322 | dc99065b | bellard | extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); |
323 | b9adb4a6 | bellard | extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*)); |
324 | dc99065b | bellard | |
325 | 43d4145a | bellard | #if 0
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326 | dc99065b | bellard | /* Fetch the disassembler for a given BFD, if that support is available. */
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327 | dc99065b | bellard | extern disassembler_ftype disassembler PARAMS ((bfd *));
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328 | 43d4145a | bellard | #endif
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329 | dc99065b | bellard | |
330 | dc99065b | bellard | |
331 | dc99065b | bellard | /* This block of definitions is for particular callers who read instructions
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332 | dc99065b | bellard | into a buffer before calling the instruction decoder. */
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333 | dc99065b | bellard | |
334 | dc99065b | bellard | /* Here is a function which callers may wish to use for read_memory_func.
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335 | dc99065b | bellard | It gets bytes from a buffer. */
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336 | dc99065b | bellard | extern int buffer_read_memory |
337 | dc99065b | bellard | PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); |
338 | dc99065b | bellard | |
339 | dc99065b | bellard | /* This function goes with buffer_read_memory.
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340 | dc99065b | bellard | It prints a message using info->fprintf_func and info->stream. */
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341 | dc99065b | bellard | extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *)); |
342 | dc99065b | bellard | |
343 | dc99065b | bellard | |
344 | dc99065b | bellard | /* Just print the address in hex. This is included for completeness even
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345 | dc99065b | bellard | though both GDB and objdump provide their own (to print symbolic
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346 | dc99065b | bellard | addresses). */
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347 | dc99065b | bellard | extern void generic_print_address |
348 | dc99065b | bellard | PARAMS ((bfd_vma, struct disassemble_info *));
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349 | dc99065b | bellard | |
350 | dc99065b | bellard | /* Always true. */
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351 | dc99065b | bellard | extern int generic_symbol_at_address |
352 | dc99065b | bellard | PARAMS ((bfd_vma, struct disassemble_info *));
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353 | dc99065b | bellard | |
354 | dc99065b | bellard | /* Macro to initialize a disassemble_info struct. This should be called
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355 | dc99065b | bellard | by all applications creating such a struct. */
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356 | dc99065b | bellard | #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
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357 | dc99065b | bellard | (INFO).flavour = bfd_target_unknown_flavour, \ |
358 | dc99065b | bellard | (INFO).arch = bfd_arch_unknown, \ |
359 | dc99065b | bellard | (INFO).mach = 0, \
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360 | dc99065b | bellard | (INFO).endian = BFD_ENDIAN_UNKNOWN, \ |
361 | dc99065b | bellard | INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) |
362 | dc99065b | bellard | |
363 | dc99065b | bellard | /* Call this macro to initialize only the internal variables for the
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364 | dc99065b | bellard | disassembler. Architecture dependent things such as byte order, or machine
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365 | dc99065b | bellard | variant are not touched by this macro. This makes things much easier for
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366 | dc99065b | bellard | GDB which must initialize these things seperatly. */
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367 | dc99065b | bellard | |
368 | dc99065b | bellard | #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
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369 | dc99065b | bellard | (INFO).fprintf_func = (FPRINTF_FUNC), \ |
370 | dc99065b | bellard | (INFO).stream = (STREAM), \ |
371 | dc99065b | bellard | (INFO).symbols = NULL, \
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372 | dc99065b | bellard | (INFO).num_symbols = 0, \
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373 | dc99065b | bellard | (INFO).buffer = NULL, \
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374 | dc99065b | bellard | (INFO).buffer_vma = 0, \
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375 | dc99065b | bellard | (INFO).buffer_length = 0, \
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376 | dc99065b | bellard | (INFO).read_memory_func = buffer_read_memory, \ |
377 | dc99065b | bellard | (INFO).memory_error_func = perror_memory, \ |
378 | dc99065b | bellard | (INFO).print_address_func = generic_print_address, \ |
379 | dc99065b | bellard | (INFO).symbol_at_address_func = generic_symbol_at_address, \ |
380 | dc99065b | bellard | (INFO).flags = 0, \
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381 | dc99065b | bellard | (INFO).bytes_per_line = 0, \
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382 | dc99065b | bellard | (INFO).bytes_per_chunk = 0, \
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383 | dc99065b | bellard | (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \ |
384 | dc99065b | bellard | (INFO).insn_info_valid = 0
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385 | dc99065b | bellard | |
386 | dc99065b | bellard | #endif /* ! defined (DIS_ASM_H) */ |