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/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec-i386.h" |
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#include "disas.h" |
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//#define DEBUG_EXEC
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#define DEBUG_FLUSH
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//#define DEBUG_SIGNAL
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/* main execution loop */
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024) |
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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#define CODE_GEN_MAX_SIZE 65536 |
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
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/* threshold to flush the translated code buffer */
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#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64) |
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#define CODE_GEN_HASH_BITS 15 |
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
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typedef struct TranslationBlock { |
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
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unsigned long cs_base; /* CS base for this block */ |
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unsigned int flags; /* flags defining in which context the code was generated */ |
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */ |
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} TranslationBlock; |
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TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; |
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TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; |
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int nb_tbs;
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uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; |
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uint8_t *code_gen_ptr; |
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/* thread support */
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#ifdef __powerpc__
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static inline int testandset (int *p) |
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{ |
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int ret;
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__asm__ __volatile__ ( |
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"0: lwarx %0,0,%1 ;"
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" xor. %0,%3,%0;"
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" bne 1f;"
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" stwcx. %2,0,%1;"
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" bne- 0b;"
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"1: "
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0) |
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: "cr0", "memory"); |
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return ret;
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} |
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#endif
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#ifdef __i386__
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static inline int testandset (int *p) |
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{ |
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char ret;
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long int readval; |
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__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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: "=q" (ret), "=m" (*p), "=a" (readval) |
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: "r" (1), "m" (*p), "a" (0) |
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: "memory");
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return ret;
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} |
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#endif
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#ifdef __s390__
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static inline int testandset (int *p) |
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{ |
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int ret;
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b"
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: "=&d" (ret)
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: "r" (1), "a" (p), "0" (*p) |
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: "cc", "memory" ); |
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return ret;
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} |
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#endif
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#ifdef __alpha__
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int testandset (int *p) |
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{ |
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int ret;
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unsigned long one; |
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n"
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" stl_c %2,%1\n"
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" beq %2,1f\n"
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".subsection 2\n"
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"1: br 0b\n"
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".previous"
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: "=r" (ret), "=m" (*p), "=r" (one) |
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: "m" (*p));
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return ret;
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} |
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#endif
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#ifdef __sparc__
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static inline int testandset (int *p) |
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{ |
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int ret;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret)
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: "r" (p)
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: "memory");
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return (ret ? 1 : 0); |
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} |
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#endif
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int global_cpu_lock = 0; |
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void cpu_lock(void) |
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{ |
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while (testandset(&global_cpu_lock));
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} |
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void cpu_unlock(void) |
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{ |
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global_cpu_lock = 0;
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} |
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/* exception support */
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/* NOTE: not static to force relocation generation by GCC */
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void raise_exception_err(int exception_index, int error_code) |
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{ |
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/* NOTE: the register at this point must be saved by hand because
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longjmp restore them */
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#ifdef reg_EAX
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env->regs[R_EAX] = EAX; |
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#endif
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#ifdef reg_ECX
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env->regs[R_ECX] = ECX; |
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#endif
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#ifdef reg_EDX
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env->regs[R_EDX] = EDX; |
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#endif
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#ifdef reg_EBX
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env->regs[R_EBX] = EBX; |
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#endif
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#ifdef reg_ESP
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env->regs[R_ESP] = ESP; |
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#endif
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#ifdef reg_EBP
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env->regs[R_EBP] = EBP; |
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#endif
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#ifdef reg_ESI
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env->regs[R_ESI] = ESI; |
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#endif
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#ifdef reg_EDI
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env->regs[R_EDI] = EDI; |
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#endif
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env->exception_index = exception_index; |
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env->error_code = error_code; |
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longjmp(env->jmp_env, 1);
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} |
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/* short cut if error_code is 0 or not present */
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void raise_exception(int exception_index) |
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{ |
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raise_exception_err(exception_index, 0);
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} |
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void cpu_x86_tblocks_init(void) |
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{ |
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if (!code_gen_ptr) {
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code_gen_ptr = code_gen_buffer; |
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} |
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} |
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/* flush all the translation blocks */
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static void tb_flush(void) |
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{ |
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int i;
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#ifdef DEBUG_FLUSH
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printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
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code_gen_ptr - code_gen_buffer, |
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nb_tbs, |
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(code_gen_ptr - code_gen_buffer) / nb_tbs); |
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#endif
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nb_tbs = 0;
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for(i = 0;i < CODE_GEN_HASH_SIZE; i++) |
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tb_hash[i] = NULL;
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code_gen_ptr = code_gen_buffer; |
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/* XXX: flush processor icache at this point */
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} |
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
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unsigned long pc, |
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unsigned long cs_base, |
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unsigned int flags) |
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{ |
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TranslationBlock **ptb, *tb; |
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unsigned int h; |
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h = pc & (CODE_GEN_HASH_SIZE - 1);
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ptb = &tb_hash[h]; |
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#if 0
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/* XXX: hack to handle 16 bit modyfing code */
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if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
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#endif
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for(;;) {
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tb = *ptb; |
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if (!tb)
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break;
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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return tb;
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ptb = &tb->hash_next; |
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} |
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*pptb = ptb; |
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return NULL; |
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} |
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/* allocate a new translation block. flush the translation buffer if
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too many translation blocks or too much generated code */
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static inline TranslationBlock *tb_alloc(void) |
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{ |
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TranslationBlock *tb; |
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if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
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(code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE) |
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tb_flush(); |
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tb = &tbs[nb_tbs++]; |
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return tb;
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} |
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int cpu_x86_exec(CPUX86State *env1)
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{ |
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int saved_T0, saved_T1, saved_A0;
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CPUX86State *saved_env; |
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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int code_gen_size, ret;
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void (*gen_func)(void); |
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TranslationBlock *tb, **ptb; |
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uint8_t *tc_ptr, *cs_base, *pc; |
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unsigned int flags; |
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/* first we save global registers */
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saved_T0 = T0; |
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saved_T1 = T1; |
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saved_A0 = A0; |
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saved_env = env; |
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env = env1; |
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#ifdef reg_EAX
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saved_EAX = EAX; |
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EAX = env->regs[R_EAX]; |
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX; |
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ECX = env->regs[R_ECX]; |
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX; |
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EDX = env->regs[R_EDX]; |
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX; |
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EBX = env->regs[R_EBX]; |
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP; |
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ESP = env->regs[R_ESP]; |
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP; |
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EBP = env->regs[R_EBP]; |
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI; |
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ESI = env->regs[R_ESI]; |
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI; |
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EDI = env->regs[R_EDI]; |
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
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CC_OP = CC_OP_EFLAGS; |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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env->interrupt_request = 0;
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/* prepare setjmp context for exception handling */
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if (setjmp(env->jmp_env) == 0) { |
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for(;;) {
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if (env->interrupt_request) {
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raise_exception(EXCP_INTERRUPT); |
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} |
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#ifdef DEBUG_EXEC
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if (loglevel) {
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/* XXX: save all volatile state in cpu state */
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX; |
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env->regs[R_EBX] = EBX; |
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env->regs[R_ECX] = ECX; |
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env->regs[R_EDX] = EDX; |
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env->regs[R_ESI] = ESI; |
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env->regs[R_EDI] = EDI; |
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env->regs[R_EBP] = EBP; |
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env->regs[R_ESP] = ESP; |
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
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cpu_x86_dump_state(env, logfile, 0);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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} |
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; |
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flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; |
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flags |= (((unsigned long)env->seg_cache[R_DS].base | |
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(unsigned long)env->seg_cache[R_ES].base | |
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(unsigned long)env->seg_cache[R_SS].base) != 0) << |
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GEN_FLAG_ADDSEG_SHIFT; |
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if (!(env->eflags & VM_MASK)) {
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flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
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} else {
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/* NOTE: a dummy CPL is kept */
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flags |= (1 << GEN_FLAG_VM_SHIFT);
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flags |= (3 << GEN_FLAG_CPL_SHIFT);
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} |
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flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
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flags |= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8);
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cs_base = env->seg_cache[R_CS].base; |
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pc = cs_base + env->eip; |
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
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flags); |
379 |
if (!tb) {
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/* if no translated code available, then translate it now */
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/* XXX: very inefficient: we lock all the cpus when
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generating code */
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cpu_lock(); |
384 |
tc_ptr = code_gen_ptr; |
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ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, |
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&code_gen_size, pc, cs_base, flags); |
387 |
/* if invalid instruction, signal it */
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if (ret != 0) { |
389 |
cpu_unlock(); |
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raise_exception(EXCP06_ILLOP); |
391 |
} |
392 |
tb = tb_alloc(); |
393 |
*ptb = tb; |
394 |
tb->pc = (unsigned long)pc; |
395 |
tb->cs_base = (unsigned long)cs_base; |
396 |
tb->flags = flags; |
397 |
tb->tc_ptr = tc_ptr; |
398 |
tb->hash_next = NULL;
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
400 |
cpu_unlock(); |
401 |
} |
402 |
#ifdef DEBUG_EXEC
|
403 |
if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc, |
406 |
lookup_symbol((void *)tb->pc));
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} |
408 |
#endif
|
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/* execute the generated code */
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410 |
tc_ptr = tb->tc_ptr; |
411 |
gen_func = (void *)tc_ptr;
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gen_func(); |
413 |
} |
414 |
} |
415 |
ret = env->exception_index; |
416 |
|
417 |
/* restore flags in standard format */
|
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
419 |
|
420 |
/* restore global registers */
|
421 |
#ifdef reg_EAX
|
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EAX = saved_EAX; |
423 |
#endif
|
424 |
#ifdef reg_ECX
|
425 |
ECX = saved_ECX; |
426 |
#endif
|
427 |
#ifdef reg_EDX
|
428 |
EDX = saved_EDX; |
429 |
#endif
|
430 |
#ifdef reg_EBX
|
431 |
EBX = saved_EBX; |
432 |
#endif
|
433 |
#ifdef reg_ESP
|
434 |
ESP = saved_ESP; |
435 |
#endif
|
436 |
#ifdef reg_EBP
|
437 |
EBP = saved_EBP; |
438 |
#endif
|
439 |
#ifdef reg_ESI
|
440 |
ESI = saved_ESI; |
441 |
#endif
|
442 |
#ifdef reg_EDI
|
443 |
EDI = saved_EDI; |
444 |
#endif
|
445 |
T0 = saved_T0; |
446 |
T1 = saved_T1; |
447 |
A0 = saved_A0; |
448 |
env = saved_env; |
449 |
return ret;
|
450 |
} |
451 |
|
452 |
void cpu_x86_interrupt(CPUX86State *s)
|
453 |
{ |
454 |
s->interrupt_request = 1;
|
455 |
} |
456 |
|
457 |
|
458 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
459 |
{ |
460 |
CPUX86State *saved_env; |
461 |
|
462 |
saved_env = env; |
463 |
env = s; |
464 |
load_seg(seg_reg, selector); |
465 |
env = saved_env; |
466 |
} |
467 |
|
468 |
#undef EAX
|
469 |
#undef ECX
|
470 |
#undef EDX
|
471 |
#undef EBX
|
472 |
#undef ESP
|
473 |
#undef EBP
|
474 |
#undef ESI
|
475 |
#undef EDI
|
476 |
#undef EIP
|
477 |
#include <signal.h> |
478 |
#include <sys/ucontext.h> |
479 |
|
480 |
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
481 |
the effective address of the memory exception */
|
482 |
static inline int handle_cpu_signal(unsigned long pc, |
483 |
unsigned long address, |
484 |
sigset_t *old_set) |
485 |
{ |
486 |
#ifdef DEBUG_SIGNAL
|
487 |
printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
|
488 |
pc, *(unsigned long *)old_set); |
489 |
#endif
|
490 |
if (pc >= (unsigned long)code_gen_buffer && |
491 |
pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) { |
492 |
/* the PC is inside the translated code. It means that we have
|
493 |
a virtual CPU fault */
|
494 |
/* we restore the process signal mask as the sigreturn should
|
495 |
do it */
|
496 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
497 |
/* XXX: need to compute virtual pc position by retranslating
|
498 |
code. The rest of the CPU state should be correct. */
|
499 |
env->cr2 = address; |
500 |
/* XXX: more precise exception code */
|
501 |
raise_exception_err(EXCP0E_PAGE, 4);
|
502 |
/* never comes here */
|
503 |
return 1; |
504 |
} else {
|
505 |
return 0; |
506 |
} |
507 |
} |
508 |
|
509 |
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
510 |
void *puc)
|
511 |
{ |
512 |
#if defined(__i386__)
|
513 |
struct ucontext *uc = puc;
|
514 |
unsigned long pc; |
515 |
sigset_t *pold_set; |
516 |
|
517 |
#ifndef REG_EIP
|
518 |
/* for glibc 2.1 */
|
519 |
#define REG_EIP EIP
|
520 |
#endif
|
521 |
pc = uc->uc_mcontext.gregs[REG_EIP]; |
522 |
pold_set = &uc->uc_sigmask; |
523 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set); |
524 |
#else
|
525 |
#warning No CPU specific signal handler: cannot handle target SIGSEGV events
|
526 |
return 0; |
527 |
#endif
|
528 |
} |