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/*
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* QEMU GT64120 PCI host
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*
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* Copyright (c) 2006,2007 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h" |
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#define GT_REGS (0x1000 >> 2) |
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|
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/* CPU Configuration */
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#define GT_CPU (0x000 >> 2) |
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#define GT_MULTI (0x120 >> 2) |
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|
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/* CPU Address Decode */
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#define GT_SCS10LD (0x008 >> 2) |
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#define GT_SCS10HD (0x010 >> 2) |
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#define GT_SCS32LD (0x018 >> 2) |
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#define GT_SCS32HD (0x020 >> 2) |
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#define GT_CS20LD (0x028 >> 2) |
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#define GT_CS20HD (0x030 >> 2) |
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#define GT_CS3BOOTLD (0x038 >> 2) |
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#define GT_CS3BOOTHD (0x040 >> 2) |
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#define GT_PCI0IOLD (0x048 >> 2) |
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#define GT_PCI0IOHD (0x050 >> 2) |
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#define GT_PCI0M0LD (0x058 >> 2) |
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#define GT_PCI0M0HD (0x060 >> 2) |
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#define GT_ISD (0x068 >> 2) |
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|
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#define GT_PCI0M1LD (0x080 >> 2) |
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#define GT_PCI0M1HD (0x088 >> 2) |
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#define GT_PCI1IOLD (0x090 >> 2) |
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#define GT_PCI1IOHD (0x098 >> 2) |
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#define GT_PCI1M0LD (0x0a0 >> 2) |
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#define GT_PCI1M0HD (0x0a8 >> 2) |
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#define GT_PCI1M1LD (0x0b0 >> 2) |
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#define GT_PCI1M1HD (0x0b8 >> 2) |
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#define GT_PCI1M1LD (0x0b0 >> 2) |
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#define GT_PCI1M1HD (0x0b8 >> 2) |
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|
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#define GT_SCS10AR (0x0d0 >> 2) |
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#define GT_SCS32AR (0x0d8 >> 2) |
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#define GT_CS20R (0x0e0 >> 2) |
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#define GT_CS3BOOTR (0x0e8 >> 2) |
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|
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#define GT_PCI0IOREMAP (0x0f0 >> 2) |
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#define GT_PCI0M0REMAP (0x0f8 >> 2) |
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#define GT_PCI0M1REMAP (0x100 >> 2) |
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#define GT_PCI1IOREMAP (0x108 >> 2) |
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#define GT_PCI1M0REMAP (0x110 >> 2) |
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#define GT_PCI1M1REMAP (0x118 >> 2) |
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|
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/* CPU Error Report */
|
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#define GT_CPUERR_ADDRLO (0x070 >> 2) |
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#define GT_CPUERR_ADDRHI (0x078 >> 2) |
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#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
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|
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/* CPU Sync Barrier */
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#define GT_PCI0SYNC (0x0c0 >> 2) |
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#define GT_PCI1SYNC (0x0c8 >> 2) |
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|
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/* SDRAM and Device Address Decode */
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#define GT_SCS0LD (0x400 >> 2) |
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#define GT_SCS0HD (0x404 >> 2) |
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#define GT_SCS1LD (0x408 >> 2) |
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#define GT_SCS1HD (0x40c >> 2) |
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#define GT_SCS2LD (0x410 >> 2) |
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#define GT_SCS2HD (0x414 >> 2) |
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#define GT_SCS3LD (0x418 >> 2) |
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#define GT_SCS3HD (0x41c >> 2) |
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#define GT_CS0LD (0x420 >> 2) |
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#define GT_CS0HD (0x424 >> 2) |
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#define GT_CS1LD (0x428 >> 2) |
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#define GT_CS1HD (0x42c >> 2) |
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#define GT_CS2LD (0x430 >> 2) |
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#define GT_CS2HD (0x434 >> 2) |
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#define GT_CS3LD (0x438 >> 2) |
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#define GT_CS3HD (0x43c >> 2) |
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#define GT_BOOTLD (0x440 >> 2) |
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#define GT_BOOTHD (0x444 >> 2) |
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#define GT_ADERR (0x470 >> 2) |
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|
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/* SDRAM Configuration */
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#define GT_SDRAM_CFG (0x448 >> 2) |
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#define GT_SDRAM_OPMODE (0x474 >> 2) |
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#define GT_SDRAM_BM (0x478 >> 2) |
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#define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
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|
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/* SDRAM Parameters */
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#define GT_SDRAM_B0 (0x44c >> 2) |
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#define GT_SDRAM_B1 (0x450 >> 2) |
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#define GT_SDRAM_B2 (0x454 >> 2) |
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#define GT_SDRAM_B3 (0x458 >> 2) |
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|
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/* Device Parameters */
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#define GT_DEV_B0 (0x45c >> 2) |
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#define GT_DEV_B1 (0x460 >> 2) |
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#define GT_DEV_B2 (0x464 >> 2) |
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#define GT_DEV_B3 (0x468 >> 2) |
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#define GT_DEV_BOOT (0x46c >> 2) |
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|
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/* ECC */
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#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
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#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
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#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
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/* DMA Record */
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#define GT_DMA0_CNT (0x800 >> 2) |
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#define GT_DMA1_CNT (0x804 >> 2) |
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#define GT_DMA2_CNT (0x808 >> 2) |
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#define GT_DMA3_CNT (0x80c >> 2) |
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#define GT_DMA0_SA (0x810 >> 2) |
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#define GT_DMA1_SA (0x814 >> 2) |
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#define GT_DMA2_SA (0x818 >> 2) |
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#define GT_DMA3_SA (0x81c >> 2) |
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#define GT_DMA0_DA (0x820 >> 2) |
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#define GT_DMA1_DA (0x824 >> 2) |
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#define GT_DMA2_DA (0x828 >> 2) |
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#define GT_DMA3_DA (0x82c >> 2) |
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#define GT_DMA0_NEXT (0x830 >> 2) |
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#define GT_DMA1_NEXT (0x834 >> 2) |
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#define GT_DMA2_NEXT (0x838 >> 2) |
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#define GT_DMA3_NEXT (0x83c >> 2) |
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#define GT_DMA0_CUR (0x870 >> 2) |
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#define GT_DMA1_CUR (0x874 >> 2) |
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#define GT_DMA2_CUR (0x878 >> 2) |
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#define GT_DMA3_CUR (0x87c >> 2) |
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/* DMA Channel Control */
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#define GT_DMA0_CTRL (0x840 >> 2) |
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#define GT_DMA1_CTRL (0x844 >> 2) |
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#define GT_DMA2_CTRL (0x848 >> 2) |
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#define GT_DMA3_CTRL (0x84c >> 2) |
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/* DMA Arbiter */
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#define GT_DMA_ARB (0x860 >> 2) |
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/* Timer/Counter */
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#define GT_TC0 (0x850 >> 2) |
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#define GT_TC1 (0x854 >> 2) |
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#define GT_TC2 (0x858 >> 2) |
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#define GT_TC3 (0x85c >> 2) |
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#define GT_TC_CONTROL (0x864 >> 2) |
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/* PCI Internal */
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#define GT_PCI0_CMD (0xc00 >> 2) |
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#define GT_PCI0_TOR (0xc04 >> 2) |
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#define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
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#define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
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#define GT_PCI0_BS_CS20 (0xc10 >> 2) |
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#define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
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#define GT_PCI1_IACK (0xc30 >> 2) |
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#define GT_PCI0_IACK (0xc34 >> 2) |
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#define GT_PCI0_BARE (0xc3c >> 2) |
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#define GT_PCI0_PREFMBR (0xc40 >> 2) |
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#define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
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#define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
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#define GT_PCI0_CS20_BAR (0xc50 >> 2) |
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#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
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#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
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#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
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#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
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#define GT_PCI1_CMD (0xc80 >> 2) |
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#define GT_PCI1_TOR (0xc84 >> 2) |
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#define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
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#define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
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#define GT_PCI1_BS_CS20 (0xc90 >> 2) |
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#define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
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#define GT_PCI1_BARE (0xcbc >> 2) |
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#define GT_PCI1_PREFMBR (0xcc0 >> 2) |
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#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
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#define GT_PCI1_SCS32_BAR (0xccc >> 2) |
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#define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
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#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
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#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
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#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
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#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
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#define GT_PCI1_CFGADDR (0xcf0 >> 2) |
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#define GT_PCI1_CFGDATA (0xcf4 >> 2) |
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#define GT_PCI0_CFGADDR (0xcf8 >> 2) |
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#define GT_PCI0_CFGDATA (0xcfc >> 2) |
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|
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/* Interrupts */
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#define GT_INTRCAUSE (0xc18 >> 2) |
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#define GT_INTRMASK (0xc1c >> 2) |
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#define GT_PCI0_ICMASK (0xc24 >> 2) |
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#define GT_PCI0_SERR0MASK (0xc28 >> 2) |
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#define GT_CPU_INTSEL (0xc70 >> 2) |
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#define GT_PCI0_INTSEL (0xc74 >> 2) |
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#define GT_HINTRCAUSE (0xc98 >> 2) |
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#define GT_HINTRMASK (0xc9c >> 2) |
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#define GT_PCI0_HICMASK (0xca4 >> 2) |
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#define GT_PCI1_SERR1MASK (0xca8 >> 2) |
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typedef PCIHostState GT64120PCIState;
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typedef struct GT64120State { |
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GT64120PCIState *pci; |
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uint32_t regs[GT_REGS]; |
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target_phys_addr_t PCI0IO_start; |
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target_phys_addr_t PCI0IO_length; |
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} GT64120State; |
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static void gt64120_pci_mapping(GT64120State *s) |
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{ |
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/* Update IO mapping */
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if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
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{ |
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/* Unmap old IO address */
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if (s->PCI0IO_length)
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{ |
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cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); |
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} |
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/* Map new IO address */
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s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
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s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
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isa_mem_base = s->PCI0IO_start; |
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isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
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} |
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} |
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|
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static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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GT64120State *s = opaque; |
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uint32_t saddr; |
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val); |
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#endif
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saddr = (addr & 0xfff) >> 2; |
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switch (saddr) {
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/* CPU Configuration */
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case GT_CPU:
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s->regs[GT_CPU] = val; |
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break;
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case GT_MULTI:
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/* Read-only register as only one GT64xxx is present on the CPU bus */
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break;
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|
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/* CPU Address Decode */
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case GT_PCI0IOLD:
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s->regs[GT_PCI0IOLD] = val & 0x00007fff;
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s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
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break;
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case GT_PCI0M0LD:
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s->regs[GT_PCI0M0LD] = val & 0x00007fff;
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s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
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break;
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case GT_PCI0M1LD:
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s->regs[GT_PCI0M1LD] = val & 0x00007fff;
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s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
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break;
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case GT_PCI1IOLD:
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s->regs[GT_PCI1IOLD] = val & 0x00007fff;
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s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
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break;
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case GT_PCI1M0LD:
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s->regs[GT_PCI1M0LD] = val & 0x00007fff;
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s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
293 |
break;
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case GT_PCI1M1LD:
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s->regs[GT_PCI1M1LD] = val & 0x00007fff;
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s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
298 |
break;
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case GT_PCI0IOHD:
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case GT_PCI0M0HD:
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case GT_PCI0M1HD:
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case GT_PCI1IOHD:
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case GT_PCI1M0HD:
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case GT_PCI1M1HD:
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s->regs[saddr] = val & 0x0000007f;
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gt64120_pci_mapping(s); |
307 |
break;
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case GT_PCI0IOREMAP:
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case GT_PCI0M0REMAP:
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case GT_PCI0M1REMAP:
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case GT_PCI1IOREMAP:
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case GT_PCI1M0REMAP:
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case GT_PCI1M1REMAP:
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s->regs[saddr] = val & 0x000007ff;
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gt64120_pci_mapping(s); |
316 |
break;
|
317 |
|
318 |
/* CPU Error Report */
|
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case GT_CPUERR_ADDRLO:
|
320 |
case GT_CPUERR_ADDRHI:
|
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case GT_CPUERR_DATALO:
|
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case GT_CPUERR_DATAHI:
|
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case GT_CPUERR_PARITY:
|
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/* Read-only registers, do nothing */
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break;
|
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|
327 |
/* CPU Sync Barrier */
|
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case GT_PCI0SYNC:
|
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case GT_PCI1SYNC:
|
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/* Read-only registers, do nothing */
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break;
|
332 |
|
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/* ECC */
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case GT_ECC_ERRDATALO:
|
335 |
case GT_ECC_ERRDATAHI:
|
336 |
case GT_ECC_MEM:
|
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case GT_ECC_CALC:
|
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case GT_ECC_ERRADDR:
|
339 |
/* Read-only registers, do nothing */
|
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break;
|
341 |
|
342 |
/* PCI Internal */
|
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case GT_PCI0_CMD:
|
344 |
case GT_PCI1_CMD:
|
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s->regs[saddr] = val & 0x0401fc0f;
|
346 |
break;
|
347 |
case GT_PCI0_CFGADDR:
|
348 |
s->pci->config_reg = val & 0x80fffffc;
|
349 |
break;
|
350 |
case GT_PCI0_CFGDATA:
|
351 |
pci_host_data_writel(s->pci, 0, val);
|
352 |
break;
|
353 |
|
354 |
/* SDRAM Parameters */
|
355 |
case GT_SDRAM_B0:
|
356 |
case GT_SDRAM_B1:
|
357 |
case GT_SDRAM_B2:
|
358 |
case GT_SDRAM_B3:
|
359 |
/* We don't simulate electrical parameters of the SDRAM.
|
360 |
Accept, but ignore the values. */
|
361 |
s->regs[saddr] = val; |
362 |
break;
|
363 |
|
364 |
default:
|
365 |
#if 0
|
366 |
printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
|
367 |
#endif
|
368 |
break;
|
369 |
} |
370 |
} |
371 |
|
372 |
static uint32_t gt64120_readl (void *opaque, |
373 |
target_phys_addr_t addr) |
374 |
{ |
375 |
GT64120State *s = opaque; |
376 |
uint32_t val; |
377 |
uint32_t saddr; |
378 |
|
379 |
val = 0;
|
380 |
saddr = (addr & 0xfff) >> 2; |
381 |
|
382 |
switch (saddr) {
|
383 |
|
384 |
/* CPU Configuration */
|
385 |
case GT_MULTI:
|
386 |
/* Only one GT64xxx is present on the CPU bus, return
|
387 |
the initial value */
|
388 |
val = s->regs[saddr]; |
389 |
break;
|
390 |
|
391 |
/* CPU Error Report */
|
392 |
case GT_CPUERR_ADDRLO:
|
393 |
case GT_CPUERR_ADDRHI:
|
394 |
case GT_CPUERR_DATALO:
|
395 |
case GT_CPUERR_DATAHI:
|
396 |
case GT_CPUERR_PARITY:
|
397 |
/* Emulated memory has no error, always return the initial
|
398 |
values */
|
399 |
val = s->regs[saddr]; |
400 |
break;
|
401 |
|
402 |
/* CPU Sync Barrier */
|
403 |
case GT_PCI0SYNC:
|
404 |
case GT_PCI1SYNC:
|
405 |
/* Reading those register should empty all FIFO on the PCI
|
406 |
bus, which are not emulated. The return value should be
|
407 |
a random value that should be ignored. */
|
408 |
val = 0xc000ffee;
|
409 |
break;
|
410 |
|
411 |
/* ECC */
|
412 |
case GT_ECC_ERRDATALO:
|
413 |
case GT_ECC_ERRDATAHI:
|
414 |
case GT_ECC_MEM:
|
415 |
case GT_ECC_CALC:
|
416 |
case GT_ECC_ERRADDR:
|
417 |
/* Emulated memory has no error, always return the initial
|
418 |
values */
|
419 |
val = s->regs[saddr]; |
420 |
break;
|
421 |
|
422 |
case GT_CPU:
|
423 |
case GT_PCI0IOLD:
|
424 |
case GT_PCI0M0LD:
|
425 |
case GT_PCI0M1LD:
|
426 |
case GT_PCI1IOLD:
|
427 |
case GT_PCI1M0LD:
|
428 |
case GT_PCI1M1LD:
|
429 |
case GT_PCI0IOHD:
|
430 |
case GT_PCI0M0HD:
|
431 |
case GT_PCI0M1HD:
|
432 |
case GT_PCI1IOHD:
|
433 |
case GT_PCI1M0HD:
|
434 |
case GT_PCI1M1HD:
|
435 |
case GT_PCI0_CMD:
|
436 |
case GT_PCI1_CMD:
|
437 |
case GT_PCI0IOREMAP:
|
438 |
case GT_PCI0M0REMAP:
|
439 |
case GT_PCI0M1REMAP:
|
440 |
case GT_PCI1IOREMAP:
|
441 |
case GT_PCI1M0REMAP:
|
442 |
case GT_PCI1M1REMAP:
|
443 |
val = s->regs[saddr]; |
444 |
break;
|
445 |
case GT_PCI0_IACK:
|
446 |
/* Read the IRQ number */
|
447 |
val = pic_read_irq(isa_pic); |
448 |
break;
|
449 |
|
450 |
/* SDRAM Parameters */
|
451 |
case GT_SDRAM_B0:
|
452 |
case GT_SDRAM_B1:
|
453 |
case GT_SDRAM_B2:
|
454 |
case GT_SDRAM_B3:
|
455 |
/* We don't simulate electrical parameters of the SDRAM.
|
456 |
Just return the last written value. */
|
457 |
val = s->regs[saddr]; |
458 |
break;
|
459 |
|
460 |
/* PCI Internal */
|
461 |
case GT_PCI0_CFGADDR:
|
462 |
val = s->pci->config_reg; |
463 |
break;
|
464 |
case GT_PCI0_CFGDATA:
|
465 |
val = pci_host_data_readl(s->pci, 0);
|
466 |
break;
|
467 |
|
468 |
default:
|
469 |
val = s->regs[saddr]; |
470 |
#if 0
|
471 |
printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
|
472 |
#endif
|
473 |
break;
|
474 |
} |
475 |
|
476 |
#ifdef TARGET_WORDS_BIGENDIAN
|
477 |
return bswap32(val);
|
478 |
#else
|
479 |
return val;
|
480 |
#endif
|
481 |
} |
482 |
|
483 |
static CPUWriteMemoryFunc *gt64120_write[] = {
|
484 |
>64120_writel, |
485 |
>64120_writel, |
486 |
>64120_writel, |
487 |
}; |
488 |
|
489 |
static CPUReadMemoryFunc *gt64120_read[] = {
|
490 |
>64120_readl, |
491 |
>64120_readl, |
492 |
>64120_readl, |
493 |
}; |
494 |
|
495 |
static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) |
496 |
{ |
497 |
int slot;
|
498 |
|
499 |
slot = (pci_dev->devfn >> 3);
|
500 |
|
501 |
switch (slot) {
|
502 |
/* PIIX4 USB */
|
503 |
case 10: |
504 |
return 3; |
505 |
/* AMD 79C973 Ethernet */
|
506 |
case 11: |
507 |
return 0; |
508 |
/* Crystal 4281 Sound */
|
509 |
case 12: |
510 |
return 0; |
511 |
/* PCI slot 1 to 4 */
|
512 |
case 18 ... 21: |
513 |
return ((slot - 18) + irq_num) & 0x03; |
514 |
/* Unknown device, don't do any translation */
|
515 |
default:
|
516 |
return irq_num;
|
517 |
} |
518 |
} |
519 |
|
520 |
extern PCIDevice *piix4_dev;
|
521 |
static int pci_irq_levels[4]; |
522 |
|
523 |
static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level) |
524 |
{ |
525 |
int i, pic_irq, pic_level;
|
526 |
|
527 |
pci_irq_levels[irq_num] = level; |
528 |
|
529 |
/* now we change the pic irq level according to the piix irq mappings */
|
530 |
/* XXX: optimize */
|
531 |
pic_irq = piix4_dev->config[0x60 + irq_num];
|
532 |
if (pic_irq < 16) { |
533 |
/* The pic level is the logical OR of all the PCI irqs mapped
|
534 |
to it */
|
535 |
pic_level = 0;
|
536 |
for (i = 0; i < 4; i++) { |
537 |
if (pic_irq == piix4_dev->config[0x60 + i]) |
538 |
pic_level |= pci_irq_levels[i]; |
539 |
} |
540 |
qemu_set_irq(pic[pic_irq], pic_level); |
541 |
} |
542 |
} |
543 |
|
544 |
|
545 |
void gt64120_reset(void *opaque) |
546 |
{ |
547 |
GT64120State *s = opaque; |
548 |
|
549 |
/* CPU Configuration */
|
550 |
#ifdef TARGET_WORDS_BIGENDIAN
|
551 |
s->regs[GT_CPU] = 0x00000000;
|
552 |
#else
|
553 |
s->regs[GT_CPU] = 0x00001000;
|
554 |
#endif
|
555 |
s->regs[GT_MULTI] = 0x00000000;
|
556 |
|
557 |
/* CPU Address decode FIXME: not complete*/
|
558 |
s->regs[GT_PCI0IOLD] = 0x00000080;
|
559 |
s->regs[GT_PCI0IOHD] = 0x0000000f;
|
560 |
s->regs[GT_PCI0M0LD] = 0x00000090;
|
561 |
s->regs[GT_PCI0M0HD] = 0x0000001f;
|
562 |
s->regs[GT_PCI0M1LD] = 0x00000790;
|
563 |
s->regs[GT_PCI0M1HD] = 0x0000001f;
|
564 |
s->regs[GT_PCI1IOLD] = 0x00000100;
|
565 |
s->regs[GT_PCI1IOHD] = 0x0000000f;
|
566 |
s->regs[GT_PCI1M0LD] = 0x00000110;
|
567 |
s->regs[GT_PCI1M0HD] = 0x0000001f;
|
568 |
s->regs[GT_PCI1M1LD] = 0x00000120;
|
569 |
s->regs[GT_PCI1M1HD] = 0x0000002f;
|
570 |
s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
571 |
s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
572 |
s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
573 |
s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
574 |
s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
575 |
s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
576 |
|
577 |
/* CPU Error Report */
|
578 |
s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
579 |
s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
580 |
s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
581 |
s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
582 |
s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
583 |
|
584 |
/* ECC */
|
585 |
s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
586 |
s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
587 |
s->regs[GT_ECC_MEM] = 0x00000000;
|
588 |
s->regs[GT_ECC_CALC] = 0x00000000;
|
589 |
s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
590 |
|
591 |
/* SDRAM Parameters */
|
592 |
s->regs[GT_SDRAM_B0] = 0x00000005;
|
593 |
s->regs[GT_SDRAM_B1] = 0x00000005;
|
594 |
s->regs[GT_SDRAM_B2] = 0x00000005;
|
595 |
s->regs[GT_SDRAM_B3] = 0x00000005;
|
596 |
|
597 |
/* PCI Internal FIXME: not complete*/
|
598 |
#ifdef TARGET_WORDS_BIGENDIAN
|
599 |
s->regs[GT_PCI0_CMD] = 0x00000000;
|
600 |
s->regs[GT_PCI1_CMD] = 0x00000000;
|
601 |
#else
|
602 |
s->regs[GT_PCI0_CMD] = 0x00010001;
|
603 |
s->regs[GT_PCI1_CMD] = 0x00010001;
|
604 |
#endif
|
605 |
s->regs[GT_PCI0_IACK] = 0x00000000;
|
606 |
s->regs[GT_PCI1_IACK] = 0x00000000;
|
607 |
|
608 |
gt64120_pci_mapping(s); |
609 |
} |
610 |
|
611 |
static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len) |
612 |
{ |
613 |
uint32_t val = pci_default_read_config(d, address, len); |
614 |
#ifdef TARGET_WORDS_BIGENDIAN
|
615 |
val = bswap32(val); |
616 |
#endif
|
617 |
return val;
|
618 |
} |
619 |
|
620 |
static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val, |
621 |
int len)
|
622 |
{ |
623 |
#ifdef TARGET_WORDS_BIGENDIAN
|
624 |
val = bswap32(val); |
625 |
#endif
|
626 |
pci_default_write_config(d, address, val, len); |
627 |
} |
628 |
|
629 |
PCIBus *pci_gt64120_init(qemu_irq *pic) |
630 |
{ |
631 |
GT64120State *s; |
632 |
PCIDevice *d; |
633 |
int gt64120;
|
634 |
|
635 |
s = qemu_mallocz(sizeof(GT64120State));
|
636 |
s->pci = qemu_mallocz(sizeof(GT64120PCIState));
|
637 |
gt64120_reset(s); |
638 |
|
639 |
s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
640 |
pic, 144, 4); |
641 |
|
642 |
gt64120 = cpu_register_io_memory(0, gt64120_read,
|
643 |
gt64120_write, s); |
644 |
cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120); |
645 |
|
646 |
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
647 |
0, gt64120_read_config, gt64120_write_config);
|
648 |
|
649 |
d->config[0x00] = 0xab; // vendor_id |
650 |
d->config[0x01] = 0x11; |
651 |
d->config[0x02] = 0x20; // device_id |
652 |
d->config[0x03] = 0x46; |
653 |
d->config[0x04] = 0x06; |
654 |
d->config[0x05] = 0x00; |
655 |
d->config[0x06] = 0x80; |
656 |
d->config[0x07] = 0xa2; |
657 |
d->config[0x08] = 0x10; |
658 |
d->config[0x09] = 0x00; |
659 |
d->config[0x0A] = 0x80; |
660 |
d->config[0x0B] = 0x05; |
661 |
d->config[0x0C] = 0x08; |
662 |
d->config[0x0D] = 0x40; |
663 |
d->config[0x0E] = 0x00; |
664 |
d->config[0x0F] = 0x00; |
665 |
d->config[0x17] = 0x08; |
666 |
d->config[0x1B] = 0x1c; |
667 |
d->config[0x1F] = 0x1f; |
668 |
d->config[0x23] = 0x14; |
669 |
d->config[0x27] = 0x14; |
670 |
d->config[0x3D] = 0x01; |
671 |
|
672 |
return s->pci->bus;
|
673 |
} |