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/*
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* Intel XScale PXA255/270 processor support.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licenced under the GPL.
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*/
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#ifndef PXA_H
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# define PXA_H "pxa.h" |
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/* Interrupt numbers */
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# define PXA2XX_PIC_SSP3 0 |
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# define PXA2XX_PIC_USBH2 2 |
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# define PXA2XX_PIC_USBH1 3 |
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# define PXA2XX_PIC_PWRI2C 6 |
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# define PXA25X_PIC_HWUART 7 |
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# define PXA27X_PIC_OST_4_11 7 |
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# define PXA2XX_PIC_GPIO_0 8 |
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# define PXA2XX_PIC_GPIO_1 9 |
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# define PXA2XX_PIC_GPIO_X 10 |
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# define PXA2XX_PIC_I2S 13 |
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# define PXA26X_PIC_ASSP 15 |
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# define PXA25X_PIC_NSSP 16 |
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# define PXA27X_PIC_SSP2 16 |
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# define PXA2XX_PIC_LCD 17 |
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# define PXA2XX_PIC_I2C 18 |
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# define PXA2XX_PIC_ICP 19 |
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# define PXA2XX_PIC_STUART 20 |
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# define PXA2XX_PIC_BTUART 21 |
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# define PXA2XX_PIC_FFUART 22 |
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# define PXA2XX_PIC_MMC 23 |
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# define PXA2XX_PIC_SSP 24 |
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# define PXA2XX_PIC_DMA 25 |
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# define PXA2XX_PIC_OST_0 26 |
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# define PXA2XX_PIC_RTC1HZ 30 |
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# define PXA2XX_PIC_RTCALARM 31 |
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/* DMA requests */
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# define PXA2XX_RX_RQ_I2S 2 |
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# define PXA2XX_TX_RQ_I2S 3 |
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# define PXA2XX_RX_RQ_BTUART 4 |
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# define PXA2XX_TX_RQ_BTUART 5 |
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# define PXA2XX_RX_RQ_FFUART 6 |
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# define PXA2XX_TX_RQ_FFUART 7 |
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# define PXA2XX_RX_RQ_SSP1 13 |
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# define PXA2XX_TX_RQ_SSP1 14 |
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# define PXA2XX_RX_RQ_SSP2 15 |
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# define PXA2XX_TX_RQ_SSP2 16 |
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# define PXA2XX_RX_RQ_ICP 17 |
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# define PXA2XX_TX_RQ_ICP 18 |
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# define PXA2XX_RX_RQ_STUART 19 |
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# define PXA2XX_TX_RQ_STUART 20 |
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# define PXA2XX_RX_RQ_MMCI 21 |
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# define PXA2XX_TX_RQ_MMCI 22 |
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# define PXA2XX_USB_RQ(x) ((x) + 24) |
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# define PXA2XX_RX_RQ_SSP3 66 |
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# define PXA2XX_TX_RQ_SSP3 67 |
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# define PXA2XX_SDRAM_BASE 0xa0000000 |
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# define PXA2XX_INTERNAL_BASE 0x5c000000 |
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/* pxa2xx_pic.c */
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struct pxa2xx_pic_state_s;
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); |
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/* pxa2xx_timer.c */
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void pxa25x_timer_init(target_phys_addr_t base,
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qemu_irq *irqs, CPUState *cpustate); |
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void pxa27x_timer_init(target_phys_addr_t base,
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qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate); |
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/* pxa2xx_gpio.c */
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struct pxa2xx_gpio_info_s;
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struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, qemu_irq *pic, int lines);
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void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level); |
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void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line, |
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gpio_handler_t handler, void *opaque);
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void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, |
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void (*handler)(void *opaque), void *opaque); |
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/* pxa2xx_dma.c */
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struct pxa2xx_dma_state_s;
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struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
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qemu_irq irq); |
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struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
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qemu_irq irq); |
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void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on); |
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/* pxa2xx_lcd.c */
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struct pxa2xx_lcdc_s;
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struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
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qemu_irq irq, DisplayState *ds); |
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void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s, |
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void (*cb)(void *opaque), void *opaque); |
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void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
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/* pxa2xx_mmci.c */
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struct pxa2xx_mmci_s;
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struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
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qemu_irq irq, void *dma);
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void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque, |
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void (*readonly_cb)(void *, int), |
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void (*coverswitch_cb)(void *, int)); |
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/* pxa2xx_pcmcia.c */
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struct pxa2xx_pcmcia_s;
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struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
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int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card); |
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int pxa2xx_pcmcia_dettach(void *opaque); |
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void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
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/* pxa2xx.c */
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struct pxa2xx_ssp_s;
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void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, |
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uint32_t (*readfn)(void *opaque),
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void (*writefn)(void *opaque, uint32_t value), void *opaque); |
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struct pxa2xx_i2s_s;
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struct pxa2xx_fir_s;
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struct pxa2xx_state_s {
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CPUState *env; |
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qemu_irq *pic; |
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struct pxa2xx_dma_state_s *dma;
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struct pxa2xx_gpio_info_s *gpio;
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struct pxa2xx_lcdc_s *lcd;
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struct pxa2xx_ssp_s **ssp;
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struct pxa2xx_mmci_s *mmc;
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struct pxa2xx_pcmcia_s *pcmcia[2]; |
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struct pxa2xx_i2s_s *i2s;
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struct pxa2xx_fir_s *fir;
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/* Power management */
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target_phys_addr_t pm_base; |
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uint32_t pm_regs[0x40];
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/* Clock management */
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target_phys_addr_t cm_base; |
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uint32_t cm_regs[4];
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uint32_t clkcfg; |
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/* Memory management */
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target_phys_addr_t mm_base; |
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uint32_t mm_regs[0x1a];
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/* Performance monitoring */
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uint32_t pmnc; |
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/* Real-Time clock */
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target_phys_addr_t rtc_base; |
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uint32_t rttr; |
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uint32_t rtsr; |
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uint32_t rtar; |
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uint32_t rdar1; |
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uint32_t rdar2; |
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uint32_t ryar1; |
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uint32_t ryar2; |
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uint32_t swar1; |
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uint32_t swar2; |
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uint32_t piar; |
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uint32_t last_rcnr; |
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uint32_t last_rdcr; |
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uint32_t last_rycr; |
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uint32_t last_swcr; |
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uint32_t last_rtcpicr; |
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int64_t last_hz; |
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int64_t last_sw; |
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int64_t last_pi; |
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QEMUTimer *rtc_hz; |
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QEMUTimer *rtc_rdal1; |
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QEMUTimer *rtc_rdal2; |
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QEMUTimer *rtc_swal1; |
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QEMUTimer *rtc_swal2; |
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QEMUTimer *rtc_pi; |
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}; |
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struct pxa2xx_i2s_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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struct pxa2xx_dma_state_s *dma;
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void (*data_req)(void *, int, int); |
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uint32_t control[2];
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uint32_t status; |
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uint32_t mask; |
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uint32_t clk; |
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int enable;
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int rx_len;
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int tx_len;
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void (*codec_out)(void *, uint32_t); |
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uint32_t (*codec_in)(void *);
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void *opaque;
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int fifo_len;
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uint32_t fifo[16];
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}; |
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# define PA_FMT "0x%08lx" |
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# define REG_FMT "0x%lx" |
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struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds, |
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const char *revision); |
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struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds); |
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void pxa2xx_reset(int line, int level, void *opaque); |
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#endif /* PXA_H */ |