Revision 56aebc89 gdbstub.c
| b/gdbstub.c | ||
|---|---|---|
| 18 | 18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | 19 |
*/ |
| 20 | 20 |
#include "config.h" |
| 21 |
#include "qemu-common.h" |
|
| 21 | 22 |
#ifdef CONFIG_USER_ONLY |
| 22 | 23 |
#include <stdlib.h> |
| 23 | 24 |
#include <stdio.h> |
| ... | ... | |
| 29 | 30 |
|
| 30 | 31 |
#include "qemu.h" |
| 31 | 32 |
#else |
| 32 |
#include "qemu-common.h" |
|
| 33 | 33 |
#include "qemu-char.h" |
| 34 | 34 |
#include "sysemu.h" |
| 35 | 35 |
#include "gdbstub.h" |
| 36 | 36 |
#endif |
| 37 | 37 |
|
| 38 |
#define MAX_PACKET_LENGTH 4096 |
|
| 39 |
|
|
| 38 | 40 |
#include "qemu_socket.h" |
| 39 | 41 |
#ifdef _WIN32 |
| 40 | 42 |
/* XXX: these constants may be independent of the host ones even for Unix */ |
| ... | ... | |
| 50 | 52 |
|
| 51 | 53 |
//#define DEBUG_GDB |
| 52 | 54 |
|
| 55 |
typedef struct GDBRegisterState {
|
|
| 56 |
int base_reg; |
|
| 57 |
int num_regs; |
|
| 58 |
gdb_reg_cb get_reg; |
|
| 59 |
gdb_reg_cb set_reg; |
|
| 60 |
const char *xml; |
|
| 61 |
struct GDBRegisterState *next; |
|
| 62 |
} GDBRegisterState; |
|
| 63 |
|
|
| 53 | 64 |
enum RSState {
|
| 54 | 65 |
RS_IDLE, |
| 55 | 66 |
RS_GETLINE, |
| ... | ... | |
| 60 | 71 |
typedef struct GDBState {
|
| 61 | 72 |
CPUState *env; /* current CPU */ |
| 62 | 73 |
enum RSState state; /* parsing state */ |
| 63 |
char line_buf[4096];
|
|
| 74 |
char line_buf[MAX_PACKET_LENGTH];
|
|
| 64 | 75 |
int line_buf_index; |
| 65 | 76 |
int line_csum; |
| 66 |
uint8_t last_packet[4100];
|
|
| 77 |
uint8_t last_packet[MAX_PACKET_LENGTH + 4];
|
|
| 67 | 78 |
int last_packet_len; |
| 68 | 79 |
int signal; |
| 69 | 80 |
#ifdef CONFIG_USER_ONLY |
| ... | ... | |
| 79 | 90 |
*/ |
| 80 | 91 |
static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; |
| 81 | 92 |
|
| 93 |
/* This is an ugly hack to cope with both new and old gdb. |
|
| 94 |
If gdb sends qXfer:features:read then assume we're talking to a newish |
|
| 95 |
gdb that understands target descriptions. */ |
|
| 96 |
static int gdb_has_xml; |
|
| 97 |
|
|
| 82 | 98 |
#ifdef CONFIG_USER_ONLY |
| 83 | 99 |
/* XXX: This is not thread safe. Do we care? */ |
| 84 | 100 |
static int gdbserver_fd = -1; |
| ... | ... | |
| 205 | 221 |
} |
| 206 | 222 |
|
| 207 | 223 |
/* return -1 if error, 0 if OK */ |
| 208 |
static int put_packet(GDBState *s, const char *buf)
|
|
| 224 |
static int put_packet_binary(GDBState *s, const char *buf, int len)
|
|
| 209 | 225 |
{
|
| 210 |
int len, csum, i;
|
|
| 226 |
int csum, i; |
|
| 211 | 227 |
uint8_t *p; |
| 212 | 228 |
|
| 213 |
#ifdef DEBUG_GDB |
|
| 214 |
printf("reply='%s'\n", buf);
|
|
| 215 |
#endif |
|
| 216 |
|
|
| 217 | 229 |
for(;;) {
|
| 218 | 230 |
p = s->last_packet; |
| 219 | 231 |
*(p++) = '$'; |
| 220 |
len = strlen(buf); |
|
| 221 | 232 |
memcpy(p, buf, len); |
| 222 | 233 |
p += len; |
| 223 | 234 |
csum = 0; |
| ... | ... | |
| 244 | 255 |
return 0; |
| 245 | 256 |
} |
| 246 | 257 |
|
| 247 |
#if defined(TARGET_I386) |
|
| 258 |
/* return -1 if error, 0 if OK */ |
|
| 259 |
static int put_packet(GDBState *s, const char *buf) |
|
| 260 |
{
|
|
| 261 |
#ifdef DEBUG_GDB |
|
| 262 |
printf("reply='%s'\n", buf);
|
|
| 263 |
#endif |
|
| 248 | 264 |
|
| 249 |
#ifdef TARGET_X86_64 |
|
| 250 |
static const uint8_t gdb_x86_64_regs[16] = {
|
|
| 251 |
R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, |
|
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8, 9, 10, 11, 12, 13, 14, 15, |
|
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}; |
|
| 265 |
return put_packet_binary(s, buf, strlen(buf)); |
|
| 266 |
} |
|
| 267 |
|
|
| 268 |
/* The GDB remote protocol transfers values in target byte order. This means |
|
| 269 |
we can use the raw memory access routines to access the value buffer. |
|
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Conveniently, these also handle the case where the buffer is mis-aligned. |
|
| 271 |
*/ |
|
| 272 |
#define GET_REG8(val) do { \
|
|
| 273 |
stb_p(mem_buf, val); \ |
|
| 274 |
return 1; \ |
|
| 275 |
} while(0) |
|
| 276 |
#define GET_REG16(val) do { \
|
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| 277 |
stw_p(mem_buf, val); \ |
|
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return 2; \ |
|
| 279 |
} while(0) |
|
| 280 |
#define GET_REG32(val) do { \
|
|
| 281 |
stl_p(mem_buf, val); \ |
|
| 282 |
return 4; \ |
|
| 283 |
} while(0) |
|
| 284 |
#define GET_REG64(val) do { \
|
|
| 285 |
stq_p(mem_buf, val); \ |
|
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return 8; \ |
|
| 287 |
} while(0) |
|
| 288 |
|
|
| 289 |
#if TARGET_LONG_BITS == 64 |
|
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#define GET_REGL(val) GET_REG64(val) |
|
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#define ldtul_p(addr) ldq_p(addr) |
|
| 292 |
#else |
|
| 293 |
#define GET_REGL(val) GET_REG32(val) |
|
| 294 |
#define ldtul_p(addr) ldl_p(addr) |
|
| 254 | 295 |
#endif |
| 255 | 296 |
|
| 256 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 257 |
{
|
|
| 258 |
int i, fpus, nb_regs; |
|
| 259 |
uint8_t *p; |
|
| 297 |
#if defined(TARGET_I386) |
|
| 260 | 298 |
|
| 261 |
p = mem_buf; |
|
| 262 | 299 |
#ifdef TARGET_X86_64 |
| 263 |
if (env->hflags & HF_CS64_MASK) {
|
|
| 264 |
nb_regs = 16; |
|
| 265 |
for(i = 0; i < 16; i++) {
|
|
| 266 |
*(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]); |
|
| 267 |
p += 8; |
|
| 268 |
} |
|
| 269 |
*(uint64_t *)p = tswap64(env->eip); |
|
| 270 |
p += 8; |
|
| 271 |
} else |
|
| 272 |
#endif |
|
| 273 |
{
|
|
| 274 |
nb_regs = 8; |
|
| 275 |
for(i = 0; i < 8; i++) {
|
|
| 276 |
*(uint32_t *)p = tswap32(env->regs[i]); |
|
| 277 |
p += 4; |
|
| 278 |
} |
|
| 279 |
*(uint32_t *)p = tswap32(env->eip); |
|
| 280 |
p += 4; |
|
| 281 |
} |
|
| 282 |
|
|
| 283 |
*(uint32_t *)p = tswap32(env->eflags); |
|
| 284 |
p += 4; |
|
| 285 |
*(uint32_t *)p = tswap32(env->segs[R_CS].selector); |
|
| 286 |
p += 4; |
|
| 287 |
*(uint32_t *)p = tswap32(env->segs[R_SS].selector); |
|
| 288 |
p += 4; |
|
| 289 |
*(uint32_t *)p = tswap32(env->segs[R_DS].selector); |
|
| 290 |
p += 4; |
|
| 291 |
*(uint32_t *)p = tswap32(env->segs[R_ES].selector); |
|
| 292 |
p += 4; |
|
| 293 |
*(uint32_t *)p = tswap32(env->segs[R_FS].selector); |
|
| 294 |
p += 4; |
|
| 295 |
*(uint32_t *)p = tswap32(env->segs[R_GS].selector); |
|
| 296 |
p += 4; |
|
| 297 |
for(i = 0; i < 8; i++) {
|
|
| 298 |
/* XXX: convert floats */ |
|
| 299 |
#ifdef USE_X86LDOUBLE |
|
| 300 |
memcpy(p, &env->fpregs[i], 10); |
|
| 300 |
static const int gpr_map[16] = {
|
|
| 301 |
R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, |
|
| 302 |
8, 9, 10, 11, 12, 13, 14, 15 |
|
| 303 |
}; |
|
| 301 | 304 |
#else |
| 302 |
memset(p, 0, 10);
|
|
| 305 |
static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
|
|
| 303 | 306 |
#endif |
| 304 |
p += 10; |
|
| 305 |
} |
|
| 306 |
*(uint32_t *)p = tswap32(env->fpuc); /* fctrl */ |
|
| 307 |
p += 4; |
|
| 308 |
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
|
| 309 |
*(uint32_t *)p = tswap32(fpus); /* fstat */ |
|
| 310 |
p += 4; |
|
| 311 |
*(uint32_t *)p = 0; /* ftag */ |
|
| 312 |
p += 4; |
|
| 313 |
*(uint32_t *)p = 0; /* fiseg */ |
|
| 314 |
p += 4; |
|
| 315 |
*(uint32_t *)p = 0; /* fioff */ |
|
| 316 |
p += 4; |
|
| 317 |
*(uint32_t *)p = 0; /* foseg */ |
|
| 318 |
p += 4; |
|
| 319 |
*(uint32_t *)p = 0; /* fooff */ |
|
| 320 |
p += 4; |
|
| 321 |
*(uint32_t *)p = 0; /* fop */ |
|
| 322 |
p += 4; |
|
| 323 |
for(i = 0; i < nb_regs; i++) {
|
|
| 324 |
*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0)); |
|
| 325 |
p += 8; |
|
| 326 |
*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1)); |
|
| 327 |
p += 8; |
|
| 328 |
} |
|
| 329 |
*(uint32_t *)p = tswap32(env->mxcsr); |
|
| 330 |
p += 4; |
|
| 331 |
return p - mem_buf; |
|
| 332 |
} |
|
| 333 | 307 |
|
| 334 |
static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp, |
|
| 335 |
int sreg) |
|
| 308 |
#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25) |
|
| 309 |
|
|
| 310 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 336 | 311 |
{
|
| 337 |
const uint8_t *p; |
|
| 338 |
uint32_t sel; |
|
| 339 |
p = *pp; |
|
| 340 |
sel = tswap32(*(uint32_t *)p); |
|
| 341 |
p += 4; |
|
| 342 |
if (sel != env->segs[sreg].selector) {
|
|
| 343 |
#if defined(CONFIG_USER_ONLY) |
|
| 344 |
cpu_x86_load_seg(env, sreg, sel); |
|
| 312 |
if (n < CPU_NB_REGS) {
|
|
| 313 |
GET_REGL(env->regs[gpr_map[n]]); |
|
| 314 |
} else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
|
|
| 315 |
/* FIXME: byteswap float values. */ |
|
| 316 |
#ifdef USE_X86LDOUBLE |
|
| 317 |
memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10); |
|
| 345 | 318 |
#else |
| 346 |
/* XXX: do it with a debug function which does not raise an |
|
| 347 |
exception */ |
|
| 319 |
memset(mem_buf, 0, 10); |
|
| 348 | 320 |
#endif |
| 321 |
return 10; |
|
| 322 |
} else if (n >= CPU_NB_REGS + 24) {
|
|
| 323 |
n -= CPU_NB_REGS + 24; |
|
| 324 |
if (n < CPU_NB_REGS) {
|
|
| 325 |
stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); |
|
| 326 |
stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); |
|
| 327 |
return 16; |
|
| 328 |
} else if (n == CPU_NB_REGS) {
|
|
| 329 |
GET_REG32(env->mxcsr); |
|
| 330 |
} |
|
| 331 |
} else {
|
|
| 332 |
n -= CPU_NB_REGS; |
|
| 333 |
switch (n) {
|
|
| 334 |
case 0: GET_REGL(env->eip); |
|
| 335 |
case 1: GET_REG32(env->eflags); |
|
| 336 |
case 2: GET_REG32(env->segs[R_CS].selector); |
|
| 337 |
case 3: GET_REG32(env->segs[R_SS].selector); |
|
| 338 |
case 4: GET_REG32(env->segs[R_DS].selector); |
|
| 339 |
case 5: GET_REG32(env->segs[R_ES].selector); |
|
| 340 |
case 6: GET_REG32(env->segs[R_FS].selector); |
|
| 341 |
case 7: GET_REG32(env->segs[R_GS].selector); |
|
| 342 |
/* 8...15 x87 regs. */ |
|
| 343 |
case 16: GET_REG32(env->fpuc); |
|
| 344 |
case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11); |
|
| 345 |
case 18: GET_REG32(0); /* ftag */ |
|
| 346 |
case 19: GET_REG32(0); /* fiseg */ |
|
| 347 |
case 20: GET_REG32(0); /* fioff */ |
|
| 348 |
case 21: GET_REG32(0); /* foseg */ |
|
| 349 |
case 22: GET_REG32(0); /* fooff */ |
|
| 350 |
case 23: GET_REG32(0); /* fop */ |
|
| 351 |
/* 24+ xmm regs. */ |
|
| 352 |
} |
|
| 349 | 353 |
} |
| 350 |
*pp = p;
|
|
| 354 |
return 0;
|
|
| 351 | 355 |
} |
| 352 | 356 |
|
| 353 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 357 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
|
|
| 354 | 358 |
{
|
| 355 |
const uint8_t *p = mem_buf; |
|
| 356 |
int i, nb_regs; |
|
| 357 |
uint16_t fpus; |
|
| 359 |
uint32_t tmp; |
|
| 358 | 360 |
|
| 359 |
#ifdef TARGET_X86_64 |
|
| 360 |
if (env->hflags & HF_CS64_MASK) {
|
|
| 361 |
nb_regs = 16; |
|
| 362 |
for(i = 0; i < 16; i++) {
|
|
| 363 |
env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p); |
|
| 364 |
p += 8; |
|
| 365 |
} |
|
| 366 |
env->eip = tswap64(*(uint64_t *)p); |
|
| 367 |
p += 8; |
|
| 368 |
} else |
|
| 361 |
if (i < CPU_NB_REGS) {
|
|
| 362 |
env->regs[gpr_map[i]] = ldtul_p(mem_buf); |
|
| 363 |
return sizeof(target_ulong); |
|
| 364 |
} else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
|
|
| 365 |
i -= CPU_NB_REGS + 8; |
|
| 366 |
#ifdef USE_X86LDOUBLE |
|
| 367 |
memcpy(&env->fpregs[i], mem_buf, 10); |
|
| 369 | 368 |
#endif |
| 370 |
{
|
|
| 371 |
nb_regs = 8; |
|
| 372 |
for(i = 0; i < 8; i++) {
|
|
| 373 |
env->regs[i] = tswap32(*(uint32_t *)p); |
|
| 374 |
p += 4; |
|
| 369 |
return 10; |
|
| 370 |
} else if (i >= CPU_NB_REGS + 24) {
|
|
| 371 |
i -= CPU_NB_REGS + 24; |
|
| 372 |
if (i < CPU_NB_REGS) {
|
|
| 373 |
env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf); |
|
| 374 |
env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8); |
|
| 375 |
return 16; |
|
| 376 |
} else if (i == CPU_NB_REGS) {
|
|
| 377 |
env->mxcsr = ldl_p(mem_buf); |
|
| 378 |
return 4; |
|
| 375 | 379 |
} |
| 376 |
env->eip = tswap32(*(uint32_t *)p); |
|
| 377 |
p += 4; |
|
| 378 |
} |
|
| 379 |
env->eflags = tswap32(*(uint32_t *)p); |
|
| 380 |
p += 4; |
|
| 381 |
cpu_gdb_load_seg(env, &p, R_CS); |
|
| 382 |
cpu_gdb_load_seg(env, &p, R_SS); |
|
| 383 |
cpu_gdb_load_seg(env, &p, R_DS); |
|
| 384 |
cpu_gdb_load_seg(env, &p, R_ES); |
|
| 385 |
cpu_gdb_load_seg(env, &p, R_FS); |
|
| 386 |
cpu_gdb_load_seg(env, &p, R_GS); |
|
| 387 |
|
|
| 388 |
/* FPU state */ |
|
| 389 |
for(i = 0; i < 8; i++) {
|
|
| 390 |
/* XXX: convert floats */ |
|
| 391 |
#ifdef USE_X86LDOUBLE |
|
| 392 |
memcpy(&env->fpregs[i], p, 10); |
|
| 380 |
} else {
|
|
| 381 |
i -= CPU_NB_REGS; |
|
| 382 |
switch (i) {
|
|
| 383 |
case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong); |
|
| 384 |
case 1: env->eflags = ldl_p(mem_buf); return 4; |
|
| 385 |
#if defined(CONFIG_USER_ONLY) |
|
| 386 |
#define LOAD_SEG(index, sreg)\ |
|
| 387 |
tmp = ldl_p(mem_buf);\ |
|
| 388 |
if (tmp != env->segs[sreg].selector)\ |
|
| 389 |
cpu_x86_load_seg(env, sreg, tmp); |
|
| 390 |
#else |
|
| 391 |
/* FIXME: Honor segment registers. Needs to avoid raising an exception |
|
| 392 |
when the selector is invalid. */ |
|
| 393 |
#define LOAD_SEG(index, sreg) do {} while(0)
|
|
| 393 | 394 |
#endif |
| 394 |
p += 10; |
|
| 395 |
} |
|
| 396 |
env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */ |
|
| 397 |
p += 4; |
|
| 398 |
fpus = tswap32(*(uint32_t *)p); |
|
| 399 |
p += 4; |
|
| 400 |
env->fpstt = (fpus >> 11) & 7; |
|
| 401 |
env->fpus = fpus & ~0x3800; |
|
| 402 |
p += 4 * 6; |
|
| 403 |
|
|
| 404 |
if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
|
|
| 405 |
/* SSE state */ |
|
| 406 |
for(i = 0; i < nb_regs; i++) {
|
|
| 407 |
env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p); |
|
| 408 |
p += 8; |
|
| 409 |
env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p); |
|
| 410 |
p += 8; |
|
| 395 |
case 2: LOAD_SEG(10, R_CS); return 4; |
|
| 396 |
case 3: LOAD_SEG(11, R_SS); return 4; |
|
| 397 |
case 4: LOAD_SEG(12, R_DS); return 4; |
|
| 398 |
case 5: LOAD_SEG(13, R_ES); return 4; |
|
| 399 |
case 6: LOAD_SEG(14, R_FS); return 4; |
|
| 400 |
case 7: LOAD_SEG(15, R_GS); return 4; |
|
| 401 |
/* 8...15 x87 regs. */ |
|
| 402 |
case 16: env->fpuc = ldl_p(mem_buf); return 4; |
|
| 403 |
case 17: |
|
| 404 |
tmp = ldl_p(mem_buf); |
|
| 405 |
env->fpstt = (tmp >> 11) & 7; |
|
| 406 |
env->fpus = tmp & ~0x3800; |
|
| 407 |
return 4; |
|
| 408 |
case 18: /* ftag */ return 4; |
|
| 409 |
case 19: /* fiseg */ return 4; |
|
| 410 |
case 20: /* fioff */ return 4; |
|
| 411 |
case 21: /* foseg */ return 4; |
|
| 412 |
case 22: /* fooff */ return 4; |
|
| 413 |
case 23: /* fop */ return 4; |
|
| 414 |
/* 24+ xmm regs. */ |
|
| 411 | 415 |
} |
| 412 |
env->mxcsr = tswap32(*(uint32_t *)p); |
|
| 413 |
p += 4; |
|
| 414 | 416 |
} |
| 417 |
/* Unrecognised register. */ |
|
| 418 |
return 0; |
|
| 415 | 419 |
} |
| 416 | 420 |
|
| 417 | 421 |
#elif defined (TARGET_PPC) |
| 418 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 419 |
{
|
|
| 420 |
uint32_t *registers = (uint32_t *)mem_buf, tmp; |
|
| 421 |
int i; |
|
| 422 | 422 |
|
| 423 |
/* fill in gprs */ |
|
| 424 |
for(i = 0; i < 32; i++) {
|
|
| 425 |
registers[i] = tswapl(env->gpr[i]); |
|
| 426 |
} |
|
| 427 |
/* fill in fprs */ |
|
| 428 |
for (i = 0; i < 32; i++) {
|
|
| 429 |
registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i])); |
|
| 430 |
registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1)); |
|
| 431 |
} |
|
| 432 |
/* nip, msr, ccr, lnk, ctr, xer, mq */ |
|
| 433 |
registers[96] = tswapl(env->nip); |
|
| 434 |
registers[97] = tswapl(env->msr); |
|
| 435 |
tmp = 0; |
|
| 436 |
for (i = 0; i < 8; i++) |
|
| 437 |
tmp |= env->crf[i] << (32 - ((i + 1) * 4)); |
|
| 438 |
registers[98] = tswapl(tmp); |
|
| 439 |
registers[99] = tswapl(env->lr); |
|
| 440 |
registers[100] = tswapl(env->ctr); |
|
| 441 |
registers[101] = tswapl(ppc_load_xer(env)); |
|
| 442 |
registers[102] = 0; |
|
| 443 |
|
|
| 444 |
return 103 * 4; |
|
| 445 |
} |
|
| 423 |
#define NUM_CORE_REGS 71 |
|
| 446 | 424 |
|
| 447 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 425 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 448 | 426 |
{
|
| 449 |
uint32_t *registers = (uint32_t *)mem_buf; |
|
| 450 |
int i; |
|
| 427 |
if (n < 32) {
|
|
| 428 |
/* gprs */ |
|
| 429 |
GET_REGL(env->gpr[n]); |
|
| 430 |
} else if (n < 64) {
|
|
| 431 |
/* fprs */ |
|
| 432 |
stfq_p(mem_buf, env->fpr[n]); |
|
| 433 |
return 8; |
|
| 434 |
} else {
|
|
| 435 |
switch (n) {
|
|
| 436 |
case 64: GET_REGL(env->nip); |
|
| 437 |
case 65: GET_REGL(env->msr); |
|
| 438 |
case 66: |
|
| 439 |
{
|
|
| 440 |
uint32_t cr = 0; |
|
| 441 |
int i; |
|
| 442 |
for (i = 0; i < 8; i++) |
|
| 443 |
cr |= env->crf[i] << (32 - ((i + 1) * 4)); |
|
| 444 |
GET_REG32(cr); |
|
| 445 |
} |
|
| 446 |
case 67: GET_REGL(env->lr); |
|
| 447 |
case 68: GET_REGL(env->ctr); |
|
| 448 |
case 69: GET_REG32(ppc_load_xer(env)); |
|
| 449 |
case 70: GET_REG32(0); /* fpscr */ |
|
| 450 |
} |
|
| 451 |
} |
|
| 452 |
return 0; |
|
| 453 |
} |
|
| 451 | 454 |
|
| 452 |
/* fill in gprs */ |
|
| 453 |
for (i = 0; i < 32; i++) {
|
|
| 454 |
env->gpr[i] = tswapl(registers[i]); |
|
| 455 |
} |
|
| 456 |
/* fill in fprs */ |
|
| 457 |
for (i = 0; i < 32; i++) {
|
|
| 458 |
*((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]); |
|
| 459 |
*((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]); |
|
| 460 |
} |
|
| 461 |
/* nip, msr, ccr, lnk, ctr, xer, mq */ |
|
| 462 |
env->nip = tswapl(registers[96]); |
|
| 463 |
ppc_store_msr(env, tswapl(registers[97])); |
|
| 464 |
registers[98] = tswapl(registers[98]); |
|
| 465 |
for (i = 0; i < 8; i++) |
|
| 466 |
env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF; |
|
| 467 |
env->lr = tswapl(registers[99]); |
|
| 468 |
env->ctr = tswapl(registers[100]); |
|
| 469 |
ppc_store_xer(env, tswapl(registers[101])); |
|
| 455 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 456 |
{
|
|
| 457 |
if (n < 32) {
|
|
| 458 |
/* gprs */ |
|
| 459 |
env->gpr[n] = ldtul_p(mem_buf); |
|
| 460 |
return sizeof(target_ulong); |
|
| 461 |
} else if (n < 64) {
|
|
| 462 |
/* fprs */ |
|
| 463 |
env->fpr[n] = ldfq_p(mem_buf); |
|
| 464 |
return 8; |
|
| 465 |
} else {
|
|
| 466 |
switch (n) {
|
|
| 467 |
case 64: |
|
| 468 |
env->nip = ldtul_p(mem_buf); |
|
| 469 |
return sizeof(target_ulong); |
|
| 470 |
case 65: |
|
| 471 |
ppc_store_msr(env, ldtul_p(mem_buf)); |
|
| 472 |
return sizeof(target_ulong); |
|
| 473 |
case 66: |
|
| 474 |
{
|
|
| 475 |
uint32_t cr = ldl_p(mem_buf); |
|
| 476 |
int i; |
|
| 477 |
for (i = 0; i < 8; i++) |
|
| 478 |
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF; |
|
| 479 |
return 4; |
|
| 480 |
} |
|
| 481 |
case 67: |
|
| 482 |
env->lr = ldtul_p(mem_buf); |
|
| 483 |
return sizeof(target_ulong); |
|
| 484 |
case 68: |
|
| 485 |
env->ctr = ldtul_p(mem_buf); |
|
| 486 |
return sizeof(target_ulong); |
|
| 487 |
case 69: |
|
| 488 |
ppc_store_xer(env, ldl_p(mem_buf)); |
|
| 489 |
return 4; |
|
| 490 |
case 70: |
|
| 491 |
/* fpscr */ |
|
| 492 |
return 4; |
|
| 493 |
} |
|
| 494 |
} |
|
| 495 |
return 0; |
|
| 470 | 496 |
} |
| 497 |
|
|
| 471 | 498 |
#elif defined (TARGET_SPARC) |
| 472 |
#ifdef TARGET_ABI32 |
|
| 473 |
#define tswap_abi(val) tswap32(val &0xffffffff) |
|
| 499 |
|
|
| 500 |
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
|
| 501 |
#define NUM_CORE_REGS 86 |
|
| 474 | 502 |
#else |
| 475 |
#define tswap_abi(val) tswapl(val)
|
|
| 503 |
#define NUM_CORE_REGS 73
|
|
| 476 | 504 |
#endif |
| 477 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 478 |
{
|
|
| 505 |
|
|
| 479 | 506 |
#ifdef TARGET_ABI32 |
| 480 |
abi_ulong *registers = (abi_ulong *)mem_buf;
|
|
| 507 |
#define GET_REGA(val) GET_REG32(val)
|
|
| 481 | 508 |
#else |
| 482 |
target_ulong *registers = (target_ulong *)mem_buf;
|
|
| 509 |
#define GET_REGA(val) GET_REGL(val)
|
|
| 483 | 510 |
#endif |
| 484 |
int i; |
|
| 485 | 511 |
|
| 486 |
/* fill in g0..g7 */ |
|
| 487 |
for(i = 0; i < 8; i++) {
|
|
| 488 |
registers[i] = tswap_abi(env->gregs[i]); |
|
| 512 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 513 |
{
|
|
| 514 |
if (n < 8) {
|
|
| 515 |
/* g0..g7 */ |
|
| 516 |
GET_REGA(env->gregs[n]); |
|
| 489 | 517 |
} |
| 490 |
/* fill in register window */
|
|
| 491 |
for(i = 0; i < 24; i++) {
|
|
| 492 |
registers[i + 8] = tswap_abi(env->regwptr[i]);
|
|
| 518 |
if (n < 32) {
|
|
| 519 |
/* register window */
|
|
| 520 |
GET_REGA(env->regwptr[n - 8]);
|
|
| 493 | 521 |
} |
| 494 |
#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
|
|
| 495 |
/* fill in fprs */
|
|
| 496 |
for (i = 0; i < 32; i++) {
|
|
| 497 |
registers[i + 32] = tswap_abi(*((uint32_t *)&env->fpr[i]));
|
|
| 522 |
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
|
|
| 523 |
if (n < 64) {
|
|
| 524 |
/* fprs */
|
|
| 525 |
GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
|
|
| 498 | 526 |
} |
| 499 | 527 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
| 500 |
registers[64] = tswap_abi(env->y); |
|
| 501 |
{
|
|
| 502 |
uint32_t tmp; |
|
| 503 |
|
|
| 504 |
tmp = GET_PSR(env); |
|
| 505 |
registers[65] = tswap32(tmp); |
|
| 506 |
} |
|
| 507 |
registers[66] = tswap_abi(env->wim); |
|
| 508 |
registers[67] = tswap_abi(env->tbr); |
|
| 509 |
registers[68] = tswap_abi(env->pc); |
|
| 510 |
registers[69] = tswap_abi(env->npc); |
|
| 511 |
registers[70] = tswap_abi(env->fsr); |
|
| 512 |
registers[71] = 0; /* csr */ |
|
| 513 |
registers[72] = 0; |
|
| 514 |
return 73 * sizeof(uint32_t); |
|
| 528 |
switch (n) {
|
|
| 529 |
case 64: GET_REGA(env->y); |
|
| 530 |
case 65: GET_REGA(GET_PSR(env)); |
|
| 531 |
case 66: GET_REGA(env->wim); |
|
| 532 |
case 67: GET_REGA(env->tbr); |
|
| 533 |
case 68: GET_REGA(env->pc); |
|
| 534 |
case 69: GET_REGA(env->npc); |
|
| 535 |
case 70: GET_REGA(env->fsr); |
|
| 536 |
case 71: GET_REGA(0); /* csr */ |
|
| 537 |
case 72: GET_REGA(0); |
|
| 538 |
} |
|
| 515 | 539 |
#else |
| 516 |
/* fill in fprs */ |
|
| 517 |
for (i = 0; i < 64; i += 2) {
|
|
| 518 |
uint64_t tmp; |
|
| 540 |
if (n < 64) {
|
|
| 541 |
/* f0-f31 */ |
|
| 542 |
GET_REG32(*((uint32_t *)&env->fpr[n - 32])); |
|
| 543 |
} |
|
| 544 |
if (n < 80) {
|
|
| 545 |
/* f32-f62 (double width, even numbers only) */ |
|
| 546 |
uint64_t val; |
|
| 519 | 547 |
|
| 520 |
tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
|
|
| 521 |
tmp |= *(uint32_t *)&env->fpr[i + 1];
|
|
| 522 |
registers[i / 2 + 32] = tswap64(tmp);
|
|
| 548 |
val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
|
|
| 549 |
val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
|
|
| 550 |
GET_REG64(val);
|
|
| 523 | 551 |
} |
| 524 |
registers[64] = tswapl(env->pc); |
|
| 525 |
registers[65] = tswapl(env->npc); |
|
| 526 |
registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) | |
|
| 552 |
switch (n) {
|
|
| 553 |
case 80: GET_REGL(env->pc); |
|
| 554 |
case 81: GET_REGL(env->npc); |
|
| 555 |
case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) | |
|
| 527 | 556 |
((env->asi & 0xff) << 24) | |
| 528 | 557 |
((env->pstate & 0xfff) << 8) | |
| 529 | 558 |
GET_CWP64(env)); |
| 530 |
registers[67] = tswapl(env->fsr);
|
|
| 531 |
registers[68] = tswapl(env->fprs);
|
|
| 532 |
registers[69] = tswapl(env->y);
|
|
| 533 |
return 70 * sizeof(target_ulong);
|
|
| 559 |
case 83: GET_REGL(env->fsr);
|
|
| 560 |
case 84: GET_REGL(env->fprs);
|
|
| 561 |
case 85: GET_REGL(env->y);
|
|
| 562 |
}
|
|
| 534 | 563 |
#endif |
| 564 |
return 0; |
|
| 535 | 565 |
} |
| 536 | 566 |
|
| 537 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 567 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 538 | 568 |
{
|
| 539 |
#ifdef TARGET_ABI32 |
|
| 540 |
abi_ulong *registers = (abi_ulong *)mem_buf; |
|
| 569 |
#if defined(TARGET_ABI32) |
|
| 570 |
abi_ulong tmp; |
|
| 571 |
|
|
| 572 |
tmp = ldl_p(mem_buf); |
|
| 541 | 573 |
#else |
| 542 |
target_ulong *registers = (target_ulong *)mem_buf; |
|
| 574 |
target_ulong tmp; |
|
| 575 |
|
|
| 576 |
tmp = ldtul_p(mem_buf); |
|
| 543 | 577 |
#endif |
| 544 |
int i; |
|
| 545 | 578 |
|
| 546 |
/* fill in g0..g7 */ |
|
| 547 |
for(i = 0; i < 7; i++) {
|
|
| 548 |
env->gregs[i] = tswap_abi(registers[i]); |
|
| 579 |
if (n < 8) {
|
|
| 580 |
/* g0..g7 */ |
|
| 581 |
env->gregs[n] = tmp; |
|
| 582 |
} else if (n < 32) {
|
|
| 583 |
/* register window */ |
|
| 584 |
env->regwptr[n - 8] = tmp; |
|
| 549 | 585 |
} |
| 550 |
/* fill in register window */ |
|
| 551 |
for(i = 0; i < 24; i++) {
|
|
| 552 |
env->regwptr[i] = tswap_abi(registers[i + 8]); |
|
| 553 |
} |
|
| 554 |
#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) |
|
| 555 |
/* fill in fprs */ |
|
| 556 |
for (i = 0; i < 32; i++) {
|
|
| 557 |
*((uint32_t *)&env->fpr[i]) = tswap_abi(registers[i + 32]); |
|
| 586 |
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) |
|
| 587 |
else if (n < 64) {
|
|
| 588 |
/* fprs */ |
|
| 589 |
*((uint32_t *)&env->fpr[n - 32]) = tmp; |
|
| 590 |
} else {
|
|
| 591 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
|
| 592 |
switch (n) {
|
|
| 593 |
case 64: env->y = tmp; break; |
|
| 594 |
case 65: PUT_PSR(env, tmp); break; |
|
| 595 |
case 66: env->wim = tmp; break; |
|
| 596 |
case 67: env->tbr = tmp; break; |
|
| 597 |
case 68: env->pc = tmp; break; |
|
| 598 |
case 69: env->npc = tmp; break; |
|
| 599 |
case 70: env->fsr = tmp; break; |
|
| 600 |
default: return 0; |
|
| 601 |
} |
|
| 558 | 602 |
} |
| 559 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
|
| 560 |
env->y = tswap_abi(registers[64]); |
|
| 561 |
PUT_PSR(env, tswap_abi(registers[65])); |
|
| 562 |
env->wim = tswap_abi(registers[66]); |
|
| 563 |
env->tbr = tswap_abi(registers[67]); |
|
| 564 |
env->pc = tswap_abi(registers[68]); |
|
| 565 |
env->npc = tswap_abi(registers[69]); |
|
| 566 |
env->fsr = tswap_abi(registers[70]); |
|
| 603 |
return 4; |
|
| 567 | 604 |
#else |
| 568 |
for (i = 0; i < 64; i += 2) {
|
|
| 569 |
uint64_t tmp; |
|
| 570 |
|
|
| 571 |
tmp = tswap64(registers[i / 2 + 32]); |
|
| 572 |
*((uint32_t *)&env->fpr[i]) = tmp >> 32; |
|
| 573 |
*((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff; |
|
| 574 |
} |
|
| 575 |
env->pc = tswapl(registers[64]); |
|
| 576 |
env->npc = tswapl(registers[65]); |
|
| 577 |
{
|
|
| 578 |
uint64_t tmp = tswapl(registers[66]); |
|
| 579 |
|
|
| 580 |
PUT_CCR(env, tmp >> 32); |
|
| 581 |
env->asi = (tmp >> 24) & 0xff; |
|
| 582 |
env->pstate = (tmp >> 8) & 0xfff; |
|
| 583 |
PUT_CWP64(env, tmp & 0xff); |
|
| 605 |
else if (n < 64) {
|
|
| 606 |
/* f0-f31 */ |
|
| 607 |
uint32_t fpr; |
|
| 608 |
|
|
| 609 |
env->fpr[n] = ldfl_p(mem_buf); |
|
| 610 |
return 4; |
|
| 611 |
} else if (n < 80) {
|
|
| 612 |
/* f32-f62 (double width, even numbers only) */ |
|
| 613 |
*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32; |
|
| 614 |
*((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp; |
|
| 615 |
} else {
|
|
| 616 |
switch (n) {
|
|
| 617 |
case 80: env->pc = tmp; break; |
|
| 618 |
case 81: env->npc = tmp; break; |
|
| 619 |
case 82: |
|
| 620 |
PUT_CCR(env, tmp >> 32); |
|
| 621 |
env->asi = (tmp >> 24) & 0xff; |
|
| 622 |
env->pstate = (tmp >> 8) & 0xfff; |
|
| 623 |
PUT_CWP64(env, tmp & 0xff); |
|
| 624 |
break; |
|
| 625 |
case 83: env->fsr = tmp; break; |
|
| 626 |
case 84: env->fprs = tmp; break; |
|
| 627 |
case 85: env->y = tmp; break; |
|
| 628 |
default: return 0; |
|
| 629 |
} |
|
| 584 | 630 |
} |
| 585 |
env->fsr = tswapl(registers[67]); |
|
| 586 |
env->fprs = tswapl(registers[68]); |
|
| 587 |
env->y = tswapl(registers[69]); |
|
| 631 |
return 8; |
|
| 588 | 632 |
#endif |
| 589 | 633 |
} |
| 590 |
#undef tswap_abi |
|
| 591 | 634 |
#elif defined (TARGET_ARM) |
| 592 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 593 |
{
|
|
| 594 |
int i; |
|
| 595 |
uint8_t *ptr; |
|
| 596 |
|
|
| 597 |
ptr = mem_buf; |
|
| 598 |
/* 16 core integer registers (4 bytes each). */ |
|
| 599 |
for (i = 0; i < 16; i++) |
|
| 600 |
{
|
|
| 601 |
*(uint32_t *)ptr = tswapl(env->regs[i]); |
|
| 602 |
ptr += 4; |
|
| 603 |
} |
|
| 604 |
/* 8 FPA registers (12 bytes each), FPS (4 bytes). |
|
| 605 |
Not yet implemented. */ |
|
| 606 |
memset (ptr, 0, 8 * 12 + 4); |
|
| 607 |
ptr += 8 * 12 + 4; |
|
| 608 |
/* CPSR (4 bytes). */ |
|
| 609 |
*(uint32_t *)ptr = tswapl (cpsr_read(env)); |
|
| 610 |
ptr += 4; |
|
| 611 |
|
|
| 612 |
return ptr - mem_buf; |
|
| 613 |
} |
|
| 614 | 635 |
|
| 615 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
|
| 616 |
{
|
|
| 617 |
int i; |
|
| 618 |
uint8_t *ptr; |
|
| 619 |
|
|
| 620 |
ptr = mem_buf; |
|
| 621 |
/* Core integer registers. */ |
|
| 622 |
for (i = 0; i < 16; i++) |
|
| 623 |
{
|
|
| 624 |
env->regs[i] = tswapl(*(uint32_t *)ptr); |
|
| 625 |
ptr += 4; |
|
| 626 |
} |
|
| 627 |
/* Ignore FPA regs and scr. */ |
|
| 628 |
ptr += 8 * 12 + 4; |
|
| 629 |
cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff); |
|
| 630 |
} |
|
| 631 |
#elif defined (TARGET_M68K) |
|
| 632 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 633 |
{
|
|
| 634 |
int i; |
|
| 635 |
uint8_t *ptr; |
|
| 636 |
CPU_DoubleU u; |
|
| 637 |
|
|
| 638 |
ptr = mem_buf; |
|
| 639 |
/* D0-D7 */ |
|
| 640 |
for (i = 0; i < 8; i++) {
|
|
| 641 |
*(uint32_t *)ptr = tswapl(env->dregs[i]); |
|
| 642 |
ptr += 4; |
|
| 643 |
} |
|
| 644 |
/* A0-A7 */ |
|
| 645 |
for (i = 0; i < 8; i++) {
|
|
| 646 |
*(uint32_t *)ptr = tswapl(env->aregs[i]); |
|
| 647 |
ptr += 4; |
|
| 648 |
} |
|
| 649 |
*(uint32_t *)ptr = tswapl(env->sr); |
|
| 650 |
ptr += 4; |
|
| 651 |
*(uint32_t *)ptr = tswapl(env->pc); |
|
| 652 |
ptr += 4; |
|
| 653 |
/* F0-F7. The 68881/68040 have 12-bit extended precision registers. |
|
| 654 |
ColdFire has 8-bit double precision registers. */ |
|
| 655 |
for (i = 0; i < 8; i++) {
|
|
| 656 |
u.d = env->fregs[i]; |
|
| 657 |
*(uint32_t *)ptr = tswap32(u.l.upper); |
|
| 658 |
*(uint32_t *)ptr = tswap32(u.l.lower); |
|
| 659 |
} |
|
| 660 |
/* FP control regs (not implemented). */ |
|
| 661 |
memset (ptr, 0, 3 * 4); |
|
| 662 |
ptr += 3 * 4; |
|
| 663 |
|
|
| 664 |
return ptr - mem_buf; |
|
| 665 |
} |
|
| 636 |
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect |
|
| 637 |
whatever the target description contains. Due to a historical mishap |
|
| 638 |
the FPA registers appear in between core integer regs and the CPSR. |
|
| 639 |
We hack round this by giving the FPA regs zero size when talking to a |
|
| 640 |
newer gdb. */ |
|
| 641 |
#define NUM_CORE_REGS 26 |
|
| 642 |
#define GDB_CORE_XML "arm-core.xml" |
|
| 666 | 643 |
|
| 667 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 644 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 668 | 645 |
{
|
| 669 |
int i; |
|
| 670 |
uint8_t *ptr; |
|
| 671 |
CPU_DoubleU u; |
|
| 672 |
|
|
| 673 |
ptr = mem_buf; |
|
| 674 |
/* D0-D7 */ |
|
| 675 |
for (i = 0; i < 8; i++) {
|
|
| 676 |
env->dregs[i] = tswapl(*(uint32_t *)ptr); |
|
| 677 |
ptr += 4; |
|
| 678 |
} |
|
| 679 |
/* A0-A7 */ |
|
| 680 |
for (i = 0; i < 8; i++) {
|
|
| 681 |
env->aregs[i] = tswapl(*(uint32_t *)ptr); |
|
| 682 |
ptr += 4; |
|
| 683 |
} |
|
| 684 |
env->sr = tswapl(*(uint32_t *)ptr); |
|
| 685 |
ptr += 4; |
|
| 686 |
env->pc = tswapl(*(uint32_t *)ptr); |
|
| 687 |
ptr += 4; |
|
| 688 |
/* F0-F7. The 68881/68040 have 12-bit extended precision registers. |
|
| 689 |
ColdFire has 8-bit double precision registers. */ |
|
| 690 |
for (i = 0; i < 8; i++) {
|
|
| 691 |
u.l.upper = tswap32(*(uint32_t *)ptr); |
|
| 692 |
u.l.lower = tswap32(*(uint32_t *)ptr); |
|
| 693 |
env->fregs[i] = u.d; |
|
| 694 |
} |
|
| 695 |
/* FP control regs (not implemented). */ |
|
| 696 |
ptr += 3 * 4; |
|
| 646 |
if (n < 16) {
|
|
| 647 |
/* Core integer register. */ |
|
| 648 |
GET_REG32(env->regs[n]); |
|
| 649 |
} |
|
| 650 |
if (n < 24) {
|
|
| 651 |
/* FPA registers. */ |
|
| 652 |
if (gdb_has_xml) |
|
| 653 |
return 0; |
|
| 654 |
memset(mem_buf, 0, 12); |
|
| 655 |
return 12; |
|
| 656 |
} |
|
| 657 |
switch (n) {
|
|
| 658 |
case 24: |
|
| 659 |
/* FPA status register. */ |
|
| 660 |
if (gdb_has_xml) |
|
| 661 |
return 0; |
|
| 662 |
GET_REG32(0); |
|
| 663 |
case 25: |
|
| 664 |
/* CPSR */ |
|
| 665 |
GET_REG32(cpsr_read(env)); |
|
| 666 |
} |
|
| 667 |
/* Unknown register. */ |
|
| 668 |
return 0; |
|
| 697 | 669 |
} |
| 698 |
#elif defined (TARGET_MIPS) |
|
| 699 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 700 |
{
|
|
| 701 |
int i; |
|
| 702 |
uint8_t *ptr; |
|
| 703 | 670 |
|
| 704 |
ptr = mem_buf; |
|
| 705 |
for (i = 0; i < 32; i++) |
|
| 706 |
{
|
|
| 707 |
*(target_ulong *)ptr = tswapl(env->active_tc.gpr[i]); |
|
| 708 |
ptr += sizeof(target_ulong); |
|
| 709 |
} |
|
| 671 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 672 |
{
|
|
| 673 |
uint32_t tmp; |
|
| 710 | 674 |
|
| 711 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status); |
|
| 712 |
ptr += sizeof(target_ulong); |
|
| 675 |
tmp = ldl_p(mem_buf); |
|
| 713 | 676 |
|
| 714 |
*(target_ulong *)ptr = tswapl(env->active_tc.LO[0]); |
|
| 715 |
ptr += sizeof(target_ulong); |
|
| 677 |
/* Mask out low bit of PC to workaround gdb bugs. This will probably |
|
| 678 |
cause problems if we ever implement the Jazelle DBX extensions. */ |
|
| 679 |
if (n == 15) |
|
| 680 |
tmp &= ~1; |
|
| 716 | 681 |
|
| 717 |
*(target_ulong *)ptr = tswapl(env->active_tc.HI[0]); |
|
| 718 |
ptr += sizeof(target_ulong); |
|
| 682 |
if (n < 16) {
|
|
| 683 |
/* Core integer register. */ |
|
| 684 |
env->regs[n] = tmp; |
|
| 685 |
return 4; |
|
| 686 |
} |
|
| 687 |
if (n < 24) { /* 16-23 */
|
|
| 688 |
/* FPA registers (ignored). */ |
|
| 689 |
if (gdb_has_xml) |
|
| 690 |
return 0; |
|
| 691 |
return 12; |
|
| 692 |
} |
|
| 693 |
switch (n) {
|
|
| 694 |
case 24: |
|
| 695 |
/* FPA status register (ignored). */ |
|
| 696 |
if (gdb_has_xml) |
|
| 697 |
return 0; |
|
| 698 |
return 4; |
|
| 699 |
case 25: |
|
| 700 |
/* CPSR */ |
|
| 701 |
cpsr_write (env, tmp, 0xffffffff); |
|
| 702 |
return 4; |
|
| 703 |
} |
|
| 704 |
/* Unknown register. */ |
|
| 705 |
return 0; |
|
| 706 |
} |
|
| 719 | 707 |
|
| 720 |
*(target_ulong *)ptr = tswapl(env->CP0_BadVAddr); |
|
| 721 |
ptr += sizeof(target_ulong); |
|
| 708 |
#elif defined (TARGET_M68K) |
|
| 722 | 709 |
|
| 723 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause); |
|
| 724 |
ptr += sizeof(target_ulong); |
|
| 710 |
#define NUM_CORE_REGS 18 |
|
| 725 | 711 |
|
| 726 |
*(target_ulong *)ptr = tswapl(env->active_tc.PC); |
|
| 727 |
ptr += sizeof(target_ulong); |
|
| 712 |
#define GDB_CORE_XML "cf-core.xml" |
|
| 728 | 713 |
|
| 729 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
| 730 |
{
|
|
| 731 |
for (i = 0; i < 32; i++) |
|
| 732 |
{
|
|
| 733 |
if (env->CP0_Status & (1 << CP0St_FR)) |
|
| 734 |
*(target_ulong *)ptr = tswapl(env->active_fpu.fpr[i].d); |
|
| 735 |
else |
|
| 736 |
*(target_ulong *)ptr = tswap32(env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); |
|
| 737 |
ptr += sizeof(target_ulong); |
|
| 738 |
} |
|
| 714 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 715 |
{
|
|
| 716 |
if (n < 8) {
|
|
| 717 |
/* D0-D7 */ |
|
| 718 |
GET_REG32(env->dregs[n]); |
|
| 719 |
} else if (n < 16) {
|
|
| 720 |
/* A0-A7 */ |
|
| 721 |
GET_REG32(env->aregs[n - 8]); |
|
| 722 |
} else {
|
|
| 723 |
switch (n) {
|
|
| 724 |
case 16: GET_REG32(env->sr); |
|
| 725 |
case 17: GET_REG32(env->pc); |
|
| 726 |
} |
|
| 727 |
} |
|
| 728 |
/* FP registers not included here because they vary between |
|
| 729 |
ColdFire and m68k. Use XML bits for these. */ |
|
| 730 |
return 0; |
|
| 731 |
} |
|
| 739 | 732 |
|
| 740 |
*(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr31); |
|
| 741 |
ptr += sizeof(target_ulong); |
|
| 733 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 734 |
{
|
|
| 735 |
uint32_t tmp; |
|
| 742 | 736 |
|
| 743 |
*(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr0); |
|
| 744 |
ptr += sizeof(target_ulong); |
|
| 745 |
} |
|
| 737 |
tmp = ldl_p(mem_buf); |
|
| 746 | 738 |
|
| 747 |
/* "fp", pseudo frame pointer. Not yet implemented in gdb. */ |
|
| 748 |
*(target_ulong *)ptr = 0; |
|
| 749 |
ptr += sizeof(target_ulong); |
|
| 739 |
if (n < 8) {
|
|
| 740 |
/* D0-D7 */ |
|
| 741 |
env->dregs[n] = tmp; |
|
| 742 |
} else if (n < 8) {
|
|
| 743 |
/* A0-A7 */ |
|
| 744 |
env->aregs[n - 8] = tmp; |
|
| 745 |
} else {
|
|
| 746 |
switch (n) {
|
|
| 747 |
case 16: env->sr = tmp; break; |
|
| 748 |
case 17: env->pc = tmp; break; |
|
| 749 |
default: return 0; |
|
| 750 |
} |
|
| 751 |
} |
|
| 752 |
return 4; |
|
| 753 |
} |
|
| 754 |
#elif defined (TARGET_MIPS) |
|
| 750 | 755 |
|
| 751 |
/* Registers for embedded use, we just pad them. */ |
|
| 752 |
for (i = 0; i < 16; i++) |
|
| 753 |
{
|
|
| 754 |
*(target_ulong *)ptr = 0; |
|
| 755 |
ptr += sizeof(target_ulong); |
|
| 756 |
} |
|
| 756 |
#define NUM_CORE_REGS 73 |
|
| 757 | 757 |
|
| 758 |
/* Processor ID. */ |
|
| 759 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid); |
|
| 760 |
ptr += sizeof(target_ulong); |
|
| 758 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 759 |
{
|
|
| 760 |
if (n < 32) {
|
|
| 761 |
GET_REGL(env->active_tc.gpr[n]); |
|
| 762 |
} |
|
| 763 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
|
|
| 764 |
if (n >= 38 && n < 70) {
|
|
| 765 |
if (env->CP0_Status & (1 << CP0St_FR)) |
|
| 766 |
GET_REGL(env->active_fpu.fpr[n - 38].d); |
|
| 767 |
else |
|
| 768 |
GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); |
|
| 769 |
} |
|
| 770 |
switch (n) {
|
|
| 771 |
case 70: GET_REGL((int32_t)env->active_fpu.fcr31); |
|
| 772 |
case 71: GET_REGL((int32_t)env->active_fpu.fcr0); |
|
| 773 |
} |
|
| 774 |
} |
|
| 775 |
switch (n) {
|
|
| 776 |
case 32: GET_REGL((int32_t)env->CP0_Status); |
|
| 777 |
case 33: GET_REGL(env->active_tc.LO[0]); |
|
| 778 |
case 34: GET_REGL(env->active_tc.HI[0]); |
|
| 779 |
case 35: GET_REGL(env->CP0_BadVAddr); |
|
| 780 |
case 36: GET_REGL((int32_t)env->CP0_Cause); |
|
| 781 |
case 37: GET_REGL(env->active_tc.PC); |
|
| 782 |
case 72: GET_REGL(0); /* fp */ |
|
| 783 |
case 89: GET_REGL((int32_t)env->CP0_PRid); |
|
| 784 |
} |
|
| 785 |
if (n >= 73 && n <= 88) {
|
|
| 786 |
/* 16 embedded regs. */ |
|
| 787 |
GET_REGL(0); |
|
| 788 |
} |
|
| 761 | 789 |
|
| 762 |
return ptr - mem_buf;
|
|
| 790 |
return 0;
|
|
| 763 | 791 |
} |
| 764 | 792 |
|
| 765 | 793 |
/* convert MIPS rounding mode in FCR31 to IEEE library */ |
| ... | ... | |
| 773 | 801 |
#define RESTORE_ROUNDING_MODE \ |
| 774 | 802 |
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) |
| 775 | 803 |
|
| 776 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 804 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 777 | 805 |
{
|
| 778 |
int i; |
|
| 779 |
uint8_t *ptr; |
|
| 780 |
|
|
| 781 |
ptr = mem_buf; |
|
| 782 |
for (i = 0; i < 32; i++) |
|
| 783 |
{
|
|
| 784 |
env->active_tc.gpr[i] = tswapl(*(target_ulong *)ptr); |
|
| 785 |
ptr += sizeof(target_ulong); |
|
| 786 |
} |
|
| 787 |
|
|
| 788 |
env->CP0_Status = tswapl(*(target_ulong *)ptr); |
|
| 789 |
ptr += sizeof(target_ulong); |
|
| 806 |
target_ulong tmp; |
|
| 790 | 807 |
|
| 791 |
env->active_tc.LO[0] = tswapl(*(target_ulong *)ptr); |
|
| 792 |
ptr += sizeof(target_ulong); |
|
| 808 |
tmp = ldtul_p(mem_buf); |
|
| 793 | 809 |
|
| 794 |
env->active_tc.HI[0] = tswapl(*(target_ulong *)ptr); |
|
| 795 |
ptr += sizeof(target_ulong); |
|
| 796 |
|
|
| 797 |
env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr); |
|
| 798 |
ptr += sizeof(target_ulong); |
|
| 799 |
|
|
| 800 |
env->CP0_Cause = tswapl(*(target_ulong *)ptr); |
|
| 801 |
ptr += sizeof(target_ulong); |
|
| 802 |
|
|
| 803 |
env->active_tc.PC = tswapl(*(target_ulong *)ptr); |
|
| 804 |
ptr += sizeof(target_ulong); |
|
| 805 |
|
|
| 806 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
| 807 |
{
|
|
| 808 |
for (i = 0; i < 32; i++) |
|
| 809 |
{
|
|
| 810 |
if (n < 32) {
|
|
| 811 |
env->active_tc.gpr[n] = tmp; |
|
| 812 |
return sizeof(target_ulong); |
|
| 813 |
} |
|
| 814 |
if (env->CP0_Config1 & (1 << CP0C1_FP) |
|
| 815 |
&& n >= 38 && n < 73) {
|
|
| 816 |
if (n < 70) {
|
|
| 810 | 817 |
if (env->CP0_Status & (1 << CP0St_FR)) |
| 811 |
env->active_fpu.fpr[i].d = tswapl(*(target_ulong *)ptr);
|
|
| 818 |
env->active_fpu.fpr[n - 38].d = tmp;
|
|
| 812 | 819 |
else |
| 813 |
env->active_fpu.fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr); |
|
| 814 |
ptr += sizeof(target_ulong); |
|
| 815 |
} |
|
| 816 |
|
|
| 817 |
env->active_fpu.fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF; |
|
| 818 |
ptr += sizeof(target_ulong); |
|
| 819 |
|
|
| 820 |
/* The remaining registers are assumed to be read-only. */ |
|
| 821 |
|
|
| 822 |
/* set rounding mode */ |
|
| 823 |
RESTORE_ROUNDING_MODE; |
|
| 824 |
|
|
| 820 |
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; |
|
| 821 |
} |
|
| 822 |
switch (n) {
|
|
| 823 |
case 70: |
|
| 824 |
env->active_fpu.fcr31 = tmp & 0xFF83FFFF; |
|
| 825 |
/* set rounding mode */ |
|
| 826 |
RESTORE_ROUNDING_MODE; |
|
| 825 | 827 |
#ifndef CONFIG_SOFTFLOAT |
| 826 |
/* no floating point exception for native float */ |
|
| 827 |
SET_FP_ENABLE(env->fcr31, 0);
|
|
| 828 |
/* no floating point exception for native float */
|
|
| 829 |
SET_FP_ENABLE(env->active_fpu.fcr31, 0);
|
|
| 828 | 830 |
#endif |
| 829 |
} |
|
| 831 |
break; |
|
| 832 |
case 71: env->active_fpu.fcr0 = tmp; break; |
|
| 833 |
} |
|
| 834 |
return sizeof(target_ulong); |
|
| 835 |
} |
|
| 836 |
switch (n) {
|
|
| 837 |
case 32: env->CP0_Status = tmp; break; |
|
| 838 |
case 33: env->active_tc.LO[0] = tmp; break; |
|
| 839 |
case 34: env->active_tc.HI[0] = tmp; break; |
|
| 840 |
case 35: env->CP0_BadVAddr = tmp; break; |
|
| 841 |
case 36: env->CP0_Cause = tmp; break; |
|
| 842 |
case 37: env->active_tc.PC = tmp; break; |
|
| 843 |
case 72: /* fp, ignored */ break; |
|
| 844 |
default: |
|
| 845 |
if (n > 89) |
|
| 846 |
return 0; |
|
| 847 |
/* Other registers are readonly. Ignore writes. */ |
|
| 848 |
break; |
|
| 849 |
} |
|
| 850 |
|
|
| 851 |
return sizeof(target_ulong); |
|
| 830 | 852 |
} |
| 831 | 853 |
#elif defined (TARGET_SH4) |
| 832 | 854 |
|
| 833 | 855 |
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */ |
| 856 |
/* FIXME: We should use XML for this. */ |
|
| 857 |
|
|
| 858 |
#define NUM_CORE_REGS 59 |
|
| 834 | 859 |
|
| 835 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
|
|
| 860 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 836 | 861 |
{
|
| 837 |
uint32_t *ptr = (uint32_t *)mem_buf; |
|
| 838 |
int i; |
|
| 839 |
|
|
| 840 |
#define SAVE(x) *ptr++=tswapl(x) |
|
| 841 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
|
| 842 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); |
|
| 843 |
} else {
|
|
| 844 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i]); |
|
| 845 |
} |
|
| 846 |
for (i = 8; i < 16; i++) SAVE(env->gregs[i]); |
|
| 847 |
SAVE (env->pc); |
|
| 848 |
SAVE (env->pr); |
|
| 849 |
SAVE (env->gbr); |
|
| 850 |
SAVE (env->vbr); |
|
| 851 |
SAVE (env->mach); |
|
| 852 |
SAVE (env->macl); |
|
| 853 |
SAVE (env->sr); |
|
| 854 |
SAVE (env->fpul); |
|
| 855 |
SAVE (env->fpscr); |
|
| 856 |
for (i = 0; i < 16; i++) |
|
| 857 |
SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
|
| 858 |
SAVE (env->ssr); |
|
| 859 |
SAVE (env->spc); |
|
| 860 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i]); |
|
| 861 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); |
|
| 862 |
return ((uint8_t *)ptr - mem_buf); |
|
| 862 |
if (n < 8) {
|
|
| 863 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
|
| 864 |
GET_REGL(env->gregs[n + 16]); |
|
| 865 |
} else {
|
|
| 866 |
GET_REGL(env->gregs[n]); |
|
| 867 |
} |
|
| 868 |
} else if (n < 16) {
|
|
| 869 |
GET_REGL(env->gregs[n - 8]); |
|
| 870 |
} else if (n >= 25 && n < 41) {
|
|
| 871 |
GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
|
| 872 |
} else if (n >= 43 && n < 51) {
|
|
| 873 |
GET_REGL(env->gregs[n - 43]); |
|
| 874 |
} else if (n >= 51 && n < 59) {
|
|
| 875 |
GET_REGL(env->gregs[n - (51 - 16)]); |
|
| 876 |
} |
|
| 877 |
switch (n) {
|
|
| 878 |
case 16: GET_REGL(env->pc); |
|
| 879 |
case 17: GET_REGL(env->pr); |
|
| 880 |
case 18: GET_REGL(env->gbr); |
|
| 881 |
case 19: GET_REGL(env->vbr); |
|
| 882 |
case 20: GET_REGL(env->mach); |
|
| 883 |
case 21: GET_REGL(env->macl); |
|
| 884 |
case 22: GET_REGL(env->sr); |
|
| 885 |
case 23: GET_REGL(env->fpul); |
|
| 886 |
case 24: GET_REGL(env->fpscr); |
|
| 887 |
case 41: GET_REGL(env->ssr); |
|
| 888 |
case 42: GET_REGL(env->spc); |
|
| 889 |
} |
|
| 890 |
|
|
| 891 |
return 0; |
|
| 863 | 892 |
} |
| 864 | 893 |
|
| 865 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
|
|
| 894 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
|
|
| 866 | 895 |
{
|
| 867 |
uint32_t *ptr = (uint32_t *)mem_buf; |
|
| 868 |
int i; |
|
| 869 |
|
|
| 870 |
#define LOAD(x) (x)=*ptr++; |
|
| 871 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
|
| 872 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); |
|
| 873 |
} else {
|
|
| 874 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i]); |
|
| 875 |
} |
|
| 876 |
for (i = 8; i < 16; i++) LOAD(env->gregs[i]); |
|
| 877 |
LOAD (env->pc); |
|
| 878 |
LOAD (env->pr); |
|
| 879 |
LOAD (env->gbr); |
|
| 880 |
LOAD (env->vbr); |
|
| 881 |
LOAD (env->mach); |
|
| 882 |
LOAD (env->macl); |
|
| 883 |
LOAD (env->sr); |
|
| 884 |
LOAD (env->fpul); |
|
| 885 |
LOAD (env->fpscr); |
|
| 886 |
for (i = 0; i < 16; i++) |
|
| 887 |
LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
|
| 888 |
LOAD (env->ssr); |
|
| 889 |
LOAD (env->spc); |
|
| 890 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i]); |
|
| 891 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); |
|
| 896 |
uint32_t tmp; |
|
| 897 |
|
|
| 898 |
tmp = ldl_p(mem_buf); |
|
| 899 |
|
|
| 900 |
if (n < 8) {
|
|
| 901 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
|
| 902 |
env->gregs[n + 16] = tmp; |
|
| 903 |
} else {
|
|
| 904 |
env->gregs[n] = tmp; |
|
| 905 |
} |
|
| 906 |
return 4; |
|
| 907 |
} else if (n < 16) {
|
|
| 908 |
env->gregs[n - 8] = tmp; |
|
| 909 |
return 4; |
|
| 910 |
} else if (n >= 25 && n < 41) {
|
|
| 911 |
env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp; |
|
| 912 |
} else if (n >= 43 && n < 51) {
|
|
| 913 |
env->gregs[n - 43] = tmp; |
|
| 914 |
return 4; |
|
| 915 |
} else if (n >= 51 && n < 59) {
|
|
| 916 |
env->gregs[n - (51 - 16)] = tmp; |
|
| 917 |
return 4; |
|
| 918 |
} |
|
| 919 |
switch (n) {
|
|
| 920 |
case 16: env->pc = tmp; |
|
| 921 |
case 17: env->pr = tmp; |
|
| 922 |
case 18: env->gbr = tmp; |
|
| 923 |
case 19: env->vbr = tmp; |
|
| 924 |
case 20: env->mach = tmp; |
|
| 925 |
case 21: env->macl = tmp; |
|
| 926 |
case 22: env->sr = tmp; |
|
| 927 |
case 23: env->fpul = tmp; |
|
| 928 |
case 24: env->fpscr = tmp; |
|
| 929 |
case 41: env->ssr = tmp; |
|
| 930 |
case 42: env->spc = tmp; |
|
| 931 |
default: return 0; |
|
| 932 |
} |
|
| 933 |
|
|
| 934 |
return 4; |
|
| 892 | 935 |
} |
| 893 | 936 |
#elif defined (TARGET_CRIS) |
| 894 | 937 |
|
| 895 |
static int cris_save_32 (unsigned char *d, uint32_t value) |
|
| 938 |
#define NUM_CORE_REGS 49 |
|
| 939 |
|
|
| 940 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 896 | 941 |
{
|
| 897 |
*d++ = (value); |
|
| 898 |
*d++ = (value >>= 8); |
|
| 899 |
*d++ = (value >>= 8); |
|
| 900 |
*d++ = (value >>= 8); |
|
| 901 |
return 4; |
|
| 942 |
uint8_t srs; |
|
| 943 |
|
|
| 944 |
srs = env->pregs[PR_SRS]; |
|
| 945 |
if (n < 16) {
|
|
| 946 |
GET_REG32(env->regs[n]); |
|
| 947 |
} |
|
| 948 |
|
|
| 949 |
if (n >= 21 && n < 32) {
|
|
| 950 |
GET_REG32(env->pregs[n - 16]); |
|
| 951 |
} |
|
| 952 |
if (n >= 33 && n < 49) {
|
|
| 953 |
GET_REG32(env->sregs[srs][n - 33]); |
|
| 954 |
} |
|
| 955 |
switch (n) {
|
|
| 956 |
case 16: GET_REG8(env->pregs[0]); |
|
| 957 |
case 17: GET_REG8(env->pregs[1]); |
|
| 958 |
case 18: GET_REG32(env->pregs[2]); |
|
| 959 |
case 19: GET_REG8(srs); |
|
| 960 |
case 20: GET_REG16(env->pregs[4]); |
|
| 961 |
case 32: GET_REG32(env->pc); |
|
| 962 |
} |
|
| 963 |
|
|
| 964 |
return 0; |
|
| 902 | 965 |
} |
| 903 |
static int cris_save_16 (unsigned char *d, uint32_t value) |
|
| 966 |
|
|
| 967 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 904 | 968 |
{
|
| 905 |
*d++ = (value); |
|
| 906 |
*d++ = (value >>= 8); |
|
| 907 |
return 2; |
|
| 969 |
uint32_t tmp; |
|
| 970 |
|
|
| 971 |
if (n > 49) |
|
| 972 |
return 0; |
|
| 973 |
|
|
| 974 |
tmp = ldl_p(mem_buf); |
|
| 975 |
|
|
| 976 |
if (n < 16) {
|
|
| 977 |
env->regs[n] = tmp; |
|
| 978 |
} |
|
| 979 |
|
|
| 980 |
/* FIXME: Should other regs be writable? */ |
|
| 981 |
switch (n) {
|
|
| 982 |
case 16: return 1; |
|
| 983 |
case 17: return 1; |
|
| 984 |
case 18: return 4; |
|
| 985 |
case 19: return 1; |
|
| 986 |
case 20: return 2; |
|
| 987 |
case 32: env->pc = tmp; break; |
|
| 988 |
} |
|
| 989 |
|
|
| 990 |
return 4; |
|
| 908 | 991 |
} |
| 909 |
static int cris_save_8 (unsigned char *d, uint32_t value) |
|
| 992 |
#else |
|
| 993 |
|
|
| 994 |
#define NUM_CORE_REGS 0 |
|
| 995 |
|
|
| 996 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 910 | 997 |
{
|
| 911 |
*d++ = (value); |
|
| 912 |
return 1; |
|
| 998 |
return 0; |
|
| 913 | 999 |
} |
| 914 | 1000 |
|
| 915 |
/* FIXME: this will bug on archs not supporting unaligned word accesses. */ |
|
| 916 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
|
| 1001 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
|
| 917 | 1002 |
{
|
| 918 |
uint8_t *ptr = mem_buf; |
|
| 919 |
uint8_t srs; |
|
| 920 |
int i; |
|
| 1003 |
return 0; |
|
| 1004 |
} |
|
| 921 | 1005 |
|
| 922 |
for (i = 0; i < 16; i++) |
|
| 923 |
ptr += cris_save_32 (ptr, env->regs[i]); |
|
| 1006 |
#endif |
|
| 924 | 1007 |
|
| 925 |
srs = env->pregs[PR_SRS];
|
|
| 1008 |
static int num_g_regs = NUM_CORE_REGS;
|
|
| 926 | 1009 |
|
| 927 |
ptr += cris_save_8 (ptr, env->pregs[0]); |
|
| 928 |
ptr += cris_save_8 (ptr, env->pregs[1]); |
|
| 929 |
ptr += cris_save_32 (ptr, env->pregs[2]); |
|
| 930 |
ptr += cris_save_8 (ptr, srs); |
|
| 931 |
ptr += cris_save_16 (ptr, env->pregs[4]); |
|
| 1010 |
#ifdef GDB_CORE_XML |
|
| 1011 |
/* Encode data using the encoding for 'x' packets. */ |
|
| 1012 |
static int memtox(char *buf, const char *mem, int len) |
|
| 1013 |
{
|
|
| 1014 |
char *p = buf; |
|
| 1015 |
char c; |
|
| 1016 |
|
|
| 1017 |
while (len--) {
|
|
| 1018 |
c = *(mem++); |
|
| 1019 |
switch (c) {
|
|
| 1020 |
case '#': case '$': case '*': case '}': |
|
| 1021 |
*(p++) = '}'; |
|
| 1022 |
*(p++) = c ^ 0x20; |
|
| 1023 |
break; |
|
| 1024 |
default: |
|
| 1025 |
*(p++) = c; |
|
| 1026 |
break; |
|
| 1027 |
} |
|
| 1028 |
} |
|
| 1029 |
return p - buf; |
|
| 1030 |
} |
|
| 932 | 1031 |
|
| 933 |
for (i = 5; i < 16; i++) |
|
| 934 |
ptr += cris_save_32 (ptr, env->pregs[i]); |
|
| 1032 |
const char *get_feature_xml(CPUState *env, const char *p, const char **newp) |
|
| 1033 |
{
|
|
| 1034 |
extern const char *const xml_builtin[][2]; |
|
| 1035 |
size_t len; |
|
| 1036 |
int i; |
|
| 1037 |
const char *name; |
|
| 1038 |
static char target_xml[1024]; |
|
| 1039 |
|
|
| 1040 |
len = 0; |
|
| 1041 |
while (p[len] && p[len] != ':') |
|
| 1042 |
len++; |
|
| 1043 |
*newp = p + len; |
|
| 1044 |
|
|
| 1045 |
name = NULL; |
|
| 1046 |
if (strncmp(p, "target.xml", len) == 0) {
|
|
| 1047 |
/* Generate the XML description for this CPU. */ |
|
| 1048 |
if (!target_xml[0]) {
|
|
| 1049 |
GDBRegisterState *r; |
|
| 1050 |
|
|
| 1051 |
sprintf(target_xml, |
|
| 1052 |
"<?xml version=\"1.0\"?>" |
|
| 1053 |
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">" |
|
| 1054 |
"<target>" |
|
| 1055 |
"<xi:include href=\"%s\"/>", |
|
| 1056 |
GDB_CORE_XML); |
|
| 1057 |
|
|
| 1058 |
for (r = env->gdb_regs; r; r = r->next) {
|
|
| 1059 |
strcat(target_xml, "<xi:include href=\""); |
|
| 1060 |
strcat(target_xml, r->xml); |
|
| 1061 |
strcat(target_xml, "\"/>"); |
|
| 1062 |
} |
|
| 1063 |
strcat(target_xml, "</target>"); |
|
| 1064 |
} |
|
| 1065 |
return target_xml; |
|
| 1066 |
} |
|
| 1067 |
for (i = 0; ; i++) {
|
|
| 1068 |
name = xml_builtin[i][0]; |
|
| 1069 |
if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len)) |
|
| 1070 |
break; |
|
| 1071 |
} |
|
| 1072 |
return name ? xml_builtin[i][1] : NULL; |
|
| 1073 |
} |
|
| 1074 |
#endif |
|
| 935 | 1075 |
|
| 936 |
ptr += cris_save_32 (ptr, env->pc); |
|
| 1076 |
static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg) |
|
| 1077 |
{
|
|
| 1078 |
GDBRegisterState *r; |
|
| 937 | 1079 |
|
| 938 |
for (i = 0; i < 16; i++)
|
|
| 939 |
ptr += cris_save_32 (ptr, env->sregs[srs][i]);
|
|
| 1080 |
if (reg < NUM_CORE_REGS)
|
|
| 1081 |
return cpu_gdb_read_register(env, mem_buf, reg);
|
|
| 940 | 1082 |
|
| 941 |
return ((uint8_t *)ptr - mem_buf); |
|
| 1083 |
for (r = env->gdb_regs; r; r = r->next) {
|
|
| 1084 |
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
|
|
| 1085 |
return r->get_reg(env, mem_buf, reg - r->base_reg); |
|
| 1086 |
} |
|
| 1087 |
} |
|
| 1088 |
return 0; |
|
| 942 | 1089 |
} |
Also available in: Unified diff