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/*
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* Arm PrimeCell PL190 Vector Interrupt Controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "primecell.h" |
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#include "arm-misc.h" |
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/* The number of virtual priority levels. 16 user vectors plus the
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unvectored IRQ. Chained interrupts would require an additional level
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if implemented. */
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#define PL190_NUM_PRIO 17 |
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typedef struct { |
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uint32_t level; |
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uint32_t soft_level; |
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uint32_t irq_enable; |
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uint32_t fiq_select; |
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uint32_t default_addr; |
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uint8_t vect_control[16];
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uint32_t vect_addr[PL190_NUM_PRIO]; |
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/* Mask containing interrupts with higher priority than this one. */
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uint32_t prio_mask[PL190_NUM_PRIO + 1];
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int protected;
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/* Current priority level. */
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int priority;
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int prev_prio[PL190_NUM_PRIO];
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qemu_irq irq; |
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qemu_irq fiq; |
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} pl190_state; |
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static const unsigned char pl190_id[] = |
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{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; |
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static inline uint32_t pl190_irq_level(pl190_state *s) |
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{ |
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return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
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} |
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/* Update interrupts. */
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static void pl190_update(pl190_state *s) |
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{ |
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uint32_t level = pl190_irq_level(s); |
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int set;
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set = (level & s->prio_mask[s->priority]) != 0;
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qemu_set_irq(s->irq, set); |
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set = ((s->level | s->soft_level) & s->fiq_select) != 0;
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qemu_set_irq(s->fiq, set); |
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} |
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static void pl190_set_irq(void *opaque, int irq, int level) |
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{ |
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pl190_state *s = (pl190_state *)opaque; |
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if (level)
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s->level |= 1u << irq;
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else
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s->level &= ~(1u << irq);
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pl190_update(s); |
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} |
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static void pl190_update_vectors(pl190_state *s) |
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{ |
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uint32_t mask; |
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int i;
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int n;
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mask = 0;
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for (i = 0; i < 16; i++) |
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{ |
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s->prio_mask[i] = mask; |
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if (s->vect_control[i] & 0x20) |
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{ |
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n = s->vect_control[i] & 0x1f;
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mask |= 1 << n;
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} |
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} |
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s->prio_mask[16] = mask;
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pl190_update(s); |
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} |
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static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) |
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{ |
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pl190_state *s = (pl190_state *)opaque; |
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int i;
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if (offset >= 0xfe0 && offset < 0x1000) { |
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return pl190_id[(offset - 0xfe0) >> 2]; |
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} |
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if (offset >= 0x100 && offset < 0x140) { |
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return s->vect_addr[(offset - 0x100) >> 2]; |
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} |
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if (offset >= 0x200 && offset < 0x240) { |
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return s->vect_control[(offset - 0x200) >> 2]; |
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} |
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switch (offset >> 2) { |
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case 0: /* IRQSTATUS */ |
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return pl190_irq_level(s);
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case 1: /* FIQSATUS */ |
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return (s->level | s->soft_level) & s->fiq_select;
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case 2: /* RAWINTR */ |
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return s->level | s->soft_level;
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case 3: /* INTSELECT */ |
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return s->fiq_select;
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case 4: /* INTENABLE */ |
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return s->irq_enable;
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case 6: /* SOFTINT */ |
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return s->soft_level;
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case 8: /* PROTECTION */ |
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return s->protected;
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case 12: /* VECTADDR */ |
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/* Read vector address at the start of an ISR. Increases the
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current priority level to that of the current interrupt. */
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for (i = 0; i < s->priority; i++) |
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{ |
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if ((s->level | s->soft_level) & s->prio_mask[i])
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break;
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} |
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/* Reading this value with no pending interrupts is undefined.
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We return the default address. */
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if (i == PL190_NUM_PRIO)
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return s->vect_addr[16]; |
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if (i < s->priority)
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{ |
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s->prev_prio[i] = s->priority; |
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s->priority = i; |
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pl190_update(s); |
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} |
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return s->vect_addr[s->priority];
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case 13: /* DEFVECTADDR */ |
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return s->vect_addr[16]; |
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default:
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cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val) |
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{ |
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pl190_state *s = (pl190_state *)opaque; |
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if (offset >= 0x100 && offset < 0x140) { |
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s->vect_addr[(offset - 0x100) >> 2] = val; |
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pl190_update_vectors(s); |
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return;
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} |
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if (offset >= 0x200 && offset < 0x240) { |
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s->vect_control[(offset - 0x200) >> 2] = val; |
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pl190_update_vectors(s); |
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return;
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} |
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switch (offset >> 2) { |
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case 0: /* SELECT */ |
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/* This is a readonly register, but linux tries to write to it
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anyway. Ignore the write. */
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break;
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case 3: /* INTSELECT */ |
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s->fiq_select = val; |
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break;
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case 4: /* INTENABLE */ |
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s->irq_enable |= val; |
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break;
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case 5: /* INTENCLEAR */ |
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s->irq_enable &= ~val; |
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break;
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case 6: /* SOFTINT */ |
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s->soft_level |= val; |
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break;
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case 7: /* SOFTINTCLEAR */ |
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s->soft_level &= ~val; |
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break;
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case 8: /* PROTECTION */ |
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/* TODO: Protection (supervisor only access) is not implemented. */
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s->protected = val & 1;
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break;
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case 12: /* VECTADDR */ |
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/* Restore the previous priority level. The value written is
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ignored. */
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if (s->priority < PL190_NUM_PRIO)
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s->priority = s->prev_prio[s->priority]; |
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break;
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case 13: /* DEFVECTADDR */ |
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s->default_addr = val; |
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break;
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case 0xc0: /* ITCR */ |
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if (val)
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cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
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break;
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default:
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cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset); |
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return;
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} |
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pl190_update(s); |
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} |
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static CPUReadMemoryFunc *pl190_readfn[] = {
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pl190_read, |
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pl190_read, |
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pl190_read |
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}; |
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static CPUWriteMemoryFunc *pl190_writefn[] = {
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pl190_write, |
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pl190_write, |
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pl190_write |
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}; |
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static void pl190_reset(pl190_state *s) |
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{ |
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int i;
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for (i = 0; i < 16; i++) |
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{ |
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s->vect_addr[i] = 0;
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s->vect_control[i] = 0;
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} |
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s->vect_addr[16] = 0; |
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s->prio_mask[17] = 0xffffffff; |
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s->priority = PL190_NUM_PRIO; |
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pl190_update_vectors(s); |
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} |
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qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq) |
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{ |
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pl190_state *s; |
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qemu_irq *qi; |
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int iomemtype;
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s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
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iomemtype = cpu_register_io_memory(0, pl190_readfn,
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pl190_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
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s->irq = irq; |
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s->fiq = fiq; |
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pl190_reset(s); |
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/* ??? Save/restore. */
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return qi;
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} |