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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 execution defines
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 7d3505c5 | bellard | #include "config.h" |
21 | 2c0262af | bellard | #include "dyngen-exec.h" |
22 | 2c0262af | bellard | |
23 | 0d1a29f9 | bellard | /* at least 4 register variables are defined */
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24 | 2c0262af | bellard | register struct CPUX86State *env asm(AREG0); |
25 | 2c0262af | bellard | register uint32_t T0 asm(AREG1); |
26 | 2c0262af | bellard | register uint32_t T1 asm(AREG2); |
27 | 2c0262af | bellard | register uint32_t T2 asm(AREG3); |
28 | 2c0262af | bellard | |
29 | 2c0262af | bellard | #define A0 T2
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30 | 2c0262af | bellard | |
31 | 2c0262af | bellard | /* if more registers are available, we define some registers too */
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32 | 2c0262af | bellard | #ifdef AREG4
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33 | 2c0262af | bellard | register uint32_t EAX asm(AREG4); |
34 | 2c0262af | bellard | #define reg_EAX
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35 | 2c0262af | bellard | #endif
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36 | 2c0262af | bellard | |
37 | 2c0262af | bellard | #ifdef AREG5
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38 | 2c0262af | bellard | register uint32_t ESP asm(AREG5); |
39 | 2c0262af | bellard | #define reg_ESP
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40 | 2c0262af | bellard | #endif
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41 | 2c0262af | bellard | |
42 | 2c0262af | bellard | #ifdef AREG6
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43 | 2c0262af | bellard | register uint32_t EBP asm(AREG6); |
44 | 2c0262af | bellard | #define reg_EBP
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45 | 2c0262af | bellard | #endif
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46 | 2c0262af | bellard | |
47 | 2c0262af | bellard | #ifdef AREG7
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48 | 2c0262af | bellard | register uint32_t ECX asm(AREG7); |
49 | 2c0262af | bellard | #define reg_ECX
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50 | 2c0262af | bellard | #endif
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51 | 2c0262af | bellard | |
52 | 2c0262af | bellard | #ifdef AREG8
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53 | 2c0262af | bellard | register uint32_t EDX asm(AREG8); |
54 | 2c0262af | bellard | #define reg_EDX
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55 | 2c0262af | bellard | #endif
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56 | 2c0262af | bellard | |
57 | 2c0262af | bellard | #ifdef AREG9
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58 | 2c0262af | bellard | register uint32_t EBX asm(AREG9); |
59 | 2c0262af | bellard | #define reg_EBX
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60 | 2c0262af | bellard | #endif
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61 | 2c0262af | bellard | |
62 | 2c0262af | bellard | #ifdef AREG10
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63 | 2c0262af | bellard | register uint32_t ESI asm(AREG10); |
64 | 2c0262af | bellard | #define reg_ESI
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65 | 2c0262af | bellard | #endif
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66 | 2c0262af | bellard | |
67 | 2c0262af | bellard | #ifdef AREG11
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68 | 2c0262af | bellard | register uint32_t EDI asm(AREG11); |
69 | 2c0262af | bellard | #define reg_EDI
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70 | 2c0262af | bellard | #endif
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71 | 2c0262af | bellard | |
72 | 2c0262af | bellard | extern FILE *logfile;
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73 | 2c0262af | bellard | extern int loglevel; |
74 | 2c0262af | bellard | |
75 | 2c0262af | bellard | #ifndef reg_EAX
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76 | 2c0262af | bellard | #define EAX (env->regs[R_EAX])
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77 | 2c0262af | bellard | #endif
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78 | 2c0262af | bellard | #ifndef reg_ECX
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79 | 2c0262af | bellard | #define ECX (env->regs[R_ECX])
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80 | 2c0262af | bellard | #endif
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81 | 2c0262af | bellard | #ifndef reg_EDX
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82 | 2c0262af | bellard | #define EDX (env->regs[R_EDX])
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83 | 2c0262af | bellard | #endif
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84 | 2c0262af | bellard | #ifndef reg_EBX
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85 | 2c0262af | bellard | #define EBX (env->regs[R_EBX])
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86 | 2c0262af | bellard | #endif
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87 | 2c0262af | bellard | #ifndef reg_ESP
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88 | 2c0262af | bellard | #define ESP (env->regs[R_ESP])
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89 | 2c0262af | bellard | #endif
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90 | 2c0262af | bellard | #ifndef reg_EBP
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91 | 2c0262af | bellard | #define EBP (env->regs[R_EBP])
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92 | 2c0262af | bellard | #endif
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93 | 2c0262af | bellard | #ifndef reg_ESI
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94 | 2c0262af | bellard | #define ESI (env->regs[R_ESI])
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95 | 2c0262af | bellard | #endif
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96 | 2c0262af | bellard | #ifndef reg_EDI
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97 | 2c0262af | bellard | #define EDI (env->regs[R_EDI])
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98 | 2c0262af | bellard | #endif
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99 | 2c0262af | bellard | #define EIP (env->eip)
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100 | 2c0262af | bellard | #define DF (env->df)
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101 | 2c0262af | bellard | |
102 | 2c0262af | bellard | #define CC_SRC (env->cc_src)
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103 | 2c0262af | bellard | #define CC_DST (env->cc_dst)
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104 | 2c0262af | bellard | #define CC_OP (env->cc_op)
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105 | 2c0262af | bellard | |
106 | 2c0262af | bellard | /* float macros */
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107 | 2c0262af | bellard | #define FT0 (env->ft0)
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108 | 2c0262af | bellard | #define ST0 (env->fpregs[env->fpstt])
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109 | 2c0262af | bellard | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7]) |
110 | 2c0262af | bellard | #define ST1 ST(1) |
111 | 2c0262af | bellard | |
112 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
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113 | 2c0262af | bellard | #define FP_CONVERT (env->fp_convert)
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114 | 2c0262af | bellard | #endif
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115 | 2c0262af | bellard | |
116 | 2c0262af | bellard | #include "cpu.h" |
117 | 2c0262af | bellard | #include "exec-all.h" |
118 | 2c0262af | bellard | |
119 | 2c0262af | bellard | typedef struct CCTable { |
120 | 2c0262af | bellard | int (*compute_all)(void); /* return all the flags */ |
121 | 2c0262af | bellard | int (*compute_c)(void); /* return the C flag */ |
122 | 2c0262af | bellard | } CCTable; |
123 | 2c0262af | bellard | |
124 | 2c0262af | bellard | extern CCTable cc_table[];
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125 | 2c0262af | bellard | |
126 | 8e682019 | bellard | void load_seg(int seg_reg, int selector); |
127 | 08cea4ee | bellard | void helper_ljmp_protected_T0_T1(int next_eip); |
128 | 2c0262af | bellard | void helper_lcall_real_T0_T1(int shift, int next_eip); |
129 | 2c0262af | bellard | void helper_lcall_protected_T0_T1(int shift, int next_eip); |
130 | 2c0262af | bellard | void helper_iret_real(int shift); |
131 | 08cea4ee | bellard | void helper_iret_protected(int shift, int next_eip); |
132 | 2c0262af | bellard | void helper_lret_protected(int shift, int addend); |
133 | 2c0262af | bellard | void helper_lldt_T0(void); |
134 | 2c0262af | bellard | void helper_ltr_T0(void); |
135 | 2c0262af | bellard | void helper_movl_crN_T0(int reg); |
136 | 2c0262af | bellard | void helper_movl_drN_T0(int reg); |
137 | 2c0262af | bellard | void helper_invlpg(unsigned int addr); |
138 | 1ac157da | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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139 | 1ac157da | bellard | void cpu_x86_update_cr3(CPUX86State *env, uint32_t new_cr3);
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140 | 1ac157da | bellard | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
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141 | 2c0262af | bellard | void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr);
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142 | 61382a50 | bellard | int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
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143 | 61382a50 | bellard | int is_write, int is_user, int is_softmmu); |
144 | 61382a50 | bellard | void tlb_fill(unsigned long addr, int is_write, int is_user, |
145 | 61382a50 | bellard | void *retaddr);
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146 | 2c0262af | bellard | void __hidden cpu_lock(void); |
147 | 2c0262af | bellard | void __hidden cpu_unlock(void); |
148 | 2c0262af | bellard | void do_interrupt(int intno, int is_int, int error_code, |
149 | 2c0262af | bellard | unsigned int next_eip, int is_hw); |
150 | 2c0262af | bellard | void do_interrupt_user(int intno, int is_int, int error_code, |
151 | 2c0262af | bellard | unsigned int next_eip); |
152 | 2c0262af | bellard | void raise_interrupt(int intno, int is_int, int error_code, |
153 | 2c0262af | bellard | unsigned int next_eip); |
154 | 2c0262af | bellard | void raise_exception_err(int exception_index, int error_code); |
155 | 2c0262af | bellard | void raise_exception(int exception_index); |
156 | 2c0262af | bellard | void __hidden cpu_loop_exit(void); |
157 | 2c0262af | bellard | void helper_fsave(uint8_t *ptr, int data32); |
158 | 2c0262af | bellard | void helper_frstor(uint8_t *ptr, int data32); |
159 | 2c0262af | bellard | |
160 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void); |
161 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void); |
162 | 2c0262af | bellard | void raise_interrupt(int intno, int is_int, int error_code, |
163 | 2c0262af | bellard | unsigned int next_eip); |
164 | 2c0262af | bellard | void raise_exception_err(int exception_index, int error_code); |
165 | 2c0262af | bellard | void raise_exception(int exception_index); |
166 | 2c0262af | bellard | void helper_divl_EAX_T0(uint32_t eip);
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167 | 2c0262af | bellard | void helper_idivl_EAX_T0(uint32_t eip);
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168 | 2c0262af | bellard | void helper_cmpxchg8b(void); |
169 | 2c0262af | bellard | void helper_cpuid(void); |
170 | 61a8c4ec | bellard | void helper_enter_level(int level, int data32); |
171 | 023fe10d | bellard | void helper_sysenter(void); |
172 | 023fe10d | bellard | void helper_sysexit(void); |
173 | 2c0262af | bellard | void helper_rdtsc(void); |
174 | 2c0262af | bellard | void helper_rdmsr(void); |
175 | 2c0262af | bellard | void helper_wrmsr(void); |
176 | 2c0262af | bellard | void helper_lsl(void); |
177 | 2c0262af | bellard | void helper_lar(void); |
178 | 3ab493de | bellard | void helper_verr(void); |
179 | 3ab493de | bellard | void helper_verw(void); |
180 | 2c0262af | bellard | |
181 | 3e25f951 | bellard | void check_iob_T0(void); |
182 | 3e25f951 | bellard | void check_iow_T0(void); |
183 | 3e25f951 | bellard | void check_iol_T0(void); |
184 | 3e25f951 | bellard | void check_iob_DX(void); |
185 | 3e25f951 | bellard | void check_iow_DX(void); |
186 | 3e25f951 | bellard | void check_iol_DX(void); |
187 | 3e25f951 | bellard | |
188 | 9951bf39 | bellard | /* XXX: move that to a generic header */
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189 | 9951bf39 | bellard | #if !defined(CONFIG_USER_ONLY)
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190 | 9951bf39 | bellard | |
191 | 9951bf39 | bellard | #define ldul_user ldl_user
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192 | 9951bf39 | bellard | #define ldul_kernel ldl_kernel
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193 | 9951bf39 | bellard | |
194 | 9951bf39 | bellard | #define ACCESS_TYPE 0 |
195 | 9951bf39 | bellard | #define MEMSUFFIX _kernel
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196 | 9951bf39 | bellard | #define DATA_SIZE 1 |
197 | 9951bf39 | bellard | #include "softmmu_header.h" |
198 | 9951bf39 | bellard | |
199 | 9951bf39 | bellard | #define DATA_SIZE 2 |
200 | 9951bf39 | bellard | #include "softmmu_header.h" |
201 | 9951bf39 | bellard | |
202 | 9951bf39 | bellard | #define DATA_SIZE 4 |
203 | 9951bf39 | bellard | #include "softmmu_header.h" |
204 | 9951bf39 | bellard | |
205 | 9951bf39 | bellard | #define DATA_SIZE 8 |
206 | 9951bf39 | bellard | #include "softmmu_header.h" |
207 | 9951bf39 | bellard | #undef ACCESS_TYPE
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208 | 9951bf39 | bellard | #undef MEMSUFFIX
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209 | 9951bf39 | bellard | |
210 | 9951bf39 | bellard | #define ACCESS_TYPE 1 |
211 | 9951bf39 | bellard | #define MEMSUFFIX _user
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212 | 9951bf39 | bellard | #define DATA_SIZE 1 |
213 | 9951bf39 | bellard | #include "softmmu_header.h" |
214 | 9951bf39 | bellard | |
215 | 9951bf39 | bellard | #define DATA_SIZE 2 |
216 | 9951bf39 | bellard | #include "softmmu_header.h" |
217 | 9951bf39 | bellard | |
218 | 9951bf39 | bellard | #define DATA_SIZE 4 |
219 | 9951bf39 | bellard | #include "softmmu_header.h" |
220 | 9951bf39 | bellard | |
221 | 9951bf39 | bellard | #define DATA_SIZE 8 |
222 | 9951bf39 | bellard | #include "softmmu_header.h" |
223 | 9951bf39 | bellard | #undef ACCESS_TYPE
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224 | 9951bf39 | bellard | #undef MEMSUFFIX
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225 | 9951bf39 | bellard | |
226 | 9951bf39 | bellard | /* these access are slower, they must be as rare as possible */
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227 | 9951bf39 | bellard | #define ACCESS_TYPE 2 |
228 | 9951bf39 | bellard | #define MEMSUFFIX _data
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229 | 9951bf39 | bellard | #define DATA_SIZE 1 |
230 | 9951bf39 | bellard | #include "softmmu_header.h" |
231 | 9951bf39 | bellard | |
232 | 9951bf39 | bellard | #define DATA_SIZE 2 |
233 | 9951bf39 | bellard | #include "softmmu_header.h" |
234 | 9951bf39 | bellard | |
235 | 9951bf39 | bellard | #define DATA_SIZE 4 |
236 | 9951bf39 | bellard | #include "softmmu_header.h" |
237 | 9951bf39 | bellard | |
238 | 9951bf39 | bellard | #define DATA_SIZE 8 |
239 | 9951bf39 | bellard | #include "softmmu_header.h" |
240 | 9951bf39 | bellard | #undef ACCESS_TYPE
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241 | 9951bf39 | bellard | #undef MEMSUFFIX
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242 | 9951bf39 | bellard | |
243 | 9951bf39 | bellard | #define ldub(p) ldub_data(p)
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244 | 9951bf39 | bellard | #define ldsb(p) ldsb_data(p)
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245 | 9951bf39 | bellard | #define lduw(p) lduw_data(p)
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246 | 9951bf39 | bellard | #define ldsw(p) ldsw_data(p)
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247 | 9951bf39 | bellard | #define ldl(p) ldl_data(p)
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248 | 9951bf39 | bellard | #define ldq(p) ldq_data(p)
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249 | 9951bf39 | bellard | |
250 | 9951bf39 | bellard | #define stb(p, v) stb_data(p, v)
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251 | 9951bf39 | bellard | #define stw(p, v) stw_data(p, v)
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252 | 9951bf39 | bellard | #define stl(p, v) stl_data(p, v)
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253 | 9951bf39 | bellard | #define stq(p, v) stq_data(p, v)
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254 | 9951bf39 | bellard | |
255 | 9951bf39 | bellard | static inline double ldfq(void *ptr) |
256 | 9951bf39 | bellard | { |
257 | 9951bf39 | bellard | union {
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258 | 9951bf39 | bellard | double d;
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259 | 9951bf39 | bellard | uint64_t i; |
260 | 9951bf39 | bellard | } u; |
261 | 9951bf39 | bellard | u.i = ldq(ptr); |
262 | 9951bf39 | bellard | return u.d;
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263 | 9951bf39 | bellard | } |
264 | 9951bf39 | bellard | |
265 | 9951bf39 | bellard | static inline void stfq(void *ptr, double v) |
266 | 9951bf39 | bellard | { |
267 | 9951bf39 | bellard | union {
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268 | 9951bf39 | bellard | double d;
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269 | 9951bf39 | bellard | uint64_t i; |
270 | 9951bf39 | bellard | } u; |
271 | 9951bf39 | bellard | u.d = v; |
272 | 9951bf39 | bellard | stq(ptr, u.i); |
273 | 9951bf39 | bellard | } |
274 | 9951bf39 | bellard | |
275 | 9951bf39 | bellard | static inline float ldfl(void *ptr) |
276 | 9951bf39 | bellard | { |
277 | 9951bf39 | bellard | union {
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278 | 9951bf39 | bellard | float f;
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279 | 9951bf39 | bellard | uint32_t i; |
280 | 9951bf39 | bellard | } u; |
281 | 9951bf39 | bellard | u.i = ldl(ptr); |
282 | 9951bf39 | bellard | return u.f;
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283 | 9951bf39 | bellard | } |
284 | 9951bf39 | bellard | |
285 | 9951bf39 | bellard | static inline void stfl(void *ptr, float v) |
286 | 9951bf39 | bellard | { |
287 | 9951bf39 | bellard | union {
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288 | 9951bf39 | bellard | float f;
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289 | 9951bf39 | bellard | uint32_t i; |
290 | 9951bf39 | bellard | } u; |
291 | 9951bf39 | bellard | u.f = v; |
292 | 9951bf39 | bellard | stl(ptr, u.i); |
293 | 9951bf39 | bellard | } |
294 | 9951bf39 | bellard | |
295 | 9951bf39 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
296 | 9951bf39 | bellard | |
297 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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298 | 2c0262af | bellard | /* use long double functions */
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299 | 2c0262af | bellard | #define lrint lrintl
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300 | 2c0262af | bellard | #define llrint llrintl
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301 | 2c0262af | bellard | #define fabs fabsl
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302 | 2c0262af | bellard | #define sin sinl
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303 | 2c0262af | bellard | #define cos cosl
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304 | 2c0262af | bellard | #define sqrt sqrtl
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305 | 2c0262af | bellard | #define pow powl
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306 | 2c0262af | bellard | #define log logl
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307 | 2c0262af | bellard | #define tan tanl
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308 | 2c0262af | bellard | #define atan2 atan2l
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309 | 2c0262af | bellard | #define floor floorl
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310 | 2c0262af | bellard | #define ceil ceill
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311 | 2c0262af | bellard | #define rint rintl
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312 | 2c0262af | bellard | #endif
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313 | 2c0262af | bellard | |
314 | 7d3505c5 | bellard | #if !defined(_BSD)
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315 | 2c0262af | bellard | extern int lrint(CPU86_LDouble x); |
316 | 2c0262af | bellard | extern int64_t llrint(CPU86_LDouble x);
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317 | 7d3505c5 | bellard | #else
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318 | 7d3505c5 | bellard | #define lrint(d) ((int)rint(d)) |
319 | 7d3505c5 | bellard | #define llrint(d) ((int)rint(d)) |
320 | 7d3505c5 | bellard | #endif
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321 | 2c0262af | bellard | extern CPU86_LDouble fabs(CPU86_LDouble x);
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322 | 2c0262af | bellard | extern CPU86_LDouble sin(CPU86_LDouble x);
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323 | 2c0262af | bellard | extern CPU86_LDouble cos(CPU86_LDouble x);
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324 | 2c0262af | bellard | extern CPU86_LDouble sqrt(CPU86_LDouble x);
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325 | 2c0262af | bellard | extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
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326 | 2c0262af | bellard | extern CPU86_LDouble log(CPU86_LDouble x);
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327 | 2c0262af | bellard | extern CPU86_LDouble tan(CPU86_LDouble x);
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328 | 2c0262af | bellard | extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
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329 | 2c0262af | bellard | extern CPU86_LDouble floor(CPU86_LDouble x);
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330 | 2c0262af | bellard | extern CPU86_LDouble ceil(CPU86_LDouble x);
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331 | 2c0262af | bellard | extern CPU86_LDouble rint(CPU86_LDouble x);
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332 | 2c0262af | bellard | |
333 | 2c0262af | bellard | #define RC_MASK 0xc00 |
334 | 2c0262af | bellard | #define RC_NEAR 0x000 |
335 | 2c0262af | bellard | #define RC_DOWN 0x400 |
336 | 2c0262af | bellard | #define RC_UP 0x800 |
337 | 2c0262af | bellard | #define RC_CHOP 0xc00 |
338 | 2c0262af | bellard | |
339 | 2c0262af | bellard | #define MAXTAN 9223372036854775808.0 |
340 | 2c0262af | bellard | |
341 | 2c0262af | bellard | #ifdef __arm__
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342 | 2c0262af | bellard | /* we have no way to do correct rounding - a FPU emulator is needed */
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343 | 2c0262af | bellard | #define FE_DOWNWARD FE_TONEAREST
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344 | 2c0262af | bellard | #define FE_UPWARD FE_TONEAREST
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345 | 2c0262af | bellard | #define FE_TOWARDZERO FE_TONEAREST
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346 | 2c0262af | bellard | #endif
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347 | 2c0262af | bellard | |
348 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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349 | 2c0262af | bellard | |
350 | 2c0262af | bellard | /* only for x86 */
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351 | 2c0262af | bellard | typedef union { |
352 | 2c0262af | bellard | long double d; |
353 | 2c0262af | bellard | struct {
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354 | 2c0262af | bellard | unsigned long long lower; |
355 | 2c0262af | bellard | unsigned short upper; |
356 | 2c0262af | bellard | } l; |
357 | 2c0262af | bellard | } CPU86_LDoubleU; |
358 | 2c0262af | bellard | |
359 | 2c0262af | bellard | /* the following deal with x86 long double-precision numbers */
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360 | 2c0262af | bellard | #define MAXEXPD 0x7fff |
361 | 2c0262af | bellard | #define EXPBIAS 16383 |
362 | 2c0262af | bellard | #define EXPD(fp) (fp.l.upper & 0x7fff) |
363 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
364 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower)
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365 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
366 | 2c0262af | bellard | |
367 | 2c0262af | bellard | #else
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368 | 2c0262af | bellard | |
369 | 2c0262af | bellard | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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370 | 2c0262af | bellard | typedef union { |
371 | 2c0262af | bellard | double d;
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372 | 2c0262af | bellard | #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
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373 | 2c0262af | bellard | struct {
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374 | 2c0262af | bellard | uint32_t lower; |
375 | 2c0262af | bellard | int32_t upper; |
376 | 2c0262af | bellard | } l; |
377 | 2c0262af | bellard | #else
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378 | 2c0262af | bellard | struct {
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379 | 2c0262af | bellard | int32_t upper; |
380 | 2c0262af | bellard | uint32_t lower; |
381 | 2c0262af | bellard | } l; |
382 | 2c0262af | bellard | #endif
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383 | 2c0262af | bellard | #ifndef __arm__
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384 | 2c0262af | bellard | int64_t ll; |
385 | 2c0262af | bellard | #endif
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386 | 2c0262af | bellard | } CPU86_LDoubleU; |
387 | 2c0262af | bellard | |
388 | 2c0262af | bellard | /* the following deal with IEEE double-precision numbers */
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389 | 2c0262af | bellard | #define MAXEXPD 0x7ff |
390 | 2c0262af | bellard | #define EXPBIAS 1023 |
391 | 2c0262af | bellard | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) |
392 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x80000000) |
393 | 2c0262af | bellard | #ifdef __arm__
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394 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) |
395 | 2c0262af | bellard | #else
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396 | 2c0262af | bellard | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) |
397 | 2c0262af | bellard | #endif
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398 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) |
399 | 2c0262af | bellard | #endif
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400 | 2c0262af | bellard | |
401 | 2c0262af | bellard | static inline void fpush(void) |
402 | 2c0262af | bellard | { |
403 | 2c0262af | bellard | env->fpstt = (env->fpstt - 1) & 7; |
404 | 2c0262af | bellard | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
405 | 2c0262af | bellard | } |
406 | 2c0262af | bellard | |
407 | 2c0262af | bellard | static inline void fpop(void) |
408 | 2c0262af | bellard | { |
409 | 2c0262af | bellard | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
410 | 2c0262af | bellard | env->fpstt = (env->fpstt + 1) & 7; |
411 | 2c0262af | bellard | } |
412 | 2c0262af | bellard | |
413 | 2c0262af | bellard | #ifndef USE_X86LDOUBLE
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414 | 2c0262af | bellard | static inline CPU86_LDouble helper_fldt(uint8_t *ptr) |
415 | 2c0262af | bellard | { |
416 | 2c0262af | bellard | CPU86_LDoubleU temp; |
417 | 2c0262af | bellard | int upper, e;
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418 | 2c0262af | bellard | uint64_t ll; |
419 | 2c0262af | bellard | |
420 | 2c0262af | bellard | /* mantissa */
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421 | 2c0262af | bellard | upper = lduw(ptr + 8);
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422 | 2c0262af | bellard | /* XXX: handle overflow ? */
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423 | 2c0262af | bellard | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ |
424 | 2c0262af | bellard | e |= (upper >> 4) & 0x800; /* sign */ |
425 | 2c0262af | bellard | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); |
426 | 2c0262af | bellard | #ifdef __arm__
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427 | 2c0262af | bellard | temp.l.upper = (e << 20) | (ll >> 32); |
428 | 2c0262af | bellard | temp.l.lower = ll; |
429 | 2c0262af | bellard | #else
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430 | 2c0262af | bellard | temp.ll = ll | ((uint64_t)e << 52);
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431 | 2c0262af | bellard | #endif
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432 | 2c0262af | bellard | return temp.d;
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433 | 2c0262af | bellard | } |
434 | 2c0262af | bellard | |
435 | 2c0262af | bellard | static inline void helper_fstt(CPU86_LDouble f, uint8_t *ptr) |
436 | 2c0262af | bellard | { |
437 | 2c0262af | bellard | CPU86_LDoubleU temp; |
438 | 2c0262af | bellard | int e;
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439 | 2c0262af | bellard | |
440 | 2c0262af | bellard | temp.d = f; |
441 | 2c0262af | bellard | /* mantissa */
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442 | 2c0262af | bellard | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); |
443 | 2c0262af | bellard | /* exponent + sign */
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444 | 2c0262af | bellard | e = EXPD(temp) - EXPBIAS + 16383;
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445 | 2c0262af | bellard | e |= SIGND(temp) >> 16;
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446 | 2c0262af | bellard | stw(ptr + 8, e);
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447 | 2c0262af | bellard | } |
448 | 9951bf39 | bellard | #else
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449 | 9951bf39 | bellard | |
450 | 9951bf39 | bellard | /* XXX: same endianness assumed */
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451 | 9951bf39 | bellard | |
452 | 9951bf39 | bellard | #ifdef CONFIG_USER_ONLY
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453 | 9951bf39 | bellard | |
454 | 9951bf39 | bellard | static inline CPU86_LDouble helper_fldt(uint8_t *ptr) |
455 | 9951bf39 | bellard | { |
456 | 9951bf39 | bellard | return *(CPU86_LDouble *)ptr;
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457 | 9951bf39 | bellard | } |
458 | 9951bf39 | bellard | |
459 | 9951bf39 | bellard | static inline void helper_fstt(CPU86_LDouble f, uint8_t *ptr) |
460 | 9951bf39 | bellard | { |
461 | 9951bf39 | bellard | *(CPU86_LDouble *)ptr = f; |
462 | 9951bf39 | bellard | } |
463 | 9951bf39 | bellard | |
464 | 9951bf39 | bellard | #else
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465 | 9951bf39 | bellard | |
466 | 9951bf39 | bellard | /* we use memory access macros */
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467 | 9951bf39 | bellard | |
468 | 9951bf39 | bellard | static inline CPU86_LDouble helper_fldt(uint8_t *ptr) |
469 | 9951bf39 | bellard | { |
470 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
471 | 9951bf39 | bellard | |
472 | 9951bf39 | bellard | temp.l.lower = ldq(ptr); |
473 | 9951bf39 | bellard | temp.l.upper = lduw(ptr + 8);
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474 | 9951bf39 | bellard | return temp.d;
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475 | 9951bf39 | bellard | } |
476 | 9951bf39 | bellard | |
477 | 9951bf39 | bellard | static inline void helper_fstt(CPU86_LDouble f, uint8_t *ptr) |
478 | 9951bf39 | bellard | { |
479 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
480 | 9951bf39 | bellard | |
481 | 9951bf39 | bellard | temp.d = f; |
482 | 9951bf39 | bellard | stq(ptr, temp.l.lower); |
483 | 9951bf39 | bellard | stw(ptr + 8, temp.l.upper);
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484 | 9951bf39 | bellard | } |
485 | 9951bf39 | bellard | |
486 | 9951bf39 | bellard | #endif /* !CONFIG_USER_ONLY */ |
487 | 9951bf39 | bellard | |
488 | 9951bf39 | bellard | #endif /* USE_X86LDOUBLE */ |
489 | 2c0262af | bellard | |
490 | 2ee73ac3 | bellard | #define FPUS_IE (1 << 0) |
491 | 2ee73ac3 | bellard | #define FPUS_DE (1 << 1) |
492 | 2ee73ac3 | bellard | #define FPUS_ZE (1 << 2) |
493 | 2ee73ac3 | bellard | #define FPUS_OE (1 << 3) |
494 | 2ee73ac3 | bellard | #define FPUS_UE (1 << 4) |
495 | 2ee73ac3 | bellard | #define FPUS_PE (1 << 5) |
496 | 2ee73ac3 | bellard | #define FPUS_SF (1 << 6) |
497 | 2ee73ac3 | bellard | #define FPUS_SE (1 << 7) |
498 | 2ee73ac3 | bellard | #define FPUS_B (1 << 15) |
499 | 2ee73ac3 | bellard | |
500 | 2ee73ac3 | bellard | #define FPUC_EM 0x3f |
501 | 2ee73ac3 | bellard | |
502 | 83fb7adf | bellard | extern const CPU86_LDouble f15rk[7]; |
503 | 2c0262af | bellard | |
504 | 2c0262af | bellard | void helper_fldt_ST0_A0(void); |
505 | 2c0262af | bellard | void helper_fstt_ST0_A0(void); |
506 | 2ee73ac3 | bellard | void fpu_raise_exception(void); |
507 | 2ee73ac3 | bellard | CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b); |
508 | 2c0262af | bellard | void helper_fbld_ST0_A0(void); |
509 | 2c0262af | bellard | void helper_fbst_ST0_A0(void); |
510 | 2c0262af | bellard | void helper_f2xm1(void); |
511 | 2c0262af | bellard | void helper_fyl2x(void); |
512 | 2c0262af | bellard | void helper_fptan(void); |
513 | 2c0262af | bellard | void helper_fpatan(void); |
514 | 2c0262af | bellard | void helper_fxtract(void); |
515 | 2c0262af | bellard | void helper_fprem1(void); |
516 | 2c0262af | bellard | void helper_fprem(void); |
517 | 2c0262af | bellard | void helper_fyl2xp1(void); |
518 | 2c0262af | bellard | void helper_fsqrt(void); |
519 | 2c0262af | bellard | void helper_fsincos(void); |
520 | 2c0262af | bellard | void helper_frndint(void); |
521 | 2c0262af | bellard | void helper_fscale(void); |
522 | 2c0262af | bellard | void helper_fsin(void); |
523 | 2c0262af | bellard | void helper_fcos(void); |
524 | 2c0262af | bellard | void helper_fxam_ST0(void); |
525 | 2c0262af | bellard | void helper_fstenv(uint8_t *ptr, int data32); |
526 | 2c0262af | bellard | void helper_fldenv(uint8_t *ptr, int data32); |
527 | 2c0262af | bellard | void helper_fsave(uint8_t *ptr, int data32); |
528 | 2c0262af | bellard | void helper_frstor(uint8_t *ptr, int data32); |
529 | 03857e31 | bellard | void restore_native_fp_state(CPUState *env);
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530 | 03857e31 | bellard | void save_native_fp_state(CPUState *env);
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531 | 2c0262af | bellard | |
532 | 83fb7adf | bellard | extern const uint8_t parity_table[256]; |
533 | 83fb7adf | bellard | extern const uint8_t rclw_table[32]; |
534 | 83fb7adf | bellard | extern const uint8_t rclb_table[32]; |
535 | 2c0262af | bellard | |
536 | 2c0262af | bellard | static inline uint32_t compute_eflags(void) |
537 | 2c0262af | bellard | { |
538 | 2c0262af | bellard | return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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539 | 2c0262af | bellard | } |
540 | 2c0262af | bellard | |
541 | 2c0262af | bellard | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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542 | 2c0262af | bellard | static inline void load_eflags(int eflags, int update_mask) |
543 | 2c0262af | bellard | { |
544 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
545 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1)); |
546 | 2c0262af | bellard | env->eflags = (env->eflags & ~update_mask) | |
547 | 2c0262af | bellard | (eflags & update_mask); |
548 | 2c0262af | bellard | } |
549 | 2c0262af | bellard | |
550 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
551 | 0d1a29f9 | bellard | { |
552 | 0d1a29f9 | bellard | #ifdef reg_EAX
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553 | 0d1a29f9 | bellard | EAX = env->regs[R_EAX]; |
554 | 0d1a29f9 | bellard | #endif
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555 | 0d1a29f9 | bellard | #ifdef reg_ECX
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556 | 0d1a29f9 | bellard | ECX = env->regs[R_ECX]; |
557 | 0d1a29f9 | bellard | #endif
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558 | 0d1a29f9 | bellard | #ifdef reg_EDX
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559 | 0d1a29f9 | bellard | EDX = env->regs[R_EDX]; |
560 | 0d1a29f9 | bellard | #endif
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561 | 0d1a29f9 | bellard | #ifdef reg_EBX
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562 | 0d1a29f9 | bellard | EBX = env->regs[R_EBX]; |
563 | 0d1a29f9 | bellard | #endif
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564 | 0d1a29f9 | bellard | #ifdef reg_ESP
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565 | 0d1a29f9 | bellard | ESP = env->regs[R_ESP]; |
566 | 0d1a29f9 | bellard | #endif
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567 | 0d1a29f9 | bellard | #ifdef reg_EBP
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568 | 0d1a29f9 | bellard | EBP = env->regs[R_EBP]; |
569 | 0d1a29f9 | bellard | #endif
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570 | 0d1a29f9 | bellard | #ifdef reg_ESI
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571 | 0d1a29f9 | bellard | ESI = env->regs[R_ESI]; |
572 | 0d1a29f9 | bellard | #endif
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573 | 0d1a29f9 | bellard | #ifdef reg_EDI
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574 | 0d1a29f9 | bellard | EDI = env->regs[R_EDI]; |
575 | 0d1a29f9 | bellard | #endif
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576 | 0d1a29f9 | bellard | } |
577 | 0d1a29f9 | bellard | |
578 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
579 | 0d1a29f9 | bellard | { |
580 | 0d1a29f9 | bellard | #ifdef reg_EAX
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581 | 0d1a29f9 | bellard | env->regs[R_EAX] = EAX; |
582 | 0d1a29f9 | bellard | #endif
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583 | 0d1a29f9 | bellard | #ifdef reg_ECX
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584 | 0d1a29f9 | bellard | env->regs[R_ECX] = ECX; |
585 | 0d1a29f9 | bellard | #endif
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586 | 0d1a29f9 | bellard | #ifdef reg_EDX
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587 | 0d1a29f9 | bellard | env->regs[R_EDX] = EDX; |
588 | 0d1a29f9 | bellard | #endif
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589 | 0d1a29f9 | bellard | #ifdef reg_EBX
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590 | 0d1a29f9 | bellard | env->regs[R_EBX] = EBX; |
591 | 0d1a29f9 | bellard | #endif
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592 | 0d1a29f9 | bellard | #ifdef reg_ESP
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593 | 0d1a29f9 | bellard | env->regs[R_ESP] = ESP; |
594 | 0d1a29f9 | bellard | #endif
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595 | 0d1a29f9 | bellard | #ifdef reg_EBP
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596 | 0d1a29f9 | bellard | env->regs[R_EBP] = EBP; |
597 | 0d1a29f9 | bellard | #endif
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598 | 0d1a29f9 | bellard | #ifdef reg_ESI
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599 | 0d1a29f9 | bellard | env->regs[R_ESI] = ESI; |
600 | 0d1a29f9 | bellard | #endif
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601 | 0d1a29f9 | bellard | #ifdef reg_EDI
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602 | 0d1a29f9 | bellard | env->regs[R_EDI] = EDI; |
603 | 0d1a29f9 | bellard | #endif
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604 | 0d1a29f9 | bellard | } |