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/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514 |
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#define E8390_CMD 0x00 /* The command register (for all pages) */ |
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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#define EN0_TSR 0x04 /* Transmit status reg RD */ |
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#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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#define EN0_NCR 0x05 /* Number of collision reg RD */ |
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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#define EN0_FIFO 0x06 /* FIFO RD */ |
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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#define EN0_RSR 0x0c /* rx status reg RD */ |
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#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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#define EN1_PHYS 0x11 |
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#define EN1_CURPAG 0x17 |
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#define EN1_MULT 0x18 |
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */ |
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#define E8390_START 0x02 /* Start the chip, clear reset */ |
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#define E8390_TRANS 0x04 /* Transmit a frame */ |
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#define E8390_RREAD 0x08 /* Remote read */ |
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#define E8390_RWRITE 0x10 /* Remote write */ |
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#define E8390_NODMA 0x20 /* Remote DMA */ |
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#define E8390_PAGE0 0x00 /* Select page chip registers */ |
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#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */ |
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#define ENISR_TX 0x02 /* Transmitter, no error */ |
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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#define ENISR_RDC 0x40 /* remote dma complete */ |
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#define ENISR_RESET 0x80 /* Reset completed */ |
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#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */ |
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#define ENRSR_CRC 0x02 /* CRC error */ |
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#define ENRSR_FAE 0x04 /* frame alignment error */ |
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#define ENRSR_FO 0x08 /* FIFO overrun */ |
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#define ENRSR_MPA 0x10 /* missed pkt */ |
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#define ENRSR_PHY 0x20 /* physical/multicast address */ |
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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#define ENRSR_DEF 0x80 /* deferring */ |
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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#define NE2000_PMEM_SIZE (32*1024) |
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#define NE2000_PMEM_START (16*1024) |
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#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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#define NE2000_MEM_SIZE NE2000_PMEM_END
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typedef struct NE2000State { |
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uint8_t cmd; |
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uint32_t start; |
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uint32_t stop; |
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uint8_t boundary; |
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uint8_t tsr; |
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uint8_t tpsr; |
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uint16_t tcnt; |
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uint16_t rcnt; |
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uint32_t rsar; |
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uint8_t rsr; |
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uint8_t isr; |
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uint8_t dcfg; |
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uint8_t imr; |
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uint8_t phys[6]; /* mac address */ |
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uint8_t curpag; |
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uint8_t mult[8]; /* multicast mask array */ |
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int irq;
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PCIDevice *pci_dev; |
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NetDriverState *nd; |
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uint8_t mem[NE2000_MEM_SIZE]; |
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} NE2000State; |
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static void ne2000_reset(NE2000State *s) |
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{ |
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int i;
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s->isr = ENISR_RESET; |
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memcpy(s->mem, s->nd->macaddr, 6);
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s->mem[14] = 0x57; |
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s->mem[15] = 0x57; |
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) { |
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i]; |
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} |
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} |
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static void ne2000_update_irq(NE2000State *s) |
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{ |
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int isr;
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isr = s->isr & s->imr; |
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#if defined(DEBUG_NE2000)
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printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
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s->irq, isr ? 1 : 0, s->isr, s->imr); |
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#endif
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if (s->irq == 16) { |
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/* PCI irq */
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pci_set_irq(s->pci_dev, 0, (isr != 0)); |
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} else {
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/* ISA irq */
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pic_set_irq(s->irq, (isr != 0));
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} |
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} |
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/* return the max buffer size if the NE2000 can receive more data */
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static int ne2000_can_receive(void *opaque) |
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{ |
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NE2000State *s = opaque; |
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int avail, index, boundary;
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if (s->cmd & E8390_STOP)
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return 0; |
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index; |
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else
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avail = (s->stop - s->start) - (index - boundary); |
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if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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return 0; |
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return MAX_ETH_FRAME_SIZE;
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} |
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#define MIN_BUF_SIZE 60 |
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static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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NE2000State *s = opaque; |
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uint8_t *p; |
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int total_len, next, avail, len, index;
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uint8_t buf1[60];
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%d\n", size);
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#endif
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size); |
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1; |
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size = MIN_BUF_SIZE; |
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} |
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index = s->curpag << 8;
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff); |
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if (next >= s->stop)
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next -= (s->stop - s->start); |
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/* prepare packet header */
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p = s->mem + index; |
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s->rsr = ENRSR_RXOK; /* receive status */
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/* XXX: check this */
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if (buf[0] & 0x01) |
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s->rsr |= ENRSR_PHY; |
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p[0] = s->rsr;
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p[1] = next >> 8; |
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p[2] = total_len;
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p[3] = total_len >> 8; |
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index += 4;
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/* write packet data */
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while (size > 0) { |
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avail = s->stop - index; |
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len = size; |
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if (len > avail)
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len = avail; |
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memcpy(s->mem + index, buf, len); |
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buf += len; |
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index += len; |
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if (index == s->stop)
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index = s->start; |
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size -= len; |
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} |
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s->curpag = next >> 8;
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/* now we can signal we have receive something */
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s->isr |= ENISR_RX; |
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ne2000_update_irq(s); |
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} |
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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NE2000State *s = opaque; |
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int offset, page;
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addr &= 0xf;
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#ifdef DEBUG_NE2000
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printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == E8390_CMD) {
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/* control register */
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s->cmd = val; |
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if (val & E8390_START) {
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s->isr &= ~ENISR_RESET; |
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/* test specific case: zero length transfert */
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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s->rcnt == 0) {
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} |
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if (val & E8390_TRANS) {
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qemu_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
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/* signal end of transfert */
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s->tsr = ENTSR_PTX; |
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s->isr |= ENISR_TX; |
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ne2000_update_irq(s); |
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} |
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} |
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_STARTPG:
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s->start = val << 8;
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break;
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case EN0_STOPPG:
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s->stop = val << 8;
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break;
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case EN0_BOUNDARY:
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s->boundary = val; |
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break;
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case EN0_IMR:
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s->imr = val; |
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ne2000_update_irq(s); |
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break;
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case EN0_TPSR:
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s->tpsr = val; |
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break;
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case EN0_TCNTLO:
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s->tcnt = (s->tcnt & 0xff00) | val;
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break;
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case EN0_TCNTHI:
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s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
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break;
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case EN0_RSARLO:
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s->rsar = (s->rsar & 0xff00) | val;
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break;
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case EN0_RSARHI:
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s->rsar = (s->rsar & 0x00ff) | (val << 8); |
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break;
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case EN0_RCNTLO:
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s->rcnt = (s->rcnt & 0xff00) | val;
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break;
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case EN0_RCNTHI:
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s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
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break;
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case EN0_DCFG:
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s->dcfg = val; |
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break;
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case EN0_ISR:
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s->isr &= ~(val & 0x7f);
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ne2000_update_irq(s); |
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break;
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case EN1_PHYS ... EN1_PHYS + 5: |
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s->phys[offset - EN1_PHYS] = val; |
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break;
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case EN1_CURPAG:
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s->curpag = val; |
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break;
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case EN1_MULT ... EN1_MULT + 7: |
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s->mult[offset - EN1_MULT] = val; |
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break;
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} |
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} |
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} |
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|
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static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
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{ |
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NE2000State *s = opaque; |
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int offset, page, ret;
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addr &= 0xf;
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if (addr == E8390_CMD) {
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ret = s->cmd; |
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_TSR:
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ret = s->tsr; |
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break;
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case EN0_BOUNDARY:
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ret = s->boundary; |
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break;
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case EN0_ISR:
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ret = s->isr; |
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break;
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case EN0_RSARLO:
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ret = s->rsar & 0x00ff;
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break;
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case EN0_RSARHI:
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ret = s->rsar >> 8;
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break;
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case EN1_PHYS ... EN1_PHYS + 5: |
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ret = s->phys[offset - EN1_PHYS]; |
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break;
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case EN1_CURPAG:
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ret = s->curpag; |
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break;
|
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case EN1_MULT ... EN1_MULT + 7: |
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ret = s->mult[offset - EN1_MULT]; |
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break;
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case EN0_RSR:
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ret = s->rsr; |
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break;
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default:
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ret = 0x00;
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break;
|
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} |
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} |
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#ifdef DEBUG_NE2000
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printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
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#endif
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return ret;
|
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} |
381 |
|
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static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
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uint32_t val) |
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{ |
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if (addr < 32 || |
386 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
387 |
s->mem[addr] = val; |
388 |
} |
389 |
} |
390 |
|
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static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
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uint32_t val) |
393 |
{ |
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
395 |
if (addr < 32 || |
396 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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*(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
398 |
} |
399 |
} |
400 |
|
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static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
402 |
uint32_t val) |
403 |
{ |
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
405 |
if (addr < 32 || |
406 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
407 |
cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
408 |
} |
409 |
} |
410 |
|
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static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
412 |
{ |
413 |
if (addr < 32 || |
414 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
415 |
return s->mem[addr];
|
416 |
} else {
|
417 |
return 0xff; |
418 |
} |
419 |
} |
420 |
|
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static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
422 |
{ |
423 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
424 |
if (addr < 32 || |
425 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
426 |
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
427 |
} else {
|
428 |
return 0xffff; |
429 |
} |
430 |
} |
431 |
|
432 |
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
433 |
{ |
434 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
435 |
if (addr < 32 || |
436 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
437 |
return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
438 |
} else {
|
439 |
return 0xffffffff; |
440 |
} |
441 |
} |
442 |
|
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static inline void ne2000_dma_update(NE2000State *s, int len) |
444 |
{ |
445 |
s->rsar += len; |
446 |
/* wrap */
|
447 |
/* XXX: check what to do if rsar > stop */
|
448 |
if (s->rsar == s->stop)
|
449 |
s->rsar = s->start; |
450 |
|
451 |
if (s->rcnt <= len) {
|
452 |
s->rcnt = 0;
|
453 |
/* signal end of transfert */
|
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s->isr |= ENISR_RDC; |
455 |
ne2000_update_irq(s); |
456 |
} else {
|
457 |
s->rcnt -= len; |
458 |
} |
459 |
} |
460 |
|
461 |
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
462 |
{ |
463 |
NE2000State *s = opaque; |
464 |
|
465 |
#ifdef DEBUG_NE2000
|
466 |
printf("NE2000: asic write val=0x%04x\n", val);
|
467 |
#endif
|
468 |
if (s->rcnt == 0) |
469 |
return;
|
470 |
if (s->dcfg & 0x01) { |
471 |
/* 16 bit access */
|
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ne2000_mem_writew(s, s->rsar, val); |
473 |
ne2000_dma_update(s, 2);
|
474 |
} else {
|
475 |
/* 8 bit access */
|
476 |
ne2000_mem_writeb(s, s->rsar, val); |
477 |
ne2000_dma_update(s, 1);
|
478 |
} |
479 |
} |
480 |
|
481 |
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
482 |
{ |
483 |
NE2000State *s = opaque; |
484 |
int ret;
|
485 |
|
486 |
if (s->dcfg & 0x01) { |
487 |
/* 16 bit access */
|
488 |
ret = ne2000_mem_readw(s, s->rsar); |
489 |
ne2000_dma_update(s, 2);
|
490 |
} else {
|
491 |
/* 8 bit access */
|
492 |
ret = ne2000_mem_readb(s, s->rsar); |
493 |
ne2000_dma_update(s, 1);
|
494 |
} |
495 |
#ifdef DEBUG_NE2000
|
496 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
497 |
#endif
|
498 |
return ret;
|
499 |
} |
500 |
|
501 |
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
502 |
{ |
503 |
NE2000State *s = opaque; |
504 |
|
505 |
#ifdef DEBUG_NE2000
|
506 |
printf("NE2000: asic writel val=0x%04x\n", val);
|
507 |
#endif
|
508 |
if (s->rcnt == 0) |
509 |
return;
|
510 |
/* 32 bit access */
|
511 |
ne2000_mem_writel(s, s->rsar, val); |
512 |
ne2000_dma_update(s, 4);
|
513 |
} |
514 |
|
515 |
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
516 |
{ |
517 |
NE2000State *s = opaque; |
518 |
int ret;
|
519 |
|
520 |
/* 32 bit access */
|
521 |
ret = ne2000_mem_readl(s, s->rsar); |
522 |
ne2000_dma_update(s, 4);
|
523 |
#ifdef DEBUG_NE2000
|
524 |
printf("NE2000: asic readl val=0x%04x\n", ret);
|
525 |
#endif
|
526 |
return ret;
|
527 |
} |
528 |
|
529 |
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
530 |
{ |
531 |
/* nothing to do (end of reset pulse) */
|
532 |
} |
533 |
|
534 |
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
535 |
{ |
536 |
NE2000State *s = opaque; |
537 |
ne2000_reset(s); |
538 |
return 0; |
539 |
} |
540 |
|
541 |
static void ne2000_save(QEMUFile* f,void* opaque) |
542 |
{ |
543 |
NE2000State* s=(NE2000State*)opaque; |
544 |
|
545 |
qemu_put_8s(f, &s->cmd); |
546 |
qemu_put_be32s(f, &s->start); |
547 |
qemu_put_be32s(f, &s->stop); |
548 |
qemu_put_8s(f, &s->boundary); |
549 |
qemu_put_8s(f, &s->tsr); |
550 |
qemu_put_8s(f, &s->tpsr); |
551 |
qemu_put_be16s(f, &s->tcnt); |
552 |
qemu_put_be16s(f, &s->rcnt); |
553 |
qemu_put_be32s(f, &s->rsar); |
554 |
qemu_put_8s(f, &s->rsr); |
555 |
qemu_put_8s(f, &s->isr); |
556 |
qemu_put_8s(f, &s->dcfg); |
557 |
qemu_put_8s(f, &s->imr); |
558 |
qemu_put_buffer(f, s->phys, 6);
|
559 |
qemu_put_8s(f, &s->curpag); |
560 |
qemu_put_buffer(f, s->mult, 8);
|
561 |
qemu_put_be32s(f, &s->irq); |
562 |
qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
563 |
} |
564 |
|
565 |
static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
566 |
{ |
567 |
NE2000State* s=(NE2000State*)opaque; |
568 |
|
569 |
if (version_id != 1) |
570 |
return -EINVAL;
|
571 |
|
572 |
qemu_get_8s(f, &s->cmd); |
573 |
qemu_get_be32s(f, &s->start); |
574 |
qemu_get_be32s(f, &s->stop); |
575 |
qemu_get_8s(f, &s->boundary); |
576 |
qemu_get_8s(f, &s->tsr); |
577 |
qemu_get_8s(f, &s->tpsr); |
578 |
qemu_get_be16s(f, &s->tcnt); |
579 |
qemu_get_be16s(f, &s->rcnt); |
580 |
qemu_get_be32s(f, &s->rsar); |
581 |
qemu_get_8s(f, &s->rsr); |
582 |
qemu_get_8s(f, &s->isr); |
583 |
qemu_get_8s(f, &s->dcfg); |
584 |
qemu_get_8s(f, &s->imr); |
585 |
qemu_get_buffer(f, s->phys, 6);
|
586 |
qemu_get_8s(f, &s->curpag); |
587 |
qemu_get_buffer(f, s->mult, 8);
|
588 |
qemu_get_be32s(f, &s->irq); |
589 |
qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
590 |
|
591 |
return 0; |
592 |
} |
593 |
|
594 |
void isa_ne2000_init(int base, int irq, NetDriverState *nd) |
595 |
{ |
596 |
NE2000State *s; |
597 |
|
598 |
s = qemu_mallocz(sizeof(NE2000State));
|
599 |
if (!s)
|
600 |
return;
|
601 |
|
602 |
register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
603 |
register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
604 |
|
605 |
register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
606 |
register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
607 |
register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
608 |
register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
609 |
|
610 |
register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
611 |
register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
612 |
s->irq = irq; |
613 |
s->nd = nd; |
614 |
|
615 |
ne2000_reset(s); |
616 |
|
617 |
qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s); |
618 |
|
619 |
register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
620 |
|
621 |
} |
622 |
|
623 |
/***********************************************************/
|
624 |
/* PCI NE2000 definitions */
|
625 |
|
626 |
typedef struct PCINE2000State { |
627 |
PCIDevice dev; |
628 |
NE2000State ne2000; |
629 |
} PCINE2000State; |
630 |
|
631 |
static void ne2000_map(PCIDevice *pci_dev, int region_num, |
632 |
uint32_t addr, uint32_t size, int type)
|
633 |
{ |
634 |
PCINE2000State *d = (PCINE2000State *)pci_dev; |
635 |
NE2000State *s = &d->ne2000; |
636 |
|
637 |
register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
638 |
register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
639 |
|
640 |
register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
641 |
register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
642 |
register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
643 |
register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
644 |
register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
645 |
register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
646 |
|
647 |
register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
648 |
register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
649 |
} |
650 |
|
651 |
void pci_ne2000_init(PCIBus *bus, NetDriverState *nd)
|
652 |
{ |
653 |
PCINE2000State *d; |
654 |
NE2000State *s; |
655 |
uint8_t *pci_conf; |
656 |
|
657 |
d = (PCINE2000State *)pci_register_device(bus, |
658 |
"NE2000", sizeof(PCINE2000State), |
659 |
-1,
|
660 |
NULL, NULL); |
661 |
pci_conf = d->dev.config; |
662 |
pci_conf[0x00] = 0xec; // Realtek 8029 |
663 |
pci_conf[0x01] = 0x10; |
664 |
pci_conf[0x02] = 0x29; |
665 |
pci_conf[0x03] = 0x80; |
666 |
pci_conf[0x0a] = 0x00; // ethernet network controller |
667 |
pci_conf[0x0b] = 0x02; |
668 |
pci_conf[0x0e] = 0x00; // header_type |
669 |
pci_conf[0x3d] = 1; // interrupt pin 0 |
670 |
|
671 |
pci_register_io_region(&d->dev, 0, 0x100, |
672 |
PCI_ADDRESS_SPACE_IO, ne2000_map); |
673 |
s = &d->ne2000; |
674 |
s->irq = 16; // PCI interrupt |
675 |
s->pci_dev = (PCIDevice *)d; |
676 |
s->nd = nd; |
677 |
ne2000_reset(s); |
678 |
qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s); |
679 |
|
680 |
/* XXX: instance number ? */
|
681 |
register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
682 |
register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load, |
683 |
&d->dev); |
684 |
} |