Revision 577f25a5 target-ppc/op_helper.c
| b/target-ppc/op_helper.c | ||
|---|---|---|
| 348 | 348 |
|
| 349 | 349 |
void helper_icbi(target_ulong addr) |
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{
|
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uint32_t tmp; |
|
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|
|
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addr &= ~(env->dcache_line_size - 1); |
| 354 | 352 |
/* Invalidate one cache line : |
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* PowerPC specification says this is to be treated like a load |
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* (not a fetch) by the MMU. To be sure it will be so, |
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* do the load "by hand". |
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*/ |
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tmp = ldl(addr);
|
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ldl(addr); |
|
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tb_invalidate_page_range(addr, addr + env->icache_line_size); |
| 361 | 359 |
} |
| 362 | 360 |
|
| ... | ... | |
| 3814 | 3812 |
EPN = env->spr[SPR_DMISS]; |
| 3815 | 3813 |
} |
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way = (env->spr[SPR_SRR1] >> 17) & 1; |
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(void)EPN; /* avoid a compiler warning */ |
|
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LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
|
| 3818 | 3817 |
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP, |
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RPN, way); |
| ... | ... | |
| 3842 | 3841 |
CMP = env->spr[SPR_PTEHI]; |
| 3843 | 3842 |
EPN = env->spr[SPR_TLBMISS] & ~0x3; |
| 3844 | 3843 |
way = env->spr[SPR_TLBMISS] & 0x3; |
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(void)EPN; /* avoid a compiler warning */ |
|
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LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
|
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" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP, |
| 3847 | 3847 |
RPN, way); |
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