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1 | 2488514c | Rob Herring | /*
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2 | 2488514c | Rob Herring | * Calxeda Highbank SoC emulation
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3 | 2488514c | Rob Herring | *
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4 | 2488514c | Rob Herring | * Copyright (c) 2010-2012 Calxeda
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5 | 2488514c | Rob Herring | *
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6 | 2488514c | Rob Herring | * This program is free software; you can redistribute it and/or modify it
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7 | 2488514c | Rob Herring | * under the terms and conditions of the GNU General Public License,
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8 | 2488514c | Rob Herring | * version 2 or later, as published by the Free Software Foundation.
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9 | 2488514c | Rob Herring | *
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10 | 2488514c | Rob Herring | * This program is distributed in the hope it will be useful, but WITHOUT
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11 | 2488514c | Rob Herring | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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12 | 2488514c | Rob Herring | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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13 | 2488514c | Rob Herring | * more details.
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14 | 2488514c | Rob Herring | *
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15 | 2488514c | Rob Herring | * You should have received a copy of the GNU General Public License along with
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16 | 2488514c | Rob Herring | * this program. If not, see <http://www.gnu.org/licenses/>.
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17 | 2488514c | Rob Herring | *
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18 | 2488514c | Rob Herring | */
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19 | 2488514c | Rob Herring | |
20 | 2488514c | Rob Herring | #include "sysbus.h" |
21 | 2488514c | Rob Herring | #include "arm-misc.h" |
22 | 2488514c | Rob Herring | #include "primecell.h" |
23 | 2488514c | Rob Herring | #include "devices.h" |
24 | 2488514c | Rob Herring | #include "loader.h" |
25 | 2488514c | Rob Herring | #include "net.h" |
26 | 2488514c | Rob Herring | #include "sysemu.h" |
27 | 2488514c | Rob Herring | #include "boards.h" |
28 | 2488514c | Rob Herring | #include "sysbus.h" |
29 | 2488514c | Rob Herring | #include "blockdev.h" |
30 | 2488514c | Rob Herring | #include "exec-memory.h" |
31 | 2488514c | Rob Herring | |
32 | 2488514c | Rob Herring | #define SMP_BOOT_ADDR 0x100 |
33 | 2488514c | Rob Herring | #define SMP_BOOT_REG 0x40 |
34 | 2488514c | Rob Herring | #define GIC_BASE_ADDR 0xfff10000 |
35 | 2488514c | Rob Herring | |
36 | 2488514c | Rob Herring | #define NIRQ_GIC 160 |
37 | 2488514c | Rob Herring | |
38 | 2488514c | Rob Herring | /* Board init. */
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39 | 2488514c | Rob Herring | static void highbank_cpu_reset(void *opaque) |
40 | 2488514c | Rob Herring | { |
41 | 2488514c | Rob Herring | CPUState *env = opaque; |
42 | 2488514c | Rob Herring | |
43 | 2488514c | Rob Herring | env->cp15.c15_config_base_address = GIC_BASE_ADDR; |
44 | 2488514c | Rob Herring | } |
45 | 2488514c | Rob Herring | |
46 | 2488514c | Rob Herring | static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info) |
47 | 2488514c | Rob Herring | { |
48 | 2488514c | Rob Herring | int n;
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49 | 2488514c | Rob Herring | uint32_t smpboot[] = { |
50 | 2488514c | Rob Herring | 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ |
51 | 2488514c | Rob Herring | 0xe210000f, /* ands r0, r0, #0x0f */ |
52 | 2488514c | Rob Herring | 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ |
53 | 2488514c | Rob Herring | 0xe0830200, /* add r0, r3, r0, lsl #4 */ |
54 | 2488514c | Rob Herring | 0xe59f2018, /* ldr r2, privbase */ |
55 | 2488514c | Rob Herring | 0xe3a01001, /* mov r1, #1 */ |
56 | 2488514c | Rob Herring | 0xe5821100, /* str r1, [r2, #256] */ |
57 | 2488514c | Rob Herring | 0xe320f003, /* wfi */ |
58 | 2488514c | Rob Herring | 0xe5901000, /* ldr r1, [r0] */ |
59 | 2488514c | Rob Herring | 0xe1110001, /* tst r1, r1 */ |
60 | 2488514c | Rob Herring | 0x0afffffb, /* beq <wfi> */ |
61 | 2488514c | Rob Herring | 0xe12fff11, /* bx r1 */ |
62 | 2488514c | Rob Herring | GIC_BASE_ADDR /* privbase: gic address. */
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63 | 2488514c | Rob Herring | }; |
64 | 2488514c | Rob Herring | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
65 | 2488514c | Rob Herring | smpboot[n] = tswap32(smpboot[n]); |
66 | 2488514c | Rob Herring | } |
67 | 2488514c | Rob Herring | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); |
68 | 2488514c | Rob Herring | } |
69 | 2488514c | Rob Herring | |
70 | 2488514c | Rob Herring | static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info) |
71 | 2488514c | Rob Herring | { |
72 | 2488514c | Rob Herring | switch (info->nb_cpus) {
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73 | 2488514c | Rob Herring | case 4: |
74 | 2488514c | Rob Herring | stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0); |
75 | 2488514c | Rob Herring | case 3: |
76 | 2488514c | Rob Herring | stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0); |
77 | 2488514c | Rob Herring | case 2: |
78 | 2488514c | Rob Herring | stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0); |
79 | 2488514c | Rob Herring | env->regs[15] = SMP_BOOT_ADDR;
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80 | 2488514c | Rob Herring | break;
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81 | 2488514c | Rob Herring | default:
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82 | 2488514c | Rob Herring | break;
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83 | 2488514c | Rob Herring | } |
84 | 2488514c | Rob Herring | } |
85 | 2488514c | Rob Herring | |
86 | 2488514c | Rob Herring | #define NUM_REGS 0x200 |
87 | 2488514c | Rob Herring | static void hb_regs_write(void *opaque, target_phys_addr_t offset, |
88 | 2488514c | Rob Herring | uint64_t value, unsigned size)
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89 | 2488514c | Rob Herring | { |
90 | 2488514c | Rob Herring | uint32_t *regs = opaque; |
91 | 2488514c | Rob Herring | |
92 | 2488514c | Rob Herring | if (offset == 0xf00) { |
93 | 2488514c | Rob Herring | if (value == 1 || value == 2) { |
94 | 2488514c | Rob Herring | qemu_system_reset_request(); |
95 | 2488514c | Rob Herring | } else if (value == 3) { |
96 | 2488514c | Rob Herring | qemu_system_shutdown_request(); |
97 | 2488514c | Rob Herring | } |
98 | 2488514c | Rob Herring | } |
99 | 2488514c | Rob Herring | |
100 | 2488514c | Rob Herring | regs[offset/4] = value;
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101 | 2488514c | Rob Herring | } |
102 | 2488514c | Rob Herring | |
103 | 2488514c | Rob Herring | static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset, |
104 | 2488514c | Rob Herring | unsigned size)
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105 | 2488514c | Rob Herring | { |
106 | 2488514c | Rob Herring | uint32_t *regs = opaque; |
107 | 2488514c | Rob Herring | uint32_t value = regs[offset/4];
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108 | 2488514c | Rob Herring | |
109 | 2488514c | Rob Herring | if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { |
110 | 2488514c | Rob Herring | value |= 0x30000000;
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111 | 2488514c | Rob Herring | } |
112 | 2488514c | Rob Herring | |
113 | 2488514c | Rob Herring | return value;
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114 | 2488514c | Rob Herring | } |
115 | 2488514c | Rob Herring | |
116 | 2488514c | Rob Herring | static const MemoryRegionOps hb_mem_ops = { |
117 | 2488514c | Rob Herring | .read = hb_regs_read, |
118 | 2488514c | Rob Herring | .write = hb_regs_write, |
119 | 2488514c | Rob Herring | .endianness = DEVICE_NATIVE_ENDIAN, |
120 | 2488514c | Rob Herring | }; |
121 | 2488514c | Rob Herring | |
122 | 2488514c | Rob Herring | typedef struct { |
123 | 2488514c | Rob Herring | SysBusDevice busdev; |
124 | 2488514c | Rob Herring | MemoryRegion *iomem; |
125 | 2488514c | Rob Herring | uint32_t regs[NUM_REGS]; |
126 | 2488514c | Rob Herring | } HighbankRegsState; |
127 | 2488514c | Rob Herring | |
128 | 2488514c | Rob Herring | static VMStateDescription vmstate_highbank_regs = {
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129 | 2488514c | Rob Herring | .name = "highbank-regs",
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130 | 2488514c | Rob Herring | .version_id = 0,
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131 | 2488514c | Rob Herring | .minimum_version_id = 0,
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132 | 2488514c | Rob Herring | .minimum_version_id_old = 0,
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133 | 2488514c | Rob Herring | .fields = (VMStateField[]) { |
134 | 2488514c | Rob Herring | VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), |
135 | 2488514c | Rob Herring | VMSTATE_END_OF_LIST(), |
136 | 2488514c | Rob Herring | }, |
137 | 2488514c | Rob Herring | }; |
138 | 2488514c | Rob Herring | |
139 | 2488514c | Rob Herring | static void highbank_regs_reset(DeviceState *dev) |
140 | 2488514c | Rob Herring | { |
141 | 2488514c | Rob Herring | SysBusDevice *sys_dev = sysbus_from_qdev(dev); |
142 | 2488514c | Rob Herring | HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev); |
143 | 2488514c | Rob Herring | |
144 | 2488514c | Rob Herring | s->regs[0x40] = 0x05F20121; |
145 | 2488514c | Rob Herring | s->regs[0x41] = 0x2; |
146 | 2488514c | Rob Herring | s->regs[0x42] = 0x05F30121; |
147 | 2488514c | Rob Herring | s->regs[0x43] = 0x05F40121; |
148 | 2488514c | Rob Herring | } |
149 | 2488514c | Rob Herring | |
150 | 2488514c | Rob Herring | static int highbank_regs_init(SysBusDevice *dev) |
151 | 2488514c | Rob Herring | { |
152 | 2488514c | Rob Herring | HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev); |
153 | 2488514c | Rob Herring | |
154 | 2488514c | Rob Herring | s->iomem = g_new(MemoryRegion, 1);
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155 | 2488514c | Rob Herring | memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
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156 | 2488514c | Rob Herring | 0x1000);
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157 | 2488514c | Rob Herring | sysbus_init_mmio(dev, s->iomem); |
158 | 2488514c | Rob Herring | |
159 | 2488514c | Rob Herring | return 0; |
160 | 2488514c | Rob Herring | } |
161 | 2488514c | Rob Herring | |
162 | 999e12bb | Anthony Liguori | static void highbank_regs_class_init(ObjectClass *klass, void *data) |
163 | 999e12bb | Anthony Liguori | { |
164 | 999e12bb | Anthony Liguori | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
165 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
166 | 999e12bb | Anthony Liguori | |
167 | 999e12bb | Anthony Liguori | sbc->init = highbank_regs_init; |
168 | 39bffca2 | Anthony Liguori | dc->desc = "Calxeda Highbank registers";
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169 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_highbank_regs; |
170 | 39bffca2 | Anthony Liguori | dc->reset = highbank_regs_reset; |
171 | 999e12bb | Anthony Liguori | } |
172 | 999e12bb | Anthony Liguori | |
173 | 39bffca2 | Anthony Liguori | static TypeInfo highbank_regs_info = {
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174 | 39bffca2 | Anthony Liguori | .name = "highbank-regs",
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175 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
176 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(HighbankRegsState),
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177 | 39bffca2 | Anthony Liguori | .class_init = highbank_regs_class_init, |
178 | 2488514c | Rob Herring | }; |
179 | 2488514c | Rob Herring | |
180 | 2488514c | Rob Herring | static void highbank_regs_register_device(void) |
181 | 2488514c | Rob Herring | { |
182 | 39bffca2 | Anthony Liguori | type_register_static(&highbank_regs_info); |
183 | 2488514c | Rob Herring | } |
184 | 2488514c | Rob Herring | |
185 | 2488514c | Rob Herring | device_init(highbank_regs_register_device) |
186 | 2488514c | Rob Herring | |
187 | 2488514c | Rob Herring | static struct arm_boot_info highbank_binfo; |
188 | 2488514c | Rob Herring | |
189 | 2488514c | Rob Herring | /* ram_size must be set to match the upper bound of memory in the
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190 | 2488514c | Rob Herring | * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
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191 | 2488514c | Rob Herring | * normally 0xff900000 or -m 4089. When running this board on a
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192 | 2488514c | Rob Herring | * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
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193 | 2488514c | Rob Herring | * device tree and pass -m 2047 to QEMU.
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194 | 2488514c | Rob Herring | */
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195 | 2488514c | Rob Herring | static void highbank_init(ram_addr_t ram_size, |
196 | 2488514c | Rob Herring | const char *boot_device, |
197 | 2488514c | Rob Herring | const char *kernel_filename, const char *kernel_cmdline, |
198 | 2488514c | Rob Herring | const char *initrd_filename, const char *cpu_model) |
199 | 2488514c | Rob Herring | { |
200 | 2488514c | Rob Herring | CPUState *env = NULL;
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201 | 2488514c | Rob Herring | DeviceState *dev; |
202 | 2488514c | Rob Herring | SysBusDevice *busdev; |
203 | 2488514c | Rob Herring | qemu_irq *irqp; |
204 | 2488514c | Rob Herring | qemu_irq pic[128];
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205 | 2488514c | Rob Herring | int n;
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206 | 2488514c | Rob Herring | qemu_irq cpu_irq[4];
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207 | 2488514c | Rob Herring | MemoryRegion *sysram; |
208 | 2488514c | Rob Herring | MemoryRegion *dram; |
209 | 2488514c | Rob Herring | MemoryRegion *sysmem; |
210 | 2488514c | Rob Herring | char *sysboot_filename;
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211 | 2488514c | Rob Herring | |
212 | 2488514c | Rob Herring | if (!cpu_model) {
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213 | 2488514c | Rob Herring | cpu_model = "cortex-a9";
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214 | 2488514c | Rob Herring | } |
215 | 2488514c | Rob Herring | |
216 | 2488514c | Rob Herring | for (n = 0; n < smp_cpus; n++) { |
217 | 2488514c | Rob Herring | env = cpu_init(cpu_model); |
218 | 2488514c | Rob Herring | if (!env) {
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219 | 2488514c | Rob Herring | fprintf(stderr, "Unable to find CPU definition\n");
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220 | 2488514c | Rob Herring | exit(1);
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221 | 2488514c | Rob Herring | } |
222 | 2488514c | Rob Herring | irqp = arm_pic_init_cpu(env); |
223 | 2488514c | Rob Herring | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
224 | 2488514c | Rob Herring | qemu_register_reset(highbank_cpu_reset, env); |
225 | 2488514c | Rob Herring | } |
226 | 2488514c | Rob Herring | |
227 | 2488514c | Rob Herring | sysmem = get_system_memory(); |
228 | 2488514c | Rob Herring | dram = g_new(MemoryRegion, 1);
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229 | 2488514c | Rob Herring | memory_region_init_ram(dram, "highbank.dram", ram_size);
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230 | 2488514c | Rob Herring | /* SDRAM at address zero. */
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231 | 2488514c | Rob Herring | memory_region_add_subregion(sysmem, 0, dram);
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232 | 2488514c | Rob Herring | |
233 | 2488514c | Rob Herring | sysram = g_new(MemoryRegion, 1);
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234 | 2488514c | Rob Herring | memory_region_init_ram(sysram, "highbank.sysram", 0x8000); |
235 | 2488514c | Rob Herring | memory_region_add_subregion(sysmem, 0xfff88000, sysram);
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236 | 2488514c | Rob Herring | if (bios_name != NULL) { |
237 | 2488514c | Rob Herring | sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
238 | 2488514c | Rob Herring | if (sysboot_filename != NULL) { |
239 | 2488514c | Rob Herring | uint32_t filesize = get_image_size(sysboot_filename); |
240 | 2488514c | Rob Herring | if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) { |
241 | 2488514c | Rob Herring | hw_error("Unable to load %s\n", bios_name);
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242 | 2488514c | Rob Herring | } |
243 | 2488514c | Rob Herring | } else {
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244 | 2488514c | Rob Herring | hw_error("Unable to find %s\n", bios_name);
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245 | 2488514c | Rob Herring | } |
246 | 2488514c | Rob Herring | } |
247 | 2488514c | Rob Herring | |
248 | 2488514c | Rob Herring | dev = qdev_create(NULL, "a9mpcore_priv"); |
249 | 2488514c | Rob Herring | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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250 | 2488514c | Rob Herring | qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
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251 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
252 | 2488514c | Rob Herring | busdev = sysbus_from_qdev(dev); |
253 | 2488514c | Rob Herring | sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
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254 | 2488514c | Rob Herring | for (n = 0; n < smp_cpus; n++) { |
255 | 2488514c | Rob Herring | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
256 | 2488514c | Rob Herring | } |
257 | 2488514c | Rob Herring | |
258 | 2488514c | Rob Herring | for (n = 0; n < 128; n++) { |
259 | 2488514c | Rob Herring | pic[n] = qdev_get_gpio_in(dev, n); |
260 | 2488514c | Rob Herring | } |
261 | 2488514c | Rob Herring | |
262 | 2488514c | Rob Herring | dev = qdev_create(NULL, "l2x0"); |
263 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
264 | 2488514c | Rob Herring | busdev = sysbus_from_qdev(dev); |
265 | 2488514c | Rob Herring | sysbus_mmio_map(busdev, 0, 0xfff12000); |
266 | 2488514c | Rob Herring | |
267 | 2488514c | Rob Herring | dev = qdev_create(NULL, "sp804"); |
268 | 2488514c | Rob Herring | qdev_prop_set_uint32(dev, "freq0", 150000000); |
269 | 2488514c | Rob Herring | qdev_prop_set_uint32(dev, "freq1", 150000000); |
270 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
271 | 2488514c | Rob Herring | busdev = sysbus_from_qdev(dev); |
272 | 2488514c | Rob Herring | sysbus_mmio_map(busdev, 0, 0xfff34000); |
273 | 2488514c | Rob Herring | sysbus_connect_irq(busdev, 0, pic[18]); |
274 | 2488514c | Rob Herring | sysbus_create_simple("pl011", 0xfff36000, pic[20]); |
275 | 2488514c | Rob Herring | |
276 | 2488514c | Rob Herring | dev = qdev_create(NULL, "highbank-regs"); |
277 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
278 | 2488514c | Rob Herring | busdev = sysbus_from_qdev(dev); |
279 | 2488514c | Rob Herring | sysbus_mmio_map(busdev, 0, 0xfff3c000); |
280 | 2488514c | Rob Herring | |
281 | 2488514c | Rob Herring | sysbus_create_simple("pl061", 0xfff30000, pic[14]); |
282 | 2488514c | Rob Herring | sysbus_create_simple("pl061", 0xfff31000, pic[15]); |
283 | 2488514c | Rob Herring | sysbus_create_simple("pl061", 0xfff32000, pic[16]); |
284 | 2488514c | Rob Herring | sysbus_create_simple("pl061", 0xfff33000, pic[17]); |
285 | 2488514c | Rob Herring | sysbus_create_simple("pl031", 0xfff35000, pic[19]); |
286 | 2488514c | Rob Herring | sysbus_create_simple("pl022", 0xfff39000, pic[23]); |
287 | 2488514c | Rob Herring | |
288 | 2488514c | Rob Herring | sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); |
289 | 2488514c | Rob Herring | |
290 | 2488514c | Rob Herring | if (nd_table[0].vlan) { |
291 | 2488514c | Rob Herring | qemu_check_nic_model(&nd_table[0], "xgmac"); |
292 | 2488514c | Rob Herring | dev = qdev_create(NULL, "xgmac"); |
293 | 2488514c | Rob Herring | qdev_set_nic_properties(dev, &nd_table[0]);
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294 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
295 | 2488514c | Rob Herring | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000); |
296 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]); |
297 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]); |
298 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]); |
299 | 2488514c | Rob Herring | |
300 | 2488514c | Rob Herring | qemu_check_nic_model(&nd_table[1], "xgmac"); |
301 | 2488514c | Rob Herring | dev = qdev_create(NULL, "xgmac"); |
302 | 2488514c | Rob Herring | qdev_set_nic_properties(dev, &nd_table[1]);
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303 | 2488514c | Rob Herring | qdev_init_nofail(dev); |
304 | 2488514c | Rob Herring | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000); |
305 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]); |
306 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]); |
307 | 2488514c | Rob Herring | sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]); |
308 | 2488514c | Rob Herring | } |
309 | 2488514c | Rob Herring | |
310 | 2488514c | Rob Herring | highbank_binfo.ram_size = ram_size; |
311 | 2488514c | Rob Herring | highbank_binfo.kernel_filename = kernel_filename; |
312 | 2488514c | Rob Herring | highbank_binfo.kernel_cmdline = kernel_cmdline; |
313 | 2488514c | Rob Herring | highbank_binfo.initrd_filename = initrd_filename; |
314 | 2488514c | Rob Herring | /* highbank requires a dtb in order to boot, and the dtb will override
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315 | 2488514c | Rob Herring | * the board ID. The following value is ignored, so set it to -1 to be
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316 | 2488514c | Rob Herring | * clear that the value is meaningless.
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317 | 2488514c | Rob Herring | */
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318 | 2488514c | Rob Herring | highbank_binfo.board_id = -1;
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319 | 2488514c | Rob Herring | highbank_binfo.nb_cpus = smp_cpus; |
320 | 2488514c | Rob Herring | highbank_binfo.loader_start = 0;
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321 | 2488514c | Rob Herring | highbank_binfo.write_secondary_boot = hb_write_secondary; |
322 | 2488514c | Rob Herring | highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; |
323 | 2488514c | Rob Herring | arm_load_kernel(first_cpu, &highbank_binfo); |
324 | 2488514c | Rob Herring | } |
325 | 2488514c | Rob Herring | |
326 | 2488514c | Rob Herring | static QEMUMachine highbank_machine = {
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327 | 2488514c | Rob Herring | .name = "highbank",
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328 | 2488514c | Rob Herring | .desc = "Calxeda Highbank (ECX-1000)",
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329 | 2488514c | Rob Herring | .init = highbank_init, |
330 | 2488514c | Rob Herring | .use_scsi = 1,
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331 | 2488514c | Rob Herring | .max_cpus = 4,
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332 | 2488514c | Rob Herring | }; |
333 | 2488514c | Rob Herring | |
334 | 2488514c | Rob Herring | static void highbank_machine_init(void) |
335 | 2488514c | Rob Herring | { |
336 | 2488514c | Rob Herring | qemu_register_machine(&highbank_machine); |
337 | 2488514c | Rob Herring | } |
338 | 2488514c | Rob Herring | |
339 | 2488514c | Rob Herring | machine_init(highbank_machine_init); |