Makefile: Add missing dependency for system emulation (fix build)
Comment from Makefile.objs:
The system emulation needs this dependency (which was missing in Makefile),otherwise builds without tools (or massive parallel builds) fail.
Signed-off-by: Stefan Weil <sw@weilnetz.de>...
modules: Fix building with --enable-modules
Compiling util/modules.c with modules enabled fails now.
Fix it by including qemu-common.h before #ifdef testing in module.c.
Signed-off-by: Fam Zheng <famz@redhat.com>Message-id: 1393453893-12125-1-git-send-email-famz@redhat.com...
Merge remote-tracking branch 'remotes/kvm/uq/master' into staging
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-20140226.0' into staging
Updates include: - Coverify fixes for vfio & pci-assign (Markus) - VFIO blacklisting support for known brokwn PCI option ROMs (Bandan)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140226' into staging
target-arm queue: * fixes for various Coverity-spotted bugs * support new KVM device control API for VGIC * support KVM VGIC save/restore/migration * more AArch64 system mode foundations...
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140225' into staging
migration/next for 20140225
Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into staging
Net patches
Merge remote-tracking branch 'remotes/kraxel/tags/pull-audio-3' into staging
hda-audio: qom cleanups
vfio: blacklist loading of unstable roms
Certain cards such as the Broadcom BCM57810 have rom quirksthat exhibit unstable system behavior duing device assignment. Inthe particular case of 57810, rom execution hangs and if a FLRfollows, the device becomes inoperable until a power cycle. This...
qdev-monitor: set DeviceState opts before calling realize
Setting opts before the realize property is set allows thefollowing patch to make decisions based on whether the userspecified "rombar". This also avoids having to create a newtristate property especially for this purpose...
pci-assign: Fix potential read beyond buffer on -EBUSY
readlink() doesn't write a terminating null byte.assign_failed_examine() passes the unterminated string to strrchr().Oops. Terminate it.
Spotted by Coverity.
Signed-off-by: Markus Armbruster <armbru@redhat.com>...
vfio: Fix overrun after readlink() fills buffer completely
readlink() returns the number of bytes written to the buffer, and itdoesn't write a terminating null byte. vfio_init() writes it itself.Overruns the buffer when readlink() filled it completely....
dma/pl330: implement dmaadnh instruction
Implement the missing DMAADNH instruction. This is a minor variantof the DMAADDH instruction, so factor out to a common implementationfor both (dmaadxh).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
dma/pl330: Fix misleading type
This type really should just be a regular int as no usages rely on it's32 bitness (it's only meaningful as a bit position and not a bit mask).This also fixes a printf which uses the variable with a regular %d.
dma/pl330: printf format type sweep.
Use PRI formats as appropriate rather than raw %x and %d. This fixesdebug printfery on some host platforms. Fix types of debug onlyvariables as appropriate.
dma/pl330: Rename parent_obj
As per current QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: abb137347ea1ee9c31487b544f3d5435fb17f6a4.1393372019.git.peter.crosthwaite@xilinx.com...
dma/pl330: Add event debugging printfs
These are helpful to anyone trying to debug event sequencing.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: e82a0ad804db3de4f46839e55a9d287735ef870d.1393372019.git.peter.crosthwaite@xilinx.com...
dma/pl330: Fix buffer depth
This is the product of the data-width and the depth arguments, I.e thedepth of the FIFO is in terms of data entries and not bytes (which iswhat the original implementation was suggesting). Fix.
target-arm: Add utility function for checking AA32/64 state of an EL
There are various situations where we need to behave differentlydepending on whether a given exception level is in AArch64 orAArch32 state. The state of the current exception level is stored...
include/qemu/crc32c.h: Rename include guards to match filename
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1393411566-24104-2-git-send-email-will.newton@linaro.orgSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation...
dma/pl330: Delete overly verbose debug printf
When using event synchronisation, this particular debug printf floods.Just delete it.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: dd94d19493f97c47497b9d8caf74ca43e70d58fd.1393372019.git.peter.crosthwaite@xilinx.com...
target-arm: A64: Implement WFI
Implement the WFI instruction for A64; this just involves wiringup the instruction, and adding a gen_a64_set_pc_im() which wasaccidentally omitted from the A64 decoder top loop.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need tocare about whether EL1 is AArch32 or AArch64, we should storethe interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIFin AArch64) in one place consistently regardless of EL1's mode....
target-arm: A64: Implement MSR (immediate) instructions
Implement the MSR (immediate) instructions, which can update thePSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64CPACR is defined to have a lot of RES0 bits, but sincethe architecture defines that RES0 bits may be implementedas reads-as-written and we know that a v8 CPU will have...
target-arm: Implement AArch64 generic timers
Implement the AArch64 view of the generic timer system registers.
target-arm: Implement AArch64 ID and feature registers
Implement the AArch64-specific ID and feature registers. Althoughmany of these are currently not used by the architecture (and soalways zero for all implementations), we define the full set offields in the ARMCPU struct for symmetry....
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
In AArch64 the breakpoint and watchpoint registers are mandatory, so thekernel always accesses them on bootup. Implement dummy versions, whichread as written but have no actual effect....
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Define a dummy version of the AArch64 OSLAR_EL1 system registerwhich just ignores writes. Linux will always write to this (itis the OS lock used for debugging), but we don't support debug.
target-arm: Get MMU index information correct for A64 code
Emit the correct MMU index information for loads and stores fromA64 code, rather than hardwiring it to "always kernel mode",by storing the exception level in the TB flags, and makecpu_mmu_index() return the right answer when the CPU is in...
target-arm: Implement AArch64 TCR_EL1
Implement the AArch64 TCR_EL1, which is the 64 bit view ofthe AArch32 TTBCR. (The uses of the bits in the register arecompletely different, but in any given situation the CPU willalways interpret them one way or the other. In fact for QEMU EL1...
target-arm: Implement AArch64 VBAR_EL1
Implement the A64 view of the VBAR system register.
target-arm: Implement AArch64 TTBR*
Implement the AArch64 TTBR* registers. For v7 these were already 64 bitsto handle LPAE, but implemented as two separate uint32_t fields.Combine them into a single uint64_t which can be used for all purposes.Since this requires touching every use, take the opportunity to rename...
target-arm: Implement AArch64 MPIDR
Implement the AArch64 MPIDR system register.
target-arm: Implement AArch64 TLB invalidate ops
Implement the AArch64 TLB invalidate operations. This isthe full set of TLBI ops defined for a CPU which doesn'timplement EL2 or EL3.
target-arm: Implement AArch64 dummy MDSCR_EL1
We don't support letting the guest do debug, but Linux prods themonitor debug system control register anyway, so implement a dummyRAZ/WI version.
target-arm: Implement AArch64 memory attribute registers
Implement the AArch64 memory attribute registers. Since QEMU doesn'tmodel caches it does not need to care about memory attributes at all,and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR...
target-arm: Implement AArch64 SCTLR_EL1
Implement the AArch64 view of the system control register SCTLR_EL1.
target-arm: Implement AArch64 CurrentEL sysreg
Implement the CurrentEL sysreg.
target-arm: Implement AArch64 MIDR_EL1
Implement the AArch64 view of the MIDR system register(for AArch64 it is a simple constant, unlike the complicatedmess that TI925 imposes on the 32-bit view).
target-arm: Implement AArch64 cache invalidate/clean ops
Implement all the AArch64 cache invalidate and clean ops(which are all NOPs since QEMU doesn't emulate the cache).The only remaining unimplemented cache op is DC ZVA.
hw: arm_gic_kvm: Add KVM VGIC save/restore logic
Save and restore the ARM KVM VGIC state from the kernel. We rely onQEMU to marshal the GICState data structure and therefore simplysynchronize the kernel state with the QEMU emulated state in bothdirections....
target-arm: Fix raw read and write functions on AArch64 registers
The raw read and write functions were using the ARM_CP_64BIT flag inri->type to determine whether to treat the register's state field asuint32_t or uint64_t; however AArch64 register info structs don't use...
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)visible to AArch64. These are mostly simple 64-bit extensions of theexisting 32 bit system registers and so can share reginfo definitions....
linux-headers: Update from v3.14-rc3
Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2)
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>Message-id: 1392687720-26806-2-git-send-email-christoffer.dall@linaro.orgSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
kvm: Introduce kvm_arch_irqchip_create
Introduce kvm_arch_irqchip_create an arch-specific hook in preparationfor architecture-specific use of the device control API to create IRQchips.
Following patches will implement the ARM irqchip create method to prefer...
kvm: Common device control API functions
Introduces two simple functions: int kvm_device_ioctl(int fd, int type, ...); int kvm_create_device(KVMState *s, uint64_t type, bool test);
These functions wrap the basic ioctl-based interactions with KVM in a...
arm: vgic device control api support
Support creating the ARM vgic device through the device control API andsetting the base address for the distributor and cpu interfaces in KVMVMs using this API.
Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be...
hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registers
The ethernet device in the musicpal only has two tx queues,but we modelled it with four CTDP registers, presumably acut and paste from the rx queue registers. Since the tx_queue[]array is only 2 entries long this allowed a guest to overrun...
target-arm: Load correct access bits from ARMv5 level 2 page table descriptors
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split intofour subpages, each of which can have different access permission settings,which are specified by four two-bit fields in the l2 descriptor. A...
hw/intc/arm_gic: Fix GIC_SET_LEVEL
The GIC_SET_LEVEL macro unfortunately overwrote the entire levelbitmask instead of just or'ing on the necessary bits, causing activelevel PPIs on a core to clear PPIs on other cores.
Cc: qemu-stable@nongnu.orgReported-by: Rob Herring <rob.herring@linaro.org>...
hw/net/stellaris_enet: Avoid unintended sign extension
Add a cast to avoid an unintended sign extension thatwould mean we returned 0xffffffff in the high 32 bitsfor an IA0 read if bit 31 in the MAC address was 1.(This is harmless since we'll only be doing 4 byte...
hw/timer/arm_timer: Avoid array overrun for bad addresses
The integrator's timer read/write functions log an error forbad addresses in guest accesses, but were falling through andusing an out of bounds array index rather than returning early.Fix this....
target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops
Correct some obviously nonsensical bit manipulation spotted by Coveritywhen constructing the short-form PAR value for ATS operations.
hw/intc/exynos4210_combiner: Don't overrun output_irq array in init
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;use the correct constant in the loop initializing our outputsysbus IRQs so that we don't overrun the output_irq[] array....
hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses
Fix incorrect use of sizeof() rather than ARRAY_SIZE() to guardaccesses into the mb_clock[] array, which was allowing a maliciousguest to overwrite the end of the array.
microblaze/s3adsp_1800: Define macros for irq map
Define macros for the interrupt map for the sake of self documentation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
ppc/virtex_ml507: Define macros for irq/memory maps
Define macros for the interrupt and memory maps for the sake of selfdocumentation.
microblaze/ml605: Define macros for irq/memory maps
Define (missing) macros for the interrupt and memory maps for the sakeof self documentation.
xilinx: Inline usages of xilinx_intc_create()
Inline these usages. Converts these init to at least a semi-recent QOMstyling.
xilinx: Inline usages of xilinx_timer_create()
xilinx: Inline usage of xilinx_ethlite_create()
Inline the only usage. Converts this init to at least a semi-recent QOMstyling.
xilinx: Inline usages of xilinx_axi*_init()
Inline the only usage of each of xilinx_axiethernet_init andxilinx_axidma_init. Converts this init to at least a semi-recent QOMstyling.
xilinx: Delete hw/include/xilinx.h
This is now obsolete - remove the header and all its inclusions.
modules: do not include gmodule-2.0 in static builds
gmodule-2.0's pkg-config files include -Wl,--export-dynamic, which breaksstatic builds. It is a glib bug, but we need to support --static builds forthe linux-user targets, and in the end all that is needed to fix this is:...
Merge remote-tracking branch 'remotes/spice/tags/pull-spice-3' into staging
qxl: add sanity check
net: remove implicit peer from offload API
The virtio_net offload APIs are used on the NIC's peer (i.e. the tapdevice). The API was defined to implicitly use nc->peer, saving thecaller the trouble.
This wasn't ideal because:1. There are callers who have the peer but not the NIC. Currently they...
vhost_net: use offload API instead of bypassing it
There is no need to access backend->info->has_vnet_hdr() and friendsanymore. Use the qemu_has_vnet_hdr() API instead.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
virtio-net: use qemu_get_queue() where possible
qemu_get_queue() is a shorthand for qemu_get_subqueue(n->nic, 0). Usethe shorthand where possible.
Fix vmstate_info_int32_le comparison/assign
Fix comparison of vmstate_info_int32_le so that it succeeds if loadedvalue is (l)ess than or (e)qual
When the comparison succeeds, assign the value loaded This is a change in behaviour but I think the original intent, since...
Fix two XBZRLE corruption issues
Push zero'd pages into the XBZRLE cache A page that was cached by XBZRLE, zero'd and then XBZRLE'd again was being compared against a stale cache value
Don't use 'qemu_put_buffer_async' to put pages from the XBZRLE cache...
rdma: rename 'x-rdma' => 'rdma'
As far as we can tell, all known bugs have been fixed:
1. Parallel migrations are working2. IPv6 migration is working3. virt-test is working
I'm not comfortable sending the revised libvirt patchuntil this is accepted or review suggestions are addressed,...
qemu_file: use fwrite() correctly
fwrite() returns the number of items written. But when there is oneerror, it can return a short write.
In the particular bug that I was tracking, I did a migration to aread-only filesystem. And it was able to finish the migration...
Merge remote-tracking branch 'remotes/mdroth/qga-pull-2014-02-24' into staging
Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into staging
Xtensa fixes and improvements queue 2014-02-24:- add support for ML605 and KC705 FPGA boards;- flush opencores_eth queue when new RX descriptor is available;- add basic checks to cache opcodes;...
net: extend NetClientInfo for offloading
Some new callbacks have been added to generalize the operations doneby virtio-net and vmxnet3 frontends to manipulate TAP offloadings.
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
net: TAP uses NetClientInfo offloading callbacks
The TAP NetClientInfo structure is inizialized with the TAP-specificfunctions that manipulates offloading features.
net: virtio-net and vmxnet3 use offloading API
With this patch, virtio-net and vmxnet3 frontends makeuse of the qemu_peer_* API for backend offloadings manipulations,instead of calling TAP-specific functions directly.We also remove the existing checks which prevent those frontends...
net: make tap offloading callbacks static
Since TAP offloadings are manipulated through a new API, it'snot necessary to export them in include/net/tap.h anymore.
net: add offloading support to netmap backend
Whit this patch, the netmap backend supports TSO/UFO/CSUMoffloadings, and accepts the virtio-net header, similarly to whathappens with TAP. The offloading callbacks in the NetClientInfointerface have been implemented....
net: Disable netmap backend when not supported
This patch fixes configure so that the netmap backend is not compiled in if thehost doesn't support an API version >= 11. A version upper bound (15) has beenadded so that the netmap API can be extended with some minor features without...
opencores_eth: flush queue whenever can_receive can go from false to true
The following registers control whether MAC can receive frames:- MODER.RXEN bit that enables/disables receiver;- TX_BD_NUM register that specifies number of RX descriptors.Notify QEMU networking core when the MAC is ready to receive frames....
net: change vnet-hdr TAP prototypes
The tap_has_vnet_hdr() and tap_has_vnet_hdr_len() functions usedto return int, even though they only return true/false values.This patch changes the prototypes to return bool.
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>...
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block patches
Merge remote-tracking branch 'remotes/sstabellini/xen-140220' into staging
Merge remote-tracking branch 'remotes/bonzini/configure' into staging
configure: check that C++ compiler actually works
Check that the C++ compiler works with the C compiler; if itdoes not, then don't pass CXX to the build process. Thisfixes a regression where QEMU was no longer building if thebuild environment didn't have a C++ compiler (introduced...
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Add HDA_AUDIO type and macro, drop DO_UPCAST().
Had to add a abstract hda audio class as parentfor all hda-* variants to make that fly. Killedsome init code duplication while being at it.
Cc: Andreas Färber <afaerber@suse.de>...
target-xtensa: add basic tests for cache opcodes
Test that non-locking prefetch operations don't cause exceptions onmissing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into singleDEFAULT_SECTIONS macro for all cores. This allows to add new features ina single place: overlay_tool.h
target-xtensa: provide HW confg ID registers
hw/xtensa: add support for ML605 and KC705 FPGA board
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>
target-xtensa: add RRRI4 opcode format fields
This encoding is used by cache instructions.
target-xtensa: add basic checks to dcache opcodes
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,DIWBI, DPFL are privileged), memory accessibility for instructions thatreference memory (all DH* and DPFL) and windowed register validity for all...
target-xtensa: add basic checks to icache opcodes
Check privilege level for privileged instructions (IHU, III, IIU and IPFLare privileged), memory accessibility for instructions that reference memory(IH* and IPFL) and windowed register validity for all instruction cache...
target-xtensa: add overridable test_init macro
Some test suites, like MMU, need per-test initialization. Don't make themredefine test macro, add test_init for that purpose.
target-xtensa: allow using core configuration in tests
Add path to the core configuration directory to test build command andreplace .include asm directive with #include to enable preprocessing.