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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation micro-operations for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger (FPU operations)
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6 | 93b12ccc | ths | * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
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7 | 6af0bf9c | bellard | *
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8 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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9 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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10 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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11 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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12 | 6af0bf9c | bellard | *
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13 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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14 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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16 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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17 | 6af0bf9c | bellard | *
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18 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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19 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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20 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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21 | 6af0bf9c | bellard | */
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22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #include "config.h" |
24 | 6af0bf9c | bellard | #include "exec.h" |
25 | 05f778c8 | ths | #include "host-utils.h" |
26 | 6af0bf9c | bellard | |
27 | 1b351e52 | bellard | #ifndef CALL_FROM_TB0
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28 | 5a5012ec | ths | #define CALL_FROM_TB0(func) func()
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29 | 1b351e52 | bellard | #endif
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30 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1
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31 | 5a5012ec | ths | #define CALL_FROM_TB1(func, arg0) func(arg0)
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32 | 1b351e52 | bellard | #endif
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33 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1_CONST16
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34 | 5a5012ec | ths | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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35 | 1b351e52 | bellard | #endif
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36 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2
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37 | 5a5012ec | ths | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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38 | 1b351e52 | bellard | #endif
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39 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2_CONST16
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40 | 1b351e52 | bellard | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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41 | 5a5012ec | ths | CALL_FROM_TB2(func, arg0, arg1) |
42 | 1b351e52 | bellard | #endif
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43 | 1b351e52 | bellard | #ifndef CALL_FROM_TB3
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44 | 5a5012ec | ths | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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45 | 1b351e52 | bellard | #endif
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46 | 1b351e52 | bellard | #ifndef CALL_FROM_TB4
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47 | 1b351e52 | bellard | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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48 | 5a5012ec | ths | func(arg0, arg1, arg2, arg3) |
49 | 1b351e52 | bellard | #endif
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50 | 1b351e52 | bellard | |
51 | 6af0bf9c | bellard | #define REG 1 |
52 | 6af0bf9c | bellard | #include "op_template.c" |
53 | 6af0bf9c | bellard | #undef REG
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54 | 6af0bf9c | bellard | #define REG 2 |
55 | 6af0bf9c | bellard | #include "op_template.c" |
56 | 6af0bf9c | bellard | #undef REG
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57 | 6af0bf9c | bellard | #define REG 3 |
58 | 6af0bf9c | bellard | #include "op_template.c" |
59 | 6af0bf9c | bellard | #undef REG
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60 | 6af0bf9c | bellard | #define REG 4 |
61 | 6af0bf9c | bellard | #include "op_template.c" |
62 | 6af0bf9c | bellard | #undef REG
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63 | 6af0bf9c | bellard | #define REG 5 |
64 | 6af0bf9c | bellard | #include "op_template.c" |
65 | 6af0bf9c | bellard | #undef REG
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66 | 6af0bf9c | bellard | #define REG 6 |
67 | 6af0bf9c | bellard | #include "op_template.c" |
68 | 6af0bf9c | bellard | #undef REG
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69 | 6af0bf9c | bellard | #define REG 7 |
70 | 6af0bf9c | bellard | #include "op_template.c" |
71 | 6af0bf9c | bellard | #undef REG
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72 | 6af0bf9c | bellard | #define REG 8 |
73 | 6af0bf9c | bellard | #include "op_template.c" |
74 | 6af0bf9c | bellard | #undef REG
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75 | 6af0bf9c | bellard | #define REG 9 |
76 | 6af0bf9c | bellard | #include "op_template.c" |
77 | 6af0bf9c | bellard | #undef REG
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78 | 6af0bf9c | bellard | #define REG 10 |
79 | 6af0bf9c | bellard | #include "op_template.c" |
80 | 6af0bf9c | bellard | #undef REG
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81 | 6af0bf9c | bellard | #define REG 11 |
82 | 6af0bf9c | bellard | #include "op_template.c" |
83 | 6af0bf9c | bellard | #undef REG
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84 | 6af0bf9c | bellard | #define REG 12 |
85 | 6af0bf9c | bellard | #include "op_template.c" |
86 | 6af0bf9c | bellard | #undef REG
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87 | 6af0bf9c | bellard | #define REG 13 |
88 | 6af0bf9c | bellard | #include "op_template.c" |
89 | 6af0bf9c | bellard | #undef REG
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90 | 6af0bf9c | bellard | #define REG 14 |
91 | 6af0bf9c | bellard | #include "op_template.c" |
92 | 6af0bf9c | bellard | #undef REG
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93 | 6af0bf9c | bellard | #define REG 15 |
94 | 6af0bf9c | bellard | #include "op_template.c" |
95 | 6af0bf9c | bellard | #undef REG
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96 | 6af0bf9c | bellard | #define REG 16 |
97 | 6af0bf9c | bellard | #include "op_template.c" |
98 | 6af0bf9c | bellard | #undef REG
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99 | 6af0bf9c | bellard | #define REG 17 |
100 | 6af0bf9c | bellard | #include "op_template.c" |
101 | 6af0bf9c | bellard | #undef REG
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102 | 6af0bf9c | bellard | #define REG 18 |
103 | 6af0bf9c | bellard | #include "op_template.c" |
104 | 6af0bf9c | bellard | #undef REG
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105 | 6af0bf9c | bellard | #define REG 19 |
106 | 6af0bf9c | bellard | #include "op_template.c" |
107 | 6af0bf9c | bellard | #undef REG
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108 | 6af0bf9c | bellard | #define REG 20 |
109 | 6af0bf9c | bellard | #include "op_template.c" |
110 | 6af0bf9c | bellard | #undef REG
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111 | 6af0bf9c | bellard | #define REG 21 |
112 | 6af0bf9c | bellard | #include "op_template.c" |
113 | 6af0bf9c | bellard | #undef REG
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114 | 6af0bf9c | bellard | #define REG 22 |
115 | 6af0bf9c | bellard | #include "op_template.c" |
116 | 6af0bf9c | bellard | #undef REG
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117 | 6af0bf9c | bellard | #define REG 23 |
118 | 6af0bf9c | bellard | #include "op_template.c" |
119 | 6af0bf9c | bellard | #undef REG
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120 | 6af0bf9c | bellard | #define REG 24 |
121 | 6af0bf9c | bellard | #include "op_template.c" |
122 | 6af0bf9c | bellard | #undef REG
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123 | 6af0bf9c | bellard | #define REG 25 |
124 | 6af0bf9c | bellard | #include "op_template.c" |
125 | 6af0bf9c | bellard | #undef REG
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126 | 6af0bf9c | bellard | #define REG 26 |
127 | 6af0bf9c | bellard | #include "op_template.c" |
128 | 6af0bf9c | bellard | #undef REG
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129 | 6af0bf9c | bellard | #define REG 27 |
130 | 6af0bf9c | bellard | #include "op_template.c" |
131 | 6af0bf9c | bellard | #undef REG
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132 | 6af0bf9c | bellard | #define REG 28 |
133 | 6af0bf9c | bellard | #include "op_template.c" |
134 | 6af0bf9c | bellard | #undef REG
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135 | 6af0bf9c | bellard | #define REG 29 |
136 | 6af0bf9c | bellard | #include "op_template.c" |
137 | 6af0bf9c | bellard | #undef REG
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138 | 6af0bf9c | bellard | #define REG 30 |
139 | 6af0bf9c | bellard | #include "op_template.c" |
140 | 6af0bf9c | bellard | #undef REG
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141 | 6af0bf9c | bellard | #define REG 31 |
142 | 6af0bf9c | bellard | #include "op_template.c" |
143 | 6af0bf9c | bellard | #undef REG
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144 | 6af0bf9c | bellard | |
145 | c570fd16 | ths | #define TN
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146 | 6af0bf9c | bellard | #include "op_template.c" |
147 | 6af0bf9c | bellard | #undef TN
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148 | 6af0bf9c | bellard | |
149 | 5a5012ec | ths | #define FREG 0 |
150 | 6ea83fed | bellard | #include "fop_template.c" |
151 | 5a5012ec | ths | #undef FREG
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152 | 5a5012ec | ths | #define FREG 1 |
153 | 6ea83fed | bellard | #include "fop_template.c" |
154 | 5a5012ec | ths | #undef FREG
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155 | 5a5012ec | ths | #define FREG 2 |
156 | 6ea83fed | bellard | #include "fop_template.c" |
157 | 5a5012ec | ths | #undef FREG
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158 | 5a5012ec | ths | #define FREG 3 |
159 | 6ea83fed | bellard | #include "fop_template.c" |
160 | 5a5012ec | ths | #undef FREG
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161 | 5a5012ec | ths | #define FREG 4 |
162 | 6ea83fed | bellard | #include "fop_template.c" |
163 | 5a5012ec | ths | #undef FREG
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164 | 5a5012ec | ths | #define FREG 5 |
165 | 6ea83fed | bellard | #include "fop_template.c" |
166 | 5a5012ec | ths | #undef FREG
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167 | 5a5012ec | ths | #define FREG 6 |
168 | 6ea83fed | bellard | #include "fop_template.c" |
169 | 5a5012ec | ths | #undef FREG
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170 | 5a5012ec | ths | #define FREG 7 |
171 | 6ea83fed | bellard | #include "fop_template.c" |
172 | 5a5012ec | ths | #undef FREG
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173 | 5a5012ec | ths | #define FREG 8 |
174 | 6ea83fed | bellard | #include "fop_template.c" |
175 | 5a5012ec | ths | #undef FREG
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176 | 5a5012ec | ths | #define FREG 9 |
177 | 6ea83fed | bellard | #include "fop_template.c" |
178 | 5a5012ec | ths | #undef FREG
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179 | 5a5012ec | ths | #define FREG 10 |
180 | 6ea83fed | bellard | #include "fop_template.c" |
181 | 5a5012ec | ths | #undef FREG
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182 | 5a5012ec | ths | #define FREG 11 |
183 | 6ea83fed | bellard | #include "fop_template.c" |
184 | 5a5012ec | ths | #undef FREG
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185 | 5a5012ec | ths | #define FREG 12 |
186 | 6ea83fed | bellard | #include "fop_template.c" |
187 | 5a5012ec | ths | #undef FREG
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188 | 5a5012ec | ths | #define FREG 13 |
189 | 6ea83fed | bellard | #include "fop_template.c" |
190 | 5a5012ec | ths | #undef FREG
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191 | 5a5012ec | ths | #define FREG 14 |
192 | 6ea83fed | bellard | #include "fop_template.c" |
193 | 5a5012ec | ths | #undef FREG
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194 | 5a5012ec | ths | #define FREG 15 |
195 | 6ea83fed | bellard | #include "fop_template.c" |
196 | 5a5012ec | ths | #undef FREG
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197 | 5a5012ec | ths | #define FREG 16 |
198 | 6ea83fed | bellard | #include "fop_template.c" |
199 | 5a5012ec | ths | #undef FREG
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200 | 5a5012ec | ths | #define FREG 17 |
201 | 6ea83fed | bellard | #include "fop_template.c" |
202 | 5a5012ec | ths | #undef FREG
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203 | 5a5012ec | ths | #define FREG 18 |
204 | 6ea83fed | bellard | #include "fop_template.c" |
205 | 5a5012ec | ths | #undef FREG
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206 | 5a5012ec | ths | #define FREG 19 |
207 | 6ea83fed | bellard | #include "fop_template.c" |
208 | 5a5012ec | ths | #undef FREG
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209 | 5a5012ec | ths | #define FREG 20 |
210 | 6ea83fed | bellard | #include "fop_template.c" |
211 | 5a5012ec | ths | #undef FREG
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212 | 5a5012ec | ths | #define FREG 21 |
213 | 6ea83fed | bellard | #include "fop_template.c" |
214 | 5a5012ec | ths | #undef FREG
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215 | 5a5012ec | ths | #define FREG 22 |
216 | 6ea83fed | bellard | #include "fop_template.c" |
217 | 5a5012ec | ths | #undef FREG
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218 | 5a5012ec | ths | #define FREG 23 |
219 | 6ea83fed | bellard | #include "fop_template.c" |
220 | 5a5012ec | ths | #undef FREG
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221 | 5a5012ec | ths | #define FREG 24 |
222 | 6ea83fed | bellard | #include "fop_template.c" |
223 | 5a5012ec | ths | #undef FREG
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224 | 5a5012ec | ths | #define FREG 25 |
225 | 6ea83fed | bellard | #include "fop_template.c" |
226 | 5a5012ec | ths | #undef FREG
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227 | 5a5012ec | ths | #define FREG 26 |
228 | 6ea83fed | bellard | #include "fop_template.c" |
229 | 5a5012ec | ths | #undef FREG
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230 | 5a5012ec | ths | #define FREG 27 |
231 | 6ea83fed | bellard | #include "fop_template.c" |
232 | 5a5012ec | ths | #undef FREG
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233 | 5a5012ec | ths | #define FREG 28 |
234 | 6ea83fed | bellard | #include "fop_template.c" |
235 | 5a5012ec | ths | #undef FREG
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236 | 5a5012ec | ths | #define FREG 29 |
237 | 6ea83fed | bellard | #include "fop_template.c" |
238 | 5a5012ec | ths | #undef FREG
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239 | 5a5012ec | ths | #define FREG 30 |
240 | 6ea83fed | bellard | #include "fop_template.c" |
241 | 5a5012ec | ths | #undef FREG
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242 | 5a5012ec | ths | #define FREG 31 |
243 | 6ea83fed | bellard | #include "fop_template.c" |
244 | 5a5012ec | ths | #undef FREG
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245 | 6ea83fed | bellard | |
246 | 6ea83fed | bellard | #define FTN
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247 | 6ea83fed | bellard | #include "fop_template.c" |
248 | 6ea83fed | bellard | #undef FTN
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249 | 6ea83fed | bellard | |
250 | 6af0bf9c | bellard | void op_dup_T0 (void) |
251 | 6af0bf9c | bellard | { |
252 | 6af0bf9c | bellard | T2 = T0; |
253 | 8f6f6026 | ths | FORCE_RET(); |
254 | 6af0bf9c | bellard | } |
255 | 6af0bf9c | bellard | |
256 | 6af0bf9c | bellard | void op_load_HI (void) |
257 | 6af0bf9c | bellard | { |
258 | ead9360e | ths | T0 = env->HI[PARAM1][env->current_tc]; |
259 | 8f6f6026 | ths | FORCE_RET(); |
260 | 6af0bf9c | bellard | } |
261 | 6af0bf9c | bellard | |
262 | 6af0bf9c | bellard | void op_store_HI (void) |
263 | 6af0bf9c | bellard | { |
264 | ead9360e | ths | env->HI[PARAM1][env->current_tc] = T0; |
265 | 8f6f6026 | ths | FORCE_RET(); |
266 | 6af0bf9c | bellard | } |
267 | 6af0bf9c | bellard | |
268 | 6af0bf9c | bellard | void op_load_LO (void) |
269 | 6af0bf9c | bellard | { |
270 | ead9360e | ths | T0 = env->LO[PARAM1][env->current_tc]; |
271 | 8f6f6026 | ths | FORCE_RET(); |
272 | 6af0bf9c | bellard | } |
273 | 6af0bf9c | bellard | |
274 | 6af0bf9c | bellard | void op_store_LO (void) |
275 | 6af0bf9c | bellard | { |
276 | ead9360e | ths | env->LO[PARAM1][env->current_tc] = T0; |
277 | 8f6f6026 | ths | FORCE_RET(); |
278 | 6af0bf9c | bellard | } |
279 | 6af0bf9c | bellard | |
280 | 6af0bf9c | bellard | /* Load and store */
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281 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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282 | 6af0bf9c | bellard | #include "op_mem.c" |
283 | 6af0bf9c | bellard | #undef MEMSUFFIX
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284 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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285 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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286 | 6af0bf9c | bellard | #include "op_mem.c" |
287 | 6af0bf9c | bellard | #undef MEMSUFFIX
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288 | 6af0bf9c | bellard | |
289 | 623a930e | ths | #define MEMSUFFIX _super
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290 | 623a930e | ths | #include "op_mem.c" |
291 | 623a930e | ths | #undef MEMSUFFIX
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292 | 623a930e | ths | |
293 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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294 | 6af0bf9c | bellard | #include "op_mem.c" |
295 | 6af0bf9c | bellard | #undef MEMSUFFIX
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296 | 6af0bf9c | bellard | #endif
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297 | 6af0bf9c | bellard | |
298 | a6763a58 | ths | /* Addresses computation */
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299 | a6763a58 | ths | void op_addr_add (void) |
300 | a6763a58 | ths | { |
301 | a6763a58 | ths | /* For compatibility with 32-bit code, data reference in user mode
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302 | a6763a58 | ths | with Status_UX = 0 should be casted to 32-bit and sign extended.
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303 | a6763a58 | ths | See the MIPS64 PRA manual, section 4.10. */
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304 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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305 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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306 | a6763a58 | ths | !(env->CP0_Status & (1 << CP0St_UX)))
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307 | a6763a58 | ths | T0 = (int64_t)(int32_t)(T0 + T1); |
308 | a6763a58 | ths | else
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309 | a6763a58 | ths | #endif
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310 | a6763a58 | ths | T0 += T1; |
311 | 8f6f6026 | ths | FORCE_RET(); |
312 | a6763a58 | ths | } |
313 | a6763a58 | ths | |
314 | 6af0bf9c | bellard | /* Arithmetic */
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315 | 6af0bf9c | bellard | void op_add (void) |
316 | 6af0bf9c | bellard | { |
317 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
318 | 8f6f6026 | ths | FORCE_RET(); |
319 | 6af0bf9c | bellard | } |
320 | 6af0bf9c | bellard | |
321 | 6af0bf9c | bellard | void op_addo (void) |
322 | 6af0bf9c | bellard | { |
323 | 6af0bf9c | bellard | target_ulong tmp; |
324 | 6af0bf9c | bellard | |
325 | c570fd16 | ths | tmp = (int32_t)T0; |
326 | c570fd16 | ths | T0 = (int32_t)T0 + (int32_t)T1; |
327 | 76e050c2 | bellard | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
328 | c570fd16 | ths | /* operands of same sign, result different sign */
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329 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
330 | 6af0bf9c | bellard | } |
331 | 5dc4b744 | ths | T0 = (int32_t)T0; |
332 | 8f6f6026 | ths | FORCE_RET(); |
333 | 6af0bf9c | bellard | } |
334 | 6af0bf9c | bellard | |
335 | 6af0bf9c | bellard | void op_sub (void) |
336 | 6af0bf9c | bellard | { |
337 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
338 | 8f6f6026 | ths | FORCE_RET(); |
339 | 6af0bf9c | bellard | } |
340 | 6af0bf9c | bellard | |
341 | 6af0bf9c | bellard | void op_subo (void) |
342 | 6af0bf9c | bellard | { |
343 | 6af0bf9c | bellard | target_ulong tmp; |
344 | 6af0bf9c | bellard | |
345 | c570fd16 | ths | tmp = (int32_t)T0; |
346 | 6af0bf9c | bellard | T0 = (int32_t)T0 - (int32_t)T1; |
347 | 76e050c2 | bellard | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
348 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
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349 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
350 | 6af0bf9c | bellard | } |
351 | 5dc4b744 | ths | T0 = (int32_t)T0; |
352 | 8f6f6026 | ths | FORCE_RET(); |
353 | 6af0bf9c | bellard | } |
354 | 6af0bf9c | bellard | |
355 | 6af0bf9c | bellard | void op_mul (void) |
356 | 6af0bf9c | bellard | { |
357 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
358 | 8f6f6026 | ths | FORCE_RET(); |
359 | 6af0bf9c | bellard | } |
360 | 6af0bf9c | bellard | |
361 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
362 | 80c27194 | ths | void op_div (void) |
363 | 80c27194 | ths | { |
364 | 80c27194 | ths | CALL_FROM_TB0(do_div); |
365 | 8f6f6026 | ths | FORCE_RET(); |
366 | 80c27194 | ths | } |
367 | 80c27194 | ths | #else
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368 | 6af0bf9c | bellard | void op_div (void) |
369 | 6af0bf9c | bellard | { |
370 | 6af0bf9c | bellard | if (T1 != 0) { |
371 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
|
372 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
|
373 | 6af0bf9c | bellard | } |
374 | 8f6f6026 | ths | FORCE_RET(); |
375 | 6af0bf9c | bellard | } |
376 | 80c27194 | ths | #endif
|
377 | 6af0bf9c | bellard | |
378 | 6af0bf9c | bellard | void op_divu (void) |
379 | 6af0bf9c | bellard | { |
380 | 6af0bf9c | bellard | if (T1 != 0) { |
381 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
|
382 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
|
383 | c570fd16 | ths | } |
384 | 8f6f6026 | ths | FORCE_RET(); |
385 | c570fd16 | ths | } |
386 | c570fd16 | ths | |
387 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
388 | c570fd16 | ths | /* Arithmetic */
|
389 | c570fd16 | ths | void op_dadd (void) |
390 | c570fd16 | ths | { |
391 | c570fd16 | ths | T0 += T1; |
392 | 8f6f6026 | ths | FORCE_RET(); |
393 | c570fd16 | ths | } |
394 | c570fd16 | ths | |
395 | c570fd16 | ths | void op_daddo (void) |
396 | c570fd16 | ths | { |
397 | c570fd16 | ths | target_long tmp; |
398 | c570fd16 | ths | |
399 | c570fd16 | ths | tmp = T0; |
400 | c570fd16 | ths | T0 += T1; |
401 | c570fd16 | ths | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { |
402 | c570fd16 | ths | /* operands of same sign, result different sign */
|
403 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
404 | c570fd16 | ths | } |
405 | 8f6f6026 | ths | FORCE_RET(); |
406 | c570fd16 | ths | } |
407 | c570fd16 | ths | |
408 | c570fd16 | ths | void op_dsub (void) |
409 | c570fd16 | ths | { |
410 | c570fd16 | ths | T0 -= T1; |
411 | 8f6f6026 | ths | FORCE_RET(); |
412 | c570fd16 | ths | } |
413 | c570fd16 | ths | |
414 | c570fd16 | ths | void op_dsubo (void) |
415 | c570fd16 | ths | { |
416 | c570fd16 | ths | target_long tmp; |
417 | c570fd16 | ths | |
418 | c570fd16 | ths | tmp = T0; |
419 | c570fd16 | ths | T0 = (int64_t)T0 - (int64_t)T1; |
420 | c570fd16 | ths | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { |
421 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
|
422 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
423 | c570fd16 | ths | } |
424 | 8f6f6026 | ths | FORCE_RET(); |
425 | c570fd16 | ths | } |
426 | c570fd16 | ths | |
427 | c570fd16 | ths | void op_dmul (void) |
428 | c570fd16 | ths | { |
429 | c570fd16 | ths | T0 = (int64_t)T0 * (int64_t)T1; |
430 | 8f6f6026 | ths | FORCE_RET(); |
431 | c570fd16 | ths | } |
432 | c570fd16 | ths | |
433 | c570fd16 | ths | /* Those might call libgcc functions. */
|
434 | c570fd16 | ths | void op_ddiv (void) |
435 | c570fd16 | ths | { |
436 | c570fd16 | ths | do_ddiv(); |
437 | 8f6f6026 | ths | FORCE_RET(); |
438 | c570fd16 | ths | } |
439 | c570fd16 | ths | |
440 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
441 | c570fd16 | ths | void op_ddivu (void) |
442 | c570fd16 | ths | { |
443 | c570fd16 | ths | do_ddivu(); |
444 | 8f6f6026 | ths | FORCE_RET(); |
445 | c570fd16 | ths | } |
446 | c570fd16 | ths | #else
|
447 | c570fd16 | ths | void op_ddivu (void) |
448 | c570fd16 | ths | { |
449 | c570fd16 | ths | if (T1 != 0) { |
450 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
|
451 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
|
452 | 6af0bf9c | bellard | } |
453 | 8f6f6026 | ths | FORCE_RET(); |
454 | 6af0bf9c | bellard | } |
455 | c570fd16 | ths | #endif
|
456 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
457 | 6af0bf9c | bellard | |
458 | 6af0bf9c | bellard | /* Logical */
|
459 | 6af0bf9c | bellard | void op_and (void) |
460 | 6af0bf9c | bellard | { |
461 | 6af0bf9c | bellard | T0 &= T1; |
462 | 8f6f6026 | ths | FORCE_RET(); |
463 | 6af0bf9c | bellard | } |
464 | 6af0bf9c | bellard | |
465 | 6af0bf9c | bellard | void op_nor (void) |
466 | 6af0bf9c | bellard | { |
467 | 6af0bf9c | bellard | T0 = ~(T0 | T1); |
468 | 8f6f6026 | ths | FORCE_RET(); |
469 | 6af0bf9c | bellard | } |
470 | 6af0bf9c | bellard | |
471 | 6af0bf9c | bellard | void op_or (void) |
472 | 6af0bf9c | bellard | { |
473 | 6af0bf9c | bellard | T0 |= T1; |
474 | 8f6f6026 | ths | FORCE_RET(); |
475 | 6af0bf9c | bellard | } |
476 | 6af0bf9c | bellard | |
477 | 6af0bf9c | bellard | void op_xor (void) |
478 | 6af0bf9c | bellard | { |
479 | 6af0bf9c | bellard | T0 ^= T1; |
480 | 8f6f6026 | ths | FORCE_RET(); |
481 | 6af0bf9c | bellard | } |
482 | 6af0bf9c | bellard | |
483 | 6af0bf9c | bellard | void op_sll (void) |
484 | 6af0bf9c | bellard | { |
485 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 << T1); |
486 | 8f6f6026 | ths | FORCE_RET(); |
487 | 6af0bf9c | bellard | } |
488 | 6af0bf9c | bellard | |
489 | 6af0bf9c | bellard | void op_sra (void) |
490 | 6af0bf9c | bellard | { |
491 | 5a63bcb2 | ths | T0 = (int32_t)((int32_t)T0 >> T1); |
492 | 8f6f6026 | ths | FORCE_RET(); |
493 | 6af0bf9c | bellard | } |
494 | 6af0bf9c | bellard | |
495 | 6af0bf9c | bellard | void op_srl (void) |
496 | 6af0bf9c | bellard | { |
497 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1); |
498 | 8f6f6026 | ths | FORCE_RET(); |
499 | 6af0bf9c | bellard | } |
500 | 6af0bf9c | bellard | |
501 | 7a387fff | ths | void op_rotr (void) |
502 | 7a387fff | ths | { |
503 | 7a387fff | ths | target_ulong tmp; |
504 | 7a387fff | ths | |
505 | 7a387fff | ths | if (T1) {
|
506 | 5a63bcb2 | ths | tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
|
507 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; |
508 | 5a63bcb2 | ths | } |
509 | 8f6f6026 | ths | FORCE_RET(); |
510 | 7a387fff | ths | } |
511 | 7a387fff | ths | |
512 | 6af0bf9c | bellard | void op_sllv (void) |
513 | 6af0bf9c | bellard | { |
514 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
515 | 8f6f6026 | ths | FORCE_RET(); |
516 | 6af0bf9c | bellard | } |
517 | 6af0bf9c | bellard | |
518 | 6af0bf9c | bellard | void op_srav (void) |
519 | 6af0bf9c | bellard | { |
520 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
521 | 8f6f6026 | ths | FORCE_RET(); |
522 | 6af0bf9c | bellard | } |
523 | 6af0bf9c | bellard | |
524 | 6af0bf9c | bellard | void op_srlv (void) |
525 | 6af0bf9c | bellard | { |
526 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
527 | 8f6f6026 | ths | FORCE_RET(); |
528 | 6af0bf9c | bellard | } |
529 | 6af0bf9c | bellard | |
530 | 7a387fff | ths | void op_rotrv (void) |
531 | 7a387fff | ths | { |
532 | 7a387fff | ths | target_ulong tmp; |
533 | 7a387fff | ths | |
534 | 7a387fff | ths | T0 &= 0x1F;
|
535 | 7a387fff | ths | if (T0) {
|
536 | 5dc4b744 | ths | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
537 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; |
538 | 7a387fff | ths | } else
|
539 | 7a387fff | ths | T0 = T1; |
540 | 8f6f6026 | ths | FORCE_RET(); |
541 | 7a387fff | ths | } |
542 | 7a387fff | ths | |
543 | 6af0bf9c | bellard | void op_clo (void) |
544 | 6af0bf9c | bellard | { |
545 | 05f778c8 | ths | T0 = clo32(T0); |
546 | 8f6f6026 | ths | FORCE_RET(); |
547 | 6af0bf9c | bellard | } |
548 | 6af0bf9c | bellard | |
549 | 6af0bf9c | bellard | void op_clz (void) |
550 | 6af0bf9c | bellard | { |
551 | 05f778c8 | ths | T0 = clz32(T0); |
552 | 8f6f6026 | ths | FORCE_RET(); |
553 | 6af0bf9c | bellard | } |
554 | 6af0bf9c | bellard | |
555 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
556 | c570fd16 | ths | |
557 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
558 | c570fd16 | ths | /* Those might call libgcc functions. */
|
559 | c570fd16 | ths | void op_dsll (void) |
560 | 6af0bf9c | bellard | { |
561 | c570fd16 | ths | CALL_FROM_TB0(do_dsll); |
562 | 8f6f6026 | ths | FORCE_RET(); |
563 | 6af0bf9c | bellard | } |
564 | 6af0bf9c | bellard | |
565 | c570fd16 | ths | void op_dsll32 (void) |
566 | 6af0bf9c | bellard | { |
567 | c570fd16 | ths | CALL_FROM_TB0(do_dsll32); |
568 | 8f6f6026 | ths | FORCE_RET(); |
569 | 6af0bf9c | bellard | } |
570 | 6af0bf9c | bellard | |
571 | c570fd16 | ths | void op_dsra (void) |
572 | 6af0bf9c | bellard | { |
573 | c570fd16 | ths | CALL_FROM_TB0(do_dsra); |
574 | 8f6f6026 | ths | FORCE_RET(); |
575 | 6af0bf9c | bellard | } |
576 | 6af0bf9c | bellard | |
577 | c570fd16 | ths | void op_dsra32 (void) |
578 | 6af0bf9c | bellard | { |
579 | c570fd16 | ths | CALL_FROM_TB0(do_dsra32); |
580 | 8f6f6026 | ths | FORCE_RET(); |
581 | 6af0bf9c | bellard | } |
582 | 6af0bf9c | bellard | |
583 | c570fd16 | ths | void op_dsrl (void) |
584 | 6af0bf9c | bellard | { |
585 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl); |
586 | 8f6f6026 | ths | FORCE_RET(); |
587 | c570fd16 | ths | } |
588 | 6af0bf9c | bellard | |
589 | c570fd16 | ths | void op_dsrl32 (void) |
590 | c570fd16 | ths | { |
591 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl32); |
592 | 8f6f6026 | ths | FORCE_RET(); |
593 | 6af0bf9c | bellard | } |
594 | 6af0bf9c | bellard | |
595 | c570fd16 | ths | void op_drotr (void) |
596 | 6af0bf9c | bellard | { |
597 | c570fd16 | ths | CALL_FROM_TB0(do_drotr); |
598 | 8f6f6026 | ths | FORCE_RET(); |
599 | c570fd16 | ths | } |
600 | 6af0bf9c | bellard | |
601 | c570fd16 | ths | void op_drotr32 (void) |
602 | c570fd16 | ths | { |
603 | c570fd16 | ths | CALL_FROM_TB0(do_drotr32); |
604 | 8f6f6026 | ths | FORCE_RET(); |
605 | 6af0bf9c | bellard | } |
606 | 6af0bf9c | bellard | |
607 | c570fd16 | ths | void op_dsllv (void) |
608 | 6af0bf9c | bellard | { |
609 | c570fd16 | ths | CALL_FROM_TB0(do_dsllv); |
610 | 8f6f6026 | ths | FORCE_RET(); |
611 | c570fd16 | ths | } |
612 | 6af0bf9c | bellard | |
613 | c570fd16 | ths | void op_dsrav (void) |
614 | c570fd16 | ths | { |
615 | c570fd16 | ths | CALL_FROM_TB0(do_dsrav); |
616 | 8f6f6026 | ths | FORCE_RET(); |
617 | 6af0bf9c | bellard | } |
618 | 6af0bf9c | bellard | |
619 | c570fd16 | ths | void op_dsrlv (void) |
620 | 6af0bf9c | bellard | { |
621 | c570fd16 | ths | CALL_FROM_TB0(do_dsrlv); |
622 | 8f6f6026 | ths | FORCE_RET(); |
623 | c570fd16 | ths | } |
624 | 6af0bf9c | bellard | |
625 | c570fd16 | ths | void op_drotrv (void) |
626 | c570fd16 | ths | { |
627 | c570fd16 | ths | CALL_FROM_TB0(do_drotrv); |
628 | 8f6f6026 | ths | FORCE_RET(); |
629 | 6af0bf9c | bellard | } |
630 | c570fd16 | ths | |
631 | 05f778c8 | ths | void op_dclo (void) |
632 | 05f778c8 | ths | { |
633 | 05f778c8 | ths | CALL_FROM_TB0(do_dclo); |
634 | 8f6f6026 | ths | FORCE_RET(); |
635 | 05f778c8 | ths | } |
636 | 05f778c8 | ths | |
637 | 05f778c8 | ths | void op_dclz (void) |
638 | 05f778c8 | ths | { |
639 | 05f778c8 | ths | CALL_FROM_TB0(do_dclz); |
640 | 8f6f6026 | ths | FORCE_RET(); |
641 | 05f778c8 | ths | } |
642 | 05f778c8 | ths | |
643 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
644 | c570fd16 | ths | |
645 | c570fd16 | ths | void op_dsll (void) |
646 | c570fd16 | ths | { |
647 | c570fd16 | ths | T0 = T0 << T1; |
648 | 8f6f6026 | ths | FORCE_RET(); |
649 | c570fd16 | ths | } |
650 | c570fd16 | ths | |
651 | c570fd16 | ths | void op_dsll32 (void) |
652 | c570fd16 | ths | { |
653 | c570fd16 | ths | T0 = T0 << (T1 + 32);
|
654 | 8f6f6026 | ths | FORCE_RET(); |
655 | c570fd16 | ths | } |
656 | c570fd16 | ths | |
657 | c570fd16 | ths | void op_dsra (void) |
658 | c570fd16 | ths | { |
659 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
660 | 8f6f6026 | ths | FORCE_RET(); |
661 | c570fd16 | ths | } |
662 | c570fd16 | ths | |
663 | c570fd16 | ths | void op_dsra32 (void) |
664 | c570fd16 | ths | { |
665 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
|
666 | 8f6f6026 | ths | FORCE_RET(); |
667 | c570fd16 | ths | } |
668 | c570fd16 | ths | |
669 | c570fd16 | ths | void op_dsrl (void) |
670 | c570fd16 | ths | { |
671 | c570fd16 | ths | T0 = T0 >> T1; |
672 | 8f6f6026 | ths | FORCE_RET(); |
673 | c570fd16 | ths | } |
674 | c570fd16 | ths | |
675 | c570fd16 | ths | void op_dsrl32 (void) |
676 | c570fd16 | ths | { |
677 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
|
678 | 8f6f6026 | ths | FORCE_RET(); |
679 | c570fd16 | ths | } |
680 | c570fd16 | ths | |
681 | c570fd16 | ths | void op_drotr (void) |
682 | c570fd16 | ths | { |
683 | c570fd16 | ths | target_ulong tmp; |
684 | c570fd16 | ths | |
685 | c570fd16 | ths | if (T1) {
|
686 | c6d6dd7c | ths | tmp = T0 << (0x40 - T1);
|
687 | c6d6dd7c | ths | T0 = (T0 >> T1) | tmp; |
688 | 5a63bcb2 | ths | } |
689 | 8f6f6026 | ths | FORCE_RET(); |
690 | c570fd16 | ths | } |
691 | c570fd16 | ths | |
692 | c570fd16 | ths | void op_drotr32 (void) |
693 | c570fd16 | ths | { |
694 | c570fd16 | ths | target_ulong tmp; |
695 | c570fd16 | ths | |
696 | c6d6dd7c | ths | tmp = T0 << (0x40 - (32 + T1)); |
697 | c6d6dd7c | ths | T0 = (T0 >> (32 + T1)) | tmp;
|
698 | 8f6f6026 | ths | FORCE_RET(); |
699 | c570fd16 | ths | } |
700 | c570fd16 | ths | |
701 | c570fd16 | ths | void op_dsllv (void) |
702 | c570fd16 | ths | { |
703 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
|
704 | 8f6f6026 | ths | FORCE_RET(); |
705 | c570fd16 | ths | } |
706 | c570fd16 | ths | |
707 | c570fd16 | ths | void op_dsrav (void) |
708 | c570fd16 | ths | { |
709 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
|
710 | 8f6f6026 | ths | FORCE_RET(); |
711 | c570fd16 | ths | } |
712 | c570fd16 | ths | |
713 | c570fd16 | ths | void op_dsrlv (void) |
714 | c570fd16 | ths | { |
715 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
|
716 | 8f6f6026 | ths | FORCE_RET(); |
717 | c570fd16 | ths | } |
718 | c570fd16 | ths | |
719 | c570fd16 | ths | void op_drotrv (void) |
720 | c570fd16 | ths | { |
721 | c570fd16 | ths | target_ulong tmp; |
722 | c570fd16 | ths | |
723 | c570fd16 | ths | T0 &= 0x3F;
|
724 | c570fd16 | ths | if (T0) {
|
725 | c6d6dd7c | ths | tmp = T1 << (0x40 - T0);
|
726 | c6d6dd7c | ths | T0 = (T1 >> T0) | tmp; |
727 | c570fd16 | ths | } else
|
728 | c6d6dd7c | ths | T0 = T1; |
729 | 8f6f6026 | ths | FORCE_RET(); |
730 | c570fd16 | ths | } |
731 | c570fd16 | ths | |
732 | c570fd16 | ths | void op_dclo (void) |
733 | c570fd16 | ths | { |
734 | 05f778c8 | ths | T0 = clo64(T0); |
735 | 8f6f6026 | ths | FORCE_RET(); |
736 | c570fd16 | ths | } |
737 | c570fd16 | ths | |
738 | c570fd16 | ths | void op_dclz (void) |
739 | c570fd16 | ths | { |
740 | 05f778c8 | ths | T0 = clz64(T0); |
741 | 8f6f6026 | ths | FORCE_RET(); |
742 | c570fd16 | ths | } |
743 | 05f778c8 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
744 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
745 | c570fd16 | ths | |
746 | c570fd16 | ths | /* 64 bits arithmetic */
|
747 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
748 | 6af0bf9c | bellard | void op_mult (void) |
749 | 6af0bf9c | bellard | { |
750 | 6af0bf9c | bellard | CALL_FROM_TB0(do_mult); |
751 | 8f6f6026 | ths | FORCE_RET(); |
752 | 6af0bf9c | bellard | } |
753 | 6af0bf9c | bellard | |
754 | 6af0bf9c | bellard | void op_multu (void) |
755 | 6af0bf9c | bellard | { |
756 | 6af0bf9c | bellard | CALL_FROM_TB0(do_multu); |
757 | 8f6f6026 | ths | FORCE_RET(); |
758 | 6af0bf9c | bellard | } |
759 | 6af0bf9c | bellard | |
760 | 6af0bf9c | bellard | void op_madd (void) |
761 | 6af0bf9c | bellard | { |
762 | 6af0bf9c | bellard | CALL_FROM_TB0(do_madd); |
763 | 8f6f6026 | ths | FORCE_RET(); |
764 | 6af0bf9c | bellard | } |
765 | 6af0bf9c | bellard | |
766 | 6af0bf9c | bellard | void op_maddu (void) |
767 | 6af0bf9c | bellard | { |
768 | 6af0bf9c | bellard | CALL_FROM_TB0(do_maddu); |
769 | 8f6f6026 | ths | FORCE_RET(); |
770 | 6af0bf9c | bellard | } |
771 | 6af0bf9c | bellard | |
772 | 6af0bf9c | bellard | void op_msub (void) |
773 | 6af0bf9c | bellard | { |
774 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msub); |
775 | 8f6f6026 | ths | FORCE_RET(); |
776 | 6af0bf9c | bellard | } |
777 | 6af0bf9c | bellard | |
778 | 6af0bf9c | bellard | void op_msubu (void) |
779 | 6af0bf9c | bellard | { |
780 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msubu); |
781 | 8f6f6026 | ths | FORCE_RET(); |
782 | 6af0bf9c | bellard | } |
783 | c570fd16 | ths | |
784 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
|
785 | e9c71dd1 | ths | void op_muls (void) |
786 | e9c71dd1 | ths | { |
787 | e9c71dd1 | ths | CALL_FROM_TB0(do_muls); |
788 | e9c71dd1 | ths | FORCE_RET(); |
789 | e9c71dd1 | ths | } |
790 | e9c71dd1 | ths | |
791 | e9c71dd1 | ths | void op_mulsu (void) |
792 | e9c71dd1 | ths | { |
793 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulsu); |
794 | e9c71dd1 | ths | FORCE_RET(); |
795 | e9c71dd1 | ths | } |
796 | e9c71dd1 | ths | |
797 | e9c71dd1 | ths | void op_macc (void) |
798 | e9c71dd1 | ths | { |
799 | e9c71dd1 | ths | CALL_FROM_TB0(do_macc); |
800 | e9c71dd1 | ths | FORCE_RET(); |
801 | e9c71dd1 | ths | } |
802 | e9c71dd1 | ths | |
803 | e9c71dd1 | ths | void op_macchi (void) |
804 | e9c71dd1 | ths | { |
805 | e9c71dd1 | ths | CALL_FROM_TB0(do_macchi); |
806 | e9c71dd1 | ths | FORCE_RET(); |
807 | e9c71dd1 | ths | } |
808 | e9c71dd1 | ths | |
809 | e9c71dd1 | ths | void op_maccu (void) |
810 | e9c71dd1 | ths | { |
811 | e9c71dd1 | ths | CALL_FROM_TB0(do_maccu); |
812 | e9c71dd1 | ths | FORCE_RET(); |
813 | e9c71dd1 | ths | } |
814 | e9c71dd1 | ths | void op_macchiu (void) |
815 | e9c71dd1 | ths | { |
816 | e9c71dd1 | ths | CALL_FROM_TB0(do_macchiu); |
817 | e9c71dd1 | ths | FORCE_RET(); |
818 | e9c71dd1 | ths | } |
819 | e9c71dd1 | ths | |
820 | e9c71dd1 | ths | void op_msac (void) |
821 | e9c71dd1 | ths | { |
822 | e9c71dd1 | ths | CALL_FROM_TB0(do_msac); |
823 | e9c71dd1 | ths | FORCE_RET(); |
824 | e9c71dd1 | ths | } |
825 | e9c71dd1 | ths | |
826 | e9c71dd1 | ths | void op_msachi (void) |
827 | e9c71dd1 | ths | { |
828 | e9c71dd1 | ths | CALL_FROM_TB0(do_msachi); |
829 | e9c71dd1 | ths | FORCE_RET(); |
830 | e9c71dd1 | ths | } |
831 | e9c71dd1 | ths | |
832 | e9c71dd1 | ths | void op_msacu (void) |
833 | e9c71dd1 | ths | { |
834 | e9c71dd1 | ths | CALL_FROM_TB0(do_msacu); |
835 | e9c71dd1 | ths | FORCE_RET(); |
836 | e9c71dd1 | ths | } |
837 | e9c71dd1 | ths | |
838 | e9c71dd1 | ths | void op_msachiu (void) |
839 | e9c71dd1 | ths | { |
840 | e9c71dd1 | ths | CALL_FROM_TB0(do_msachiu); |
841 | e9c71dd1 | ths | FORCE_RET(); |
842 | e9c71dd1 | ths | } |
843 | e9c71dd1 | ths | |
844 | e9c71dd1 | ths | void op_mulhi (void) |
845 | e9c71dd1 | ths | { |
846 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulhi); |
847 | e9c71dd1 | ths | FORCE_RET(); |
848 | e9c71dd1 | ths | } |
849 | e9c71dd1 | ths | |
850 | e9c71dd1 | ths | void op_mulhiu (void) |
851 | e9c71dd1 | ths | { |
852 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulhiu); |
853 | e9c71dd1 | ths | FORCE_RET(); |
854 | e9c71dd1 | ths | } |
855 | e9c71dd1 | ths | |
856 | e9c71dd1 | ths | void op_mulshi (void) |
857 | e9c71dd1 | ths | { |
858 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulshi); |
859 | e9c71dd1 | ths | FORCE_RET(); |
860 | e9c71dd1 | ths | } |
861 | e9c71dd1 | ths | |
862 | e9c71dd1 | ths | void op_mulshiu (void) |
863 | e9c71dd1 | ths | { |
864 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulshiu); |
865 | e9c71dd1 | ths | FORCE_RET(); |
866 | e9c71dd1 | ths | } |
867 | e9c71dd1 | ths | |
868 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
869 | c570fd16 | ths | |
870 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
871 | c570fd16 | ths | { |
872 | ead9360e | ths | return ((uint64_t)env->HI[0][env->current_tc] << 32) | |
873 | ead9360e | ths | ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
|
874 | c570fd16 | ths | } |
875 | c570fd16 | ths | |
876 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
877 | c570fd16 | ths | { |
878 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
879 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
880 | c570fd16 | ths | } |
881 | c570fd16 | ths | |
882 | e9c71dd1 | ths | static always_inline void set_HIT0_LO (uint64_t HILO) |
883 | e9c71dd1 | ths | { |
884 | e9c71dd1 | ths | env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
885 | e9c71dd1 | ths | T0 = env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
886 | e9c71dd1 | ths | } |
887 | e9c71dd1 | ths | |
888 | e9c71dd1 | ths | static always_inline void set_HI_LOT0 (uint64_t HILO) |
889 | e9c71dd1 | ths | { |
890 | e9c71dd1 | ths | T0 = env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
891 | e9c71dd1 | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
892 | e9c71dd1 | ths | } |
893 | e9c71dd1 | ths | |
894 | c570fd16 | ths | void op_mult (void) |
895 | c570fd16 | ths | { |
896 | c570fd16 | ths | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
897 | 8f6f6026 | ths | FORCE_RET(); |
898 | c570fd16 | ths | } |
899 | c570fd16 | ths | |
900 | c570fd16 | ths | void op_multu (void) |
901 | c570fd16 | ths | { |
902 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
903 | 8f6f6026 | ths | FORCE_RET(); |
904 | c570fd16 | ths | } |
905 | c570fd16 | ths | |
906 | c570fd16 | ths | void op_madd (void) |
907 | c570fd16 | ths | { |
908 | c570fd16 | ths | int64_t tmp; |
909 | c570fd16 | ths | |
910 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
911 | c570fd16 | ths | set_HILO((int64_t)get_HILO() + tmp); |
912 | 8f6f6026 | ths | FORCE_RET(); |
913 | c570fd16 | ths | } |
914 | c570fd16 | ths | |
915 | c570fd16 | ths | void op_maddu (void) |
916 | c570fd16 | ths | { |
917 | c570fd16 | ths | uint64_t tmp; |
918 | c570fd16 | ths | |
919 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
920 | c570fd16 | ths | set_HILO(get_HILO() + tmp); |
921 | 8f6f6026 | ths | FORCE_RET(); |
922 | c570fd16 | ths | } |
923 | c570fd16 | ths | |
924 | c570fd16 | ths | void op_msub (void) |
925 | c570fd16 | ths | { |
926 | c570fd16 | ths | int64_t tmp; |
927 | c570fd16 | ths | |
928 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
929 | c570fd16 | ths | set_HILO((int64_t)get_HILO() - tmp); |
930 | 8f6f6026 | ths | FORCE_RET(); |
931 | c570fd16 | ths | } |
932 | c570fd16 | ths | |
933 | c570fd16 | ths | void op_msubu (void) |
934 | c570fd16 | ths | { |
935 | c570fd16 | ths | uint64_t tmp; |
936 | c570fd16 | ths | |
937 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
938 | c570fd16 | ths | set_HILO(get_HILO() - tmp); |
939 | 8f6f6026 | ths | FORCE_RET(); |
940 | c570fd16 | ths | } |
941 | e9c71dd1 | ths | |
942 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
|
943 | e9c71dd1 | ths | void op_muls (void) |
944 | e9c71dd1 | ths | { |
945 | e9c71dd1 | ths | set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
946 | e9c71dd1 | ths | FORCE_RET(); |
947 | e9c71dd1 | ths | } |
948 | e9c71dd1 | ths | |
949 | e9c71dd1 | ths | void op_mulsu (void) |
950 | e9c71dd1 | ths | { |
951 | e9c71dd1 | ths | set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
952 | e9c71dd1 | ths | FORCE_RET(); |
953 | e9c71dd1 | ths | } |
954 | e9c71dd1 | ths | |
955 | e9c71dd1 | ths | void op_macc (void) |
956 | e9c71dd1 | ths | { |
957 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
958 | e9c71dd1 | ths | FORCE_RET(); |
959 | e9c71dd1 | ths | } |
960 | e9c71dd1 | ths | |
961 | e9c71dd1 | ths | void op_macchi (void) |
962 | e9c71dd1 | ths | { |
963 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
964 | e9c71dd1 | ths | FORCE_RET(); |
965 | e9c71dd1 | ths | } |
966 | e9c71dd1 | ths | |
967 | e9c71dd1 | ths | void op_maccu (void) |
968 | e9c71dd1 | ths | { |
969 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
970 | e9c71dd1 | ths | FORCE_RET(); |
971 | e9c71dd1 | ths | } |
972 | e9c71dd1 | ths | |
973 | e9c71dd1 | ths | void op_macchiu (void) |
974 | e9c71dd1 | ths | { |
975 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
976 | e9c71dd1 | ths | FORCE_RET(); |
977 | e9c71dd1 | ths | } |
978 | e9c71dd1 | ths | |
979 | e9c71dd1 | ths | void op_msac (void) |
980 | e9c71dd1 | ths | { |
981 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
982 | e9c71dd1 | ths | FORCE_RET(); |
983 | e9c71dd1 | ths | } |
984 | e9c71dd1 | ths | |
985 | e9c71dd1 | ths | void op_msachi (void) |
986 | e9c71dd1 | ths | { |
987 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
988 | e9c71dd1 | ths | FORCE_RET(); |
989 | e9c71dd1 | ths | } |
990 | e9c71dd1 | ths | |
991 | e9c71dd1 | ths | void op_msacu (void) |
992 | e9c71dd1 | ths | { |
993 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
994 | e9c71dd1 | ths | FORCE_RET(); |
995 | e9c71dd1 | ths | } |
996 | e9c71dd1 | ths | |
997 | e9c71dd1 | ths | void op_msachiu (void) |
998 | e9c71dd1 | ths | { |
999 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
1000 | e9c71dd1 | ths | FORCE_RET(); |
1001 | e9c71dd1 | ths | } |
1002 | e9c71dd1 | ths | |
1003 | e9c71dd1 | ths | void op_mulhi (void) |
1004 | e9c71dd1 | ths | { |
1005 | e9c71dd1 | ths | set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
1006 | e9c71dd1 | ths | FORCE_RET(); |
1007 | e9c71dd1 | ths | } |
1008 | e9c71dd1 | ths | |
1009 | e9c71dd1 | ths | void op_mulhiu (void) |
1010 | e9c71dd1 | ths | { |
1011 | e9c71dd1 | ths | set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
1012 | e9c71dd1 | ths | FORCE_RET(); |
1013 | e9c71dd1 | ths | } |
1014 | e9c71dd1 | ths | |
1015 | e9c71dd1 | ths | void op_mulshi (void) |
1016 | e9c71dd1 | ths | { |
1017 | e9c71dd1 | ths | set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
1018 | e9c71dd1 | ths | FORCE_RET(); |
1019 | e9c71dd1 | ths | } |
1020 | e9c71dd1 | ths | |
1021 | e9c71dd1 | ths | void op_mulshiu (void) |
1022 | e9c71dd1 | ths | { |
1023 | e9c71dd1 | ths | set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
1024 | e9c71dd1 | ths | FORCE_RET(); |
1025 | e9c71dd1 | ths | } |
1026 | e9c71dd1 | ths | |
1027 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
1028 | c570fd16 | ths | |
1029 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
1030 | c570fd16 | ths | void op_dmult (void) |
1031 | c570fd16 | ths | { |
1032 | 5592a750 | ths | CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1); |
1033 | 8f6f6026 | ths | FORCE_RET(); |
1034 | c570fd16 | ths | } |
1035 | c570fd16 | ths | |
1036 | c570fd16 | ths | void op_dmultu (void) |
1037 | c570fd16 | ths | { |
1038 | 5592a750 | ths | CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1); |
1039 | 8f6f6026 | ths | FORCE_RET(); |
1040 | c570fd16 | ths | } |
1041 | 6af0bf9c | bellard | #endif
|
1042 | 6af0bf9c | bellard | |
1043 | 6af0bf9c | bellard | /* Conditional moves */
|
1044 | 6af0bf9c | bellard | void op_movn (void) |
1045 | 6af0bf9c | bellard | { |
1046 | 6af0bf9c | bellard | if (T1 != 0) |
1047 | ead9360e | ths | env->gpr[PARAM1][env->current_tc] = T0; |
1048 | 8f6f6026 | ths | FORCE_RET(); |
1049 | 6af0bf9c | bellard | } |
1050 | 6af0bf9c | bellard | |
1051 | 6af0bf9c | bellard | void op_movz (void) |
1052 | 6af0bf9c | bellard | { |
1053 | 6af0bf9c | bellard | if (T1 == 0) |
1054 | ead9360e | ths | env->gpr[PARAM1][env->current_tc] = T0; |
1055 | 8f6f6026 | ths | FORCE_RET(); |
1056 | 6af0bf9c | bellard | } |
1057 | 6af0bf9c | bellard | |
1058 | 7a387fff | ths | void op_movf (void) |
1059 | 7a387fff | ths | { |
1060 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
1061 | 5a5012ec | ths | T0 = T1; |
1062 | 8f6f6026 | ths | FORCE_RET(); |
1063 | 7a387fff | ths | } |
1064 | 7a387fff | ths | |
1065 | 7a387fff | ths | void op_movt (void) |
1066 | 7a387fff | ths | { |
1067 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
1068 | 5a5012ec | ths | T0 = T1; |
1069 | 8f6f6026 | ths | FORCE_RET(); |
1070 | 7a387fff | ths | } |
1071 | 7a387fff | ths | |
1072 | 6af0bf9c | bellard | /* Tests */
|
1073 | 6af0bf9c | bellard | #define OP_COND(name, cond) \
|
1074 | 6af0bf9c | bellard | void glue(op_, name) (void) \ |
1075 | 6af0bf9c | bellard | { \ |
1076 | 6af0bf9c | bellard | if (cond) { \
|
1077 | 6af0bf9c | bellard | T0 = 1; \
|
1078 | 6af0bf9c | bellard | } else { \
|
1079 | 6af0bf9c | bellard | T0 = 0; \
|
1080 | 6af0bf9c | bellard | } \ |
1081 | 8f6f6026 | ths | FORCE_RET(); \ |
1082 | 6af0bf9c | bellard | } |
1083 | 6af0bf9c | bellard | |
1084 | 6af0bf9c | bellard | OP_COND(eq, T0 == T1); |
1085 | 6af0bf9c | bellard | OP_COND(ne, T0 != T1); |
1086 | f469b9db | ths | OP_COND(ge, (target_long)T0 >= (target_long)T1); |
1087 | 6af0bf9c | bellard | OP_COND(geu, T0 >= T1); |
1088 | f469b9db | ths | OP_COND(lt, (target_long)T0 < (target_long)T1); |
1089 | 6af0bf9c | bellard | OP_COND(ltu, T0 < T1); |
1090 | f469b9db | ths | OP_COND(gez, (target_long)T0 >= 0);
|
1091 | f469b9db | ths | OP_COND(gtz, (target_long)T0 > 0);
|
1092 | f469b9db | ths | OP_COND(lez, (target_long)T0 <= 0);
|
1093 | f469b9db | ths | OP_COND(ltz, (target_long)T0 < 0);
|
1094 | 6af0bf9c | bellard | |
1095 | 7a387fff | ths | /* Branches */
|
1096 | 6af0bf9c | bellard | /* Branch to register */
|
1097 | 6af0bf9c | bellard | void op_save_breg_target (void) |
1098 | 6af0bf9c | bellard | { |
1099 | 6af0bf9c | bellard | env->btarget = T2; |
1100 | 8f6f6026 | ths | FORCE_RET(); |
1101 | 6af0bf9c | bellard | } |
1102 | 6af0bf9c | bellard | |
1103 | 6af0bf9c | bellard | void op_restore_breg_target (void) |
1104 | 6af0bf9c | bellard | { |
1105 | 6af0bf9c | bellard | T2 = env->btarget; |
1106 | 8f6f6026 | ths | FORCE_RET(); |
1107 | 6af0bf9c | bellard | } |
1108 | 6af0bf9c | bellard | |
1109 | 6af0bf9c | bellard | void op_breg (void) |
1110 | 6af0bf9c | bellard | { |
1111 | ead9360e | ths | env->PC[env->current_tc] = T2; |
1112 | 8f6f6026 | ths | FORCE_RET(); |
1113 | 6af0bf9c | bellard | } |
1114 | 6af0bf9c | bellard | |
1115 | 6af0bf9c | bellard | void op_save_btarget (void) |
1116 | 6af0bf9c | bellard | { |
1117 | 6af0bf9c | bellard | env->btarget = PARAM1; |
1118 | 8f6f6026 | ths | FORCE_RET(); |
1119 | 6af0bf9c | bellard | } |
1120 | 6af0bf9c | bellard | |
1121 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
1122 | 9b9e4393 | ths | void op_save_btarget64 (void) |
1123 | 9b9e4393 | ths | { |
1124 | 9b9e4393 | ths | env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
1125 | 8f6f6026 | ths | FORCE_RET(); |
1126 | 9b9e4393 | ths | } |
1127 | 9b9e4393 | ths | #endif
|
1128 | 9b9e4393 | ths | |
1129 | 6af0bf9c | bellard | /* Conditional branch */
|
1130 | 6af0bf9c | bellard | void op_set_bcond (void) |
1131 | 6af0bf9c | bellard | { |
1132 | 6af0bf9c | bellard | T2 = T0; |
1133 | 8f6f6026 | ths | FORCE_RET(); |
1134 | 6af0bf9c | bellard | } |
1135 | 6af0bf9c | bellard | |
1136 | 6af0bf9c | bellard | void op_save_bcond (void) |
1137 | 6af0bf9c | bellard | { |
1138 | 6af0bf9c | bellard | env->bcond = T2; |
1139 | 8f6f6026 | ths | FORCE_RET(); |
1140 | 6af0bf9c | bellard | } |
1141 | 6af0bf9c | bellard | |
1142 | 6af0bf9c | bellard | void op_restore_bcond (void) |
1143 | 6af0bf9c | bellard | { |
1144 | 6af0bf9c | bellard | T2 = env->bcond; |
1145 | 8f6f6026 | ths | FORCE_RET(); |
1146 | 6af0bf9c | bellard | } |
1147 | 6af0bf9c | bellard | |
1148 | c53be334 | bellard | void op_jnz_T2 (void) |
1149 | 6af0bf9c | bellard | { |
1150 | c53be334 | bellard | if (T2)
|
1151 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
1152 | 8f6f6026 | ths | FORCE_RET(); |
1153 | 6af0bf9c | bellard | } |
1154 | 6af0bf9c | bellard | |
1155 | 6af0bf9c | bellard | /* CP0 functions */
|
1156 | 873eb012 | ths | void op_mfc0_index (void) |
1157 | 6af0bf9c | bellard | { |
1158 | 9c2149c8 | ths | T0 = env->CP0_Index; |
1159 | 8f6f6026 | ths | FORCE_RET(); |
1160 | 873eb012 | ths | } |
1161 | 873eb012 | ths | |
1162 | ead9360e | ths | void op_mfc0_mvpcontrol (void) |
1163 | ead9360e | ths | { |
1164 | ead9360e | ths | T0 = env->mvp->CP0_MVPControl; |
1165 | 8f6f6026 | ths | FORCE_RET(); |
1166 | ead9360e | ths | } |
1167 | ead9360e | ths | |
1168 | ead9360e | ths | void op_mfc0_mvpconf0 (void) |
1169 | ead9360e | ths | { |
1170 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf0; |
1171 | 8f6f6026 | ths | FORCE_RET(); |
1172 | ead9360e | ths | } |
1173 | ead9360e | ths | |
1174 | ead9360e | ths | void op_mfc0_mvpconf1 (void) |
1175 | ead9360e | ths | { |
1176 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf1; |
1177 | 8f6f6026 | ths | FORCE_RET(); |
1178 | ead9360e | ths | } |
1179 | ead9360e | ths | |
1180 | 873eb012 | ths | void op_mfc0_random (void) |
1181 | 873eb012 | ths | { |
1182 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_random); |
1183 | 8f6f6026 | ths | FORCE_RET(); |
1184 | 873eb012 | ths | } |
1185 | 873eb012 | ths | |
1186 | ead9360e | ths | void op_mfc0_vpecontrol (void) |
1187 | ead9360e | ths | { |
1188 | ead9360e | ths | T0 = env->CP0_VPEControl; |
1189 | 8f6f6026 | ths | FORCE_RET(); |
1190 | ead9360e | ths | } |
1191 | ead9360e | ths | |
1192 | ead9360e | ths | void op_mfc0_vpeconf0 (void) |
1193 | ead9360e | ths | { |
1194 | ead9360e | ths | T0 = env->CP0_VPEConf0; |
1195 | 8f6f6026 | ths | FORCE_RET(); |
1196 | ead9360e | ths | } |
1197 | ead9360e | ths | |
1198 | ead9360e | ths | void op_mfc0_vpeconf1 (void) |
1199 | ead9360e | ths | { |
1200 | ead9360e | ths | T0 = env->CP0_VPEConf1; |
1201 | 8f6f6026 | ths | FORCE_RET(); |
1202 | ead9360e | ths | } |
1203 | ead9360e | ths | |
1204 | ead9360e | ths | void op_mfc0_yqmask (void) |
1205 | ead9360e | ths | { |
1206 | ead9360e | ths | T0 = env->CP0_YQMask; |
1207 | 8f6f6026 | ths | FORCE_RET(); |
1208 | ead9360e | ths | } |
1209 | ead9360e | ths | |
1210 | ead9360e | ths | void op_mfc0_vpeschedule (void) |
1211 | ead9360e | ths | { |
1212 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
1213 | 8f6f6026 | ths | FORCE_RET(); |
1214 | ead9360e | ths | } |
1215 | ead9360e | ths | |
1216 | ead9360e | ths | void op_mfc0_vpeschefback (void) |
1217 | ead9360e | ths | { |
1218 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
1219 | 8f6f6026 | ths | FORCE_RET(); |
1220 | ead9360e | ths | } |
1221 | ead9360e | ths | |
1222 | ead9360e | ths | void op_mfc0_vpeopt (void) |
1223 | ead9360e | ths | { |
1224 | ead9360e | ths | T0 = env->CP0_VPEOpt; |
1225 | 8f6f6026 | ths | FORCE_RET(); |
1226 | ead9360e | ths | } |
1227 | ead9360e | ths | |
1228 | 873eb012 | ths | void op_mfc0_entrylo0 (void) |
1229 | 873eb012 | ths | { |
1230 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo0; |
1231 | 8f6f6026 | ths | FORCE_RET(); |
1232 | 873eb012 | ths | } |
1233 | 873eb012 | ths | |
1234 | ead9360e | ths | void op_mfc0_tcstatus (void) |
1235 | ead9360e | ths | { |
1236 | ead9360e | ths | T0 = env->CP0_TCStatus[env->current_tc]; |
1237 | 8f6f6026 | ths | FORCE_RET(); |
1238 | ead9360e | ths | } |
1239 | ead9360e | ths | |
1240 | ead9360e | ths | void op_mftc0_tcstatus(void) |
1241 | ead9360e | ths | { |
1242 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1243 | ead9360e | ths | |
1244 | ead9360e | ths | T0 = env->CP0_TCStatus[other_tc]; |
1245 | 8f6f6026 | ths | FORCE_RET(); |
1246 | ead9360e | ths | } |
1247 | ead9360e | ths | |
1248 | ead9360e | ths | void op_mfc0_tcbind (void) |
1249 | ead9360e | ths | { |
1250 | ead9360e | ths | T0 = env->CP0_TCBind[env->current_tc]; |
1251 | 8f6f6026 | ths | FORCE_RET(); |
1252 | ead9360e | ths | } |
1253 | ead9360e | ths | |
1254 | ead9360e | ths | void op_mftc0_tcbind(void) |
1255 | ead9360e | ths | { |
1256 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1257 | ead9360e | ths | |
1258 | ead9360e | ths | T0 = env->CP0_TCBind[other_tc]; |
1259 | 8f6f6026 | ths | FORCE_RET(); |
1260 | ead9360e | ths | } |
1261 | ead9360e | ths | |
1262 | ead9360e | ths | void op_mfc0_tcrestart (void) |
1263 | ead9360e | ths | { |
1264 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
1265 | 8f6f6026 | ths | FORCE_RET(); |
1266 | ead9360e | ths | } |
1267 | ead9360e | ths | |
1268 | ead9360e | ths | void op_mftc0_tcrestart(void) |
1269 | ead9360e | ths | { |
1270 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1271 | ead9360e | ths | |
1272 | ead9360e | ths | T0 = env->PC[other_tc]; |
1273 | 8f6f6026 | ths | FORCE_RET(); |
1274 | ead9360e | ths | } |
1275 | ead9360e | ths | |
1276 | ead9360e | ths | void op_mfc0_tchalt (void) |
1277 | ead9360e | ths | { |
1278 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
1279 | 8f6f6026 | ths | FORCE_RET(); |
1280 | ead9360e | ths | } |
1281 | ead9360e | ths | |
1282 | ead9360e | ths | void op_mftc0_tchalt(void) |
1283 | ead9360e | ths | { |
1284 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1285 | ead9360e | ths | |
1286 | ead9360e | ths | T0 = env->CP0_TCHalt[other_tc]; |
1287 | 8f6f6026 | ths | FORCE_RET(); |
1288 | ead9360e | ths | } |
1289 | ead9360e | ths | |
1290 | ead9360e | ths | void op_mfc0_tccontext (void) |
1291 | ead9360e | ths | { |
1292 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
1293 | 8f6f6026 | ths | FORCE_RET(); |
1294 | ead9360e | ths | } |
1295 | ead9360e | ths | |
1296 | ead9360e | ths | void op_mftc0_tccontext(void) |
1297 | ead9360e | ths | { |
1298 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1299 | ead9360e | ths | |
1300 | ead9360e | ths | T0 = env->CP0_TCContext[other_tc]; |
1301 | 8f6f6026 | ths | FORCE_RET(); |
1302 | ead9360e | ths | } |
1303 | ead9360e | ths | |
1304 | ead9360e | ths | void op_mfc0_tcschedule (void) |
1305 | ead9360e | ths | { |
1306 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
1307 | 8f6f6026 | ths | FORCE_RET(); |
1308 | ead9360e | ths | } |
1309 | ead9360e | ths | |
1310 | ead9360e | ths | void op_mftc0_tcschedule(void) |
1311 | ead9360e | ths | { |
1312 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1313 | ead9360e | ths | |
1314 | ead9360e | ths | T0 = env->CP0_TCSchedule[other_tc]; |
1315 | 8f6f6026 | ths | FORCE_RET(); |
1316 | ead9360e | ths | } |
1317 | ead9360e | ths | |
1318 | ead9360e | ths | void op_mfc0_tcschefback (void) |
1319 | ead9360e | ths | { |
1320 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
1321 | 8f6f6026 | ths | FORCE_RET(); |
1322 | ead9360e | ths | } |
1323 | ead9360e | ths | |
1324 | ead9360e | ths | void op_mftc0_tcschefback(void) |
1325 | ead9360e | ths | { |
1326 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1327 | ead9360e | ths | |
1328 | ead9360e | ths | T0 = env->CP0_TCScheFBack[other_tc]; |
1329 | 8f6f6026 | ths | FORCE_RET(); |
1330 | ead9360e | ths | } |
1331 | ead9360e | ths | |
1332 | 873eb012 | ths | void op_mfc0_entrylo1 (void) |
1333 | 873eb012 | ths | { |
1334 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo1; |
1335 | 8f6f6026 | ths | FORCE_RET(); |
1336 | 873eb012 | ths | } |
1337 | 873eb012 | ths | |
1338 | 873eb012 | ths | void op_mfc0_context (void) |
1339 | 873eb012 | ths | { |
1340 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_Context; |
1341 | 8f6f6026 | ths | FORCE_RET(); |
1342 | 873eb012 | ths | } |
1343 | 873eb012 | ths | |
1344 | 873eb012 | ths | void op_mfc0_pagemask (void) |
1345 | 873eb012 | ths | { |
1346 | 9c2149c8 | ths | T0 = env->CP0_PageMask; |
1347 | 8f6f6026 | ths | FORCE_RET(); |
1348 | 873eb012 | ths | } |
1349 | 873eb012 | ths | |
1350 | 7a387fff | ths | void op_mfc0_pagegrain (void) |
1351 | 7a387fff | ths | { |
1352 | 9c2149c8 | ths | T0 = env->CP0_PageGrain; |
1353 | 8f6f6026 | ths | FORCE_RET(); |
1354 | 7a387fff | ths | } |
1355 | 7a387fff | ths | |
1356 | 873eb012 | ths | void op_mfc0_wired (void) |
1357 | 873eb012 | ths | { |
1358 | 9c2149c8 | ths | T0 = env->CP0_Wired; |
1359 | 8f6f6026 | ths | FORCE_RET(); |
1360 | 873eb012 | ths | } |
1361 | 873eb012 | ths | |
1362 | ead9360e | ths | void op_mfc0_srsconf0 (void) |
1363 | ead9360e | ths | { |
1364 | ead9360e | ths | T0 = env->CP0_SRSConf0; |
1365 | 8f6f6026 | ths | FORCE_RET(); |
1366 | ead9360e | ths | } |
1367 | ead9360e | ths | |
1368 | ead9360e | ths | void op_mfc0_srsconf1 (void) |
1369 | ead9360e | ths | { |
1370 | ead9360e | ths | T0 = env->CP0_SRSConf1; |
1371 | 8f6f6026 | ths | FORCE_RET(); |
1372 | ead9360e | ths | } |
1373 | ead9360e | ths | |
1374 | ead9360e | ths | void op_mfc0_srsconf2 (void) |
1375 | ead9360e | ths | { |
1376 | ead9360e | ths | T0 = env->CP0_SRSConf2; |
1377 | 8f6f6026 | ths | FORCE_RET(); |
1378 | ead9360e | ths | } |
1379 | ead9360e | ths | |
1380 | ead9360e | ths | void op_mfc0_srsconf3 (void) |
1381 | ead9360e | ths | { |
1382 | ead9360e | ths | T0 = env->CP0_SRSConf3; |
1383 | 8f6f6026 | ths | FORCE_RET(); |
1384 | ead9360e | ths | } |
1385 | ead9360e | ths | |
1386 | ead9360e | ths | void op_mfc0_srsconf4 (void) |
1387 | ead9360e | ths | { |
1388 | ead9360e | ths | T0 = env->CP0_SRSConf4; |
1389 | 8f6f6026 | ths | FORCE_RET(); |
1390 | ead9360e | ths | } |
1391 | ead9360e | ths | |
1392 | 7a387fff | ths | void op_mfc0_hwrena (void) |
1393 | 7a387fff | ths | { |
1394 | 9c2149c8 | ths | T0 = env->CP0_HWREna; |
1395 | 8f6f6026 | ths | FORCE_RET(); |
1396 | 7a387fff | ths | } |
1397 | 7a387fff | ths | |
1398 | 873eb012 | ths | void op_mfc0_badvaddr (void) |
1399 | 873eb012 | ths | { |
1400 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_BadVAddr; |
1401 | 8f6f6026 | ths | FORCE_RET(); |
1402 | 873eb012 | ths | } |
1403 | 873eb012 | ths | |
1404 | 873eb012 | ths | void op_mfc0_count (void) |
1405 | 873eb012 | ths | { |
1406 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_count); |
1407 | 8f6f6026 | ths | FORCE_RET(); |
1408 | 873eb012 | ths | } |
1409 | 873eb012 | ths | |
1410 | 873eb012 | ths | void op_mfc0_entryhi (void) |
1411 | 873eb012 | ths | { |
1412 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryHi; |
1413 | 8f6f6026 | ths | FORCE_RET(); |
1414 | 873eb012 | ths | } |
1415 | 873eb012 | ths | |
1416 | ead9360e | ths | void op_mftc0_entryhi(void) |
1417 | ead9360e | ths | { |
1418 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1419 | ead9360e | ths | |
1420 | ead9360e | ths | T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); |
1421 | 8f6f6026 | ths | FORCE_RET(); |
1422 | ead9360e | ths | } |
1423 | ead9360e | ths | |
1424 | 873eb012 | ths | void op_mfc0_compare (void) |
1425 | 873eb012 | ths | { |
1426 | 9c2149c8 | ths | T0 = env->CP0_Compare; |
1427 | 8f6f6026 | ths | FORCE_RET(); |
1428 | 873eb012 | ths | } |
1429 | 873eb012 | ths | |
1430 | 873eb012 | ths | void op_mfc0_status (void) |
1431 | 873eb012 | ths | { |
1432 | 9c2149c8 | ths | T0 = env->CP0_Status; |
1433 | 8f6f6026 | ths | FORCE_RET(); |
1434 | 873eb012 | ths | } |
1435 | 873eb012 | ths | |
1436 | ead9360e | ths | void op_mftc0_status(void) |
1437 | ead9360e | ths | { |
1438 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1439 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
1440 | ead9360e | ths | |
1441 | ead9360e | ths | T0 = env->CP0_Status & ~0xf1000018;
|
1442 | ead9360e | ths | T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
|
1443 | ead9360e | ths | T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
|
1444 | 623a930e | ths | T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
|
1445 | 8f6f6026 | ths | FORCE_RET(); |
1446 | ead9360e | ths | } |
1447 | ead9360e | ths | |
1448 | 7a387fff | ths | void op_mfc0_intctl (void) |
1449 | 7a387fff | ths | { |
1450 | 9c2149c8 | ths | T0 = env->CP0_IntCtl; |
1451 | 8f6f6026 | ths | FORCE_RET(); |
1452 | 7a387fff | ths | } |
1453 | 7a387fff | ths | |
1454 | 7a387fff | ths | void op_mfc0_srsctl (void) |
1455 | 7a387fff | ths | { |
1456 | 9c2149c8 | ths | T0 = env->CP0_SRSCtl; |
1457 | 8f6f6026 | ths | FORCE_RET(); |
1458 | 9c2149c8 | ths | } |
1459 | 9c2149c8 | ths | |
1460 | 9c2149c8 | ths | void op_mfc0_srsmap (void) |
1461 | 9c2149c8 | ths | { |
1462 | 9c2149c8 | ths | T0 = env->CP0_SRSMap; |
1463 | 8f6f6026 | ths | FORCE_RET(); |
1464 | 7a387fff | ths | } |
1465 | 7a387fff | ths | |
1466 | 873eb012 | ths | void op_mfc0_cause (void) |
1467 | 873eb012 | ths | { |
1468 | 9c2149c8 | ths | T0 = env->CP0_Cause; |
1469 | 8f6f6026 | ths | FORCE_RET(); |
1470 | 873eb012 | ths | } |
1471 | 873eb012 | ths | |
1472 | 873eb012 | ths | void op_mfc0_epc (void) |
1473 | 873eb012 | ths | { |
1474 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EPC; |
1475 | 8f6f6026 | ths | FORCE_RET(); |
1476 | 873eb012 | ths | } |
1477 | 873eb012 | ths | |
1478 | 873eb012 | ths | void op_mfc0_prid (void) |
1479 | 873eb012 | ths | { |
1480 | 9c2149c8 | ths | T0 = env->CP0_PRid; |
1481 | 8f6f6026 | ths | FORCE_RET(); |
1482 | 873eb012 | ths | } |
1483 | 873eb012 | ths | |
1484 | 7a387fff | ths | void op_mfc0_ebase (void) |
1485 | 7a387fff | ths | { |
1486 | b29a0341 | ths | T0 = env->CP0_EBase; |
1487 | 8f6f6026 | ths | FORCE_RET(); |
1488 | 7a387fff | ths | } |
1489 | 7a387fff | ths | |
1490 | 873eb012 | ths | void op_mfc0_config0 (void) |
1491 | 873eb012 | ths | { |
1492 | 9c2149c8 | ths | T0 = env->CP0_Config0; |
1493 | 8f6f6026 | ths | FORCE_RET(); |
1494 | 873eb012 | ths | } |
1495 | 873eb012 | ths | |
1496 | 873eb012 | ths | void op_mfc0_config1 (void) |
1497 | 873eb012 | ths | { |
1498 | 9c2149c8 | ths | T0 = env->CP0_Config1; |
1499 | 8f6f6026 | ths | FORCE_RET(); |
1500 | 873eb012 | ths | } |
1501 | 873eb012 | ths | |
1502 | 7a387fff | ths | void op_mfc0_config2 (void) |
1503 | 7a387fff | ths | { |
1504 | 9c2149c8 | ths | T0 = env->CP0_Config2; |
1505 | 8f6f6026 | ths | FORCE_RET(); |
1506 | 7a387fff | ths | } |
1507 | 7a387fff | ths | |
1508 | 7a387fff | ths | void op_mfc0_config3 (void) |
1509 | 7a387fff | ths | { |
1510 | 9c2149c8 | ths | T0 = env->CP0_Config3; |
1511 | 8f6f6026 | ths | FORCE_RET(); |
1512 | 7a387fff | ths | } |
1513 | 7a387fff | ths | |
1514 | e397ee33 | ths | void op_mfc0_config6 (void) |
1515 | e397ee33 | ths | { |
1516 | e397ee33 | ths | T0 = env->CP0_Config6; |
1517 | 8f6f6026 | ths | FORCE_RET(); |
1518 | e397ee33 | ths | } |
1519 | e397ee33 | ths | |
1520 | e397ee33 | ths | void op_mfc0_config7 (void) |
1521 | e397ee33 | ths | { |
1522 | e397ee33 | ths | T0 = env->CP0_Config7; |
1523 | 8f6f6026 | ths | FORCE_RET(); |
1524 | e397ee33 | ths | } |
1525 | e397ee33 | ths | |
1526 | 873eb012 | ths | void op_mfc0_lladdr (void) |
1527 | 873eb012 | ths | { |
1528 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_LLAddr >> 4;
|
1529 | 8f6f6026 | ths | FORCE_RET(); |
1530 | 873eb012 | ths | } |
1531 | 873eb012 | ths | |
1532 | fd88b6ab | ths | void op_mfc0_watchlo (void) |
1533 | 873eb012 | ths | { |
1534 | fd88b6ab | ths | T0 = (int32_t)env->CP0_WatchLo[PARAM1]; |
1535 | 8f6f6026 | ths | FORCE_RET(); |
1536 | 873eb012 | ths | } |
1537 | 873eb012 | ths | |
1538 | fd88b6ab | ths | void op_mfc0_watchhi (void) |
1539 | 873eb012 | ths | { |
1540 | fd88b6ab | ths | T0 = env->CP0_WatchHi[PARAM1]; |
1541 | 8f6f6026 | ths | FORCE_RET(); |
1542 | 873eb012 | ths | } |
1543 | 873eb012 | ths | |
1544 | 7a387fff | ths | void op_mfc0_xcontext (void) |
1545 | 7a387fff | ths | { |
1546 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_XContext; |
1547 | 8f6f6026 | ths | FORCE_RET(); |
1548 | 7a387fff | ths | } |
1549 | 7a387fff | ths | |
1550 | 7a387fff | ths | void op_mfc0_framemask (void) |
1551 | 7a387fff | ths | { |
1552 | 7a387fff | ths | T0 = env->CP0_Framemask; |
1553 | 8f6f6026 | ths | FORCE_RET(); |
1554 | 7a387fff | ths | } |
1555 | 7a387fff | ths | |
1556 | 873eb012 | ths | void op_mfc0_debug (void) |
1557 | 873eb012 | ths | { |
1558 | 9c2149c8 | ths | T0 = env->CP0_Debug; |
1559 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
1560 | 873eb012 | ths | T0 |= 1 << CP0DB_DM;
|
1561 | 8f6f6026 | ths | FORCE_RET(); |
1562 | 873eb012 | ths | } |
1563 | 873eb012 | ths | |
1564 | ead9360e | ths | void op_mftc0_debug(void) |
1565 | ead9360e | ths | { |
1566 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1567 | ead9360e | ths | |
1568 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
1569 | ead9360e | ths | T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1570 | ead9360e | ths | (env->CP0_Debug_tcstatus[other_tc] & |
1571 | ead9360e | ths | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
1572 | 8f6f6026 | ths | FORCE_RET(); |
1573 | ead9360e | ths | } |
1574 | ead9360e | ths | |
1575 | 873eb012 | ths | void op_mfc0_depc (void) |
1576 | 873eb012 | ths | { |
1577 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_DEPC; |
1578 | 8f6f6026 | ths | FORCE_RET(); |
1579 | 873eb012 | ths | } |
1580 | 873eb012 | ths | |
1581 | 7a387fff | ths | void op_mfc0_performance0 (void) |
1582 | 7a387fff | ths | { |
1583 | 9c2149c8 | ths | T0 = env->CP0_Performance0; |
1584 | 8f6f6026 | ths | FORCE_RET(); |
1585 | 7a387fff | ths | } |
1586 | 7a387fff | ths | |
1587 | 873eb012 | ths | void op_mfc0_taglo (void) |
1588 | 873eb012 | ths | { |
1589 | 9c2149c8 | ths | T0 = env->CP0_TagLo; |
1590 | 8f6f6026 | ths | FORCE_RET(); |
1591 | 873eb012 | ths | } |
1592 | 873eb012 | ths | |
1593 | 873eb012 | ths | void op_mfc0_datalo (void) |
1594 | 873eb012 | ths | { |
1595 | 9c2149c8 | ths | T0 = env->CP0_DataLo; |
1596 | 8f6f6026 | ths | FORCE_RET(); |
1597 | 873eb012 | ths | } |
1598 | 873eb012 | ths | |
1599 | 7a387fff | ths | void op_mfc0_taghi (void) |
1600 | 7a387fff | ths | { |
1601 | 9c2149c8 | ths | T0 = env->CP0_TagHi; |
1602 | 8f6f6026 | ths | FORCE_RET(); |
1603 | 7a387fff | ths | } |
1604 | 7a387fff | ths | |
1605 | 7a387fff | ths | void op_mfc0_datahi (void) |
1606 | 7a387fff | ths | { |
1607 | 9c2149c8 | ths | T0 = env->CP0_DataHi; |
1608 | 8f6f6026 | ths | FORCE_RET(); |
1609 | 7a387fff | ths | } |
1610 | 7a387fff | ths | |
1611 | 873eb012 | ths | void op_mfc0_errorepc (void) |
1612 | 873eb012 | ths | { |
1613 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_ErrorEPC; |
1614 | 8f6f6026 | ths | FORCE_RET(); |
1615 | 873eb012 | ths | } |
1616 | 873eb012 | ths | |
1617 | 873eb012 | ths | void op_mfc0_desave (void) |
1618 | 873eb012 | ths | { |
1619 | 9c2149c8 | ths | T0 = env->CP0_DESAVE; |
1620 | 8f6f6026 | ths | FORCE_RET(); |
1621 | 6af0bf9c | bellard | } |
1622 | 6af0bf9c | bellard | |
1623 | 8c0fdd85 | ths | void op_mtc0_index (void) |
1624 | 6af0bf9c | bellard | { |
1625 | 60445285 | ths | int num = 1; |
1626 | 60445285 | ths | unsigned int tmp = env->tlb->nb_tlb; |
1627 | 60445285 | ths | |
1628 | 60445285 | ths | do {
|
1629 | 60445285 | ths | tmp >>= 1;
|
1630 | 60445285 | ths | num <<= 1;
|
1631 | 60445285 | ths | } while (tmp);
|
1632 | 60445285 | ths | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); |
1633 | 8f6f6026 | ths | FORCE_RET(); |
1634 | ead9360e | ths | } |
1635 | ead9360e | ths | |
1636 | ead9360e | ths | void op_mtc0_mvpcontrol (void) |
1637 | ead9360e | ths | { |
1638 | ead9360e | ths | uint32_t mask = 0;
|
1639 | ead9360e | ths | uint32_t newval; |
1640 | ead9360e | ths | |
1641 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
1642 | ead9360e | ths | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
1643 | ead9360e | ths | (1 << CP0MVPCo_EVP);
|
1644 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1645 | ead9360e | ths | mask |= (1 << CP0MVPCo_STLB);
|
1646 | ead9360e | ths | newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); |
1647 | ead9360e | ths | |
1648 | ead9360e | ths | // TODO: Enable/disable shared TLB, enable/disable VPEs.
|
1649 | ead9360e | ths | |
1650 | ead9360e | ths | env->mvp->CP0_MVPControl = newval; |
1651 | 8f6f6026 | ths | FORCE_RET(); |
1652 | ead9360e | ths | } |
1653 | ead9360e | ths | |
1654 | ead9360e | ths | void op_mtc0_vpecontrol (void) |
1655 | ead9360e | ths | { |
1656 | ead9360e | ths | uint32_t mask; |
1657 | ead9360e | ths | uint32_t newval; |
1658 | ead9360e | ths | |
1659 | ead9360e | ths | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
1660 | ead9360e | ths | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
1661 | ead9360e | ths | newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); |
1662 | ead9360e | ths | |
1663 | ead9360e | ths | /* Yield scheduler intercept not implemented. */
|
1664 | ead9360e | ths | /* Gating storage scheduler intercept not implemented. */
|
1665 | ead9360e | ths | |
1666 | ead9360e | ths | // TODO: Enable/disable TCs.
|
1667 | ead9360e | ths | |
1668 | ead9360e | ths | env->CP0_VPEControl = newval; |
1669 | 8f6f6026 | ths | FORCE_RET(); |
1670 | ead9360e | ths | } |
1671 | ead9360e | ths | |
1672 | ead9360e | ths | void op_mtc0_vpeconf0 (void) |
1673 | ead9360e | ths | { |
1674 | ead9360e | ths | uint32_t mask = 0;
|
1675 | ead9360e | ths | uint32_t newval; |
1676 | ead9360e | ths | |
1677 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
1678 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
1679 | ead9360e | ths | mask |= (0xff << CP0VPEC0_XTC);
|
1680 | ead9360e | ths | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
1681 | ead9360e | ths | } |
1682 | ead9360e | ths | newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); |
1683 | ead9360e | ths | |
1684 | ead9360e | ths | // TODO: TC exclusive handling due to ERL/EXL.
|
1685 | ead9360e | ths | |
1686 | ead9360e | ths | env->CP0_VPEConf0 = newval; |
1687 | 8f6f6026 | ths | FORCE_RET(); |
1688 | ead9360e | ths | } |
1689 | ead9360e | ths | |
1690 | ead9360e | ths | void op_mtc0_vpeconf1 (void) |
1691 | ead9360e | ths | { |
1692 | ead9360e | ths | uint32_t mask = 0;
|
1693 | ead9360e | ths | uint32_t newval; |
1694 | ead9360e | ths | |
1695 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1696 | ead9360e | ths | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
1697 | ead9360e | ths | (0xff << CP0VPEC1_NCP1);
|
1698 | ead9360e | ths | newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); |
1699 | ead9360e | ths | |
1700 | ead9360e | ths | /* UDI not implemented. */
|
1701 | ead9360e | ths | /* CP2 not implemented. */
|
1702 | ead9360e | ths | |
1703 | ead9360e | ths | // TODO: Handle FPU (CP1) binding.
|
1704 | ead9360e | ths | |
1705 | ead9360e | ths | env->CP0_VPEConf1 = newval; |
1706 | 8f6f6026 | ths | FORCE_RET(); |
1707 | ead9360e | ths | } |
1708 | ead9360e | ths | |
1709 | ead9360e | ths | void op_mtc0_yqmask (void) |
1710 | ead9360e | ths | { |
1711 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
1712 | ead9360e | ths | env->CP0_YQMask = 0x00000000;
|
1713 | 8f6f6026 | ths | FORCE_RET(); |
1714 | ead9360e | ths | } |
1715 | ead9360e | ths | |
1716 | ead9360e | ths | void op_mtc0_vpeschedule (void) |
1717 | ead9360e | ths | { |
1718 | ead9360e | ths | env->CP0_VPESchedule = T0; |
1719 | 8f6f6026 | ths | FORCE_RET(); |
1720 | ead9360e | ths | } |
1721 | ead9360e | ths | |
1722 | ead9360e | ths | void op_mtc0_vpeschefback (void) |
1723 | ead9360e | ths | { |
1724 | ead9360e | ths | env->CP0_VPEScheFBack = T0; |
1725 | 8f6f6026 | ths | FORCE_RET(); |
1726 | ead9360e | ths | } |
1727 | ead9360e | ths | |
1728 | ead9360e | ths | void op_mtc0_vpeopt (void) |
1729 | ead9360e | ths | { |
1730 | ead9360e | ths | env->CP0_VPEOpt = T0 & 0x0000ffff;
|
1731 | 8f6f6026 | ths | FORCE_RET(); |
1732 | 8c0fdd85 | ths | } |
1733 | 8c0fdd85 | ths | |
1734 | 8c0fdd85 | ths | void op_mtc0_entrylo0 (void) |
1735 | 8c0fdd85 | ths | { |
1736 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
1737 | 7a387fff | ths | /* 1k pages not implemented */
|
1738 | f1b0aa5d | ths | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
1739 | 8f6f6026 | ths | FORCE_RET(); |
1740 | 8c0fdd85 | ths | } |
1741 | 8c0fdd85 | ths | |
1742 | ead9360e | ths | void op_mtc0_tcstatus (void) |
1743 | ead9360e | ths | { |
1744 | ead9360e | ths | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
1745 | ead9360e | ths | uint32_t newval; |
1746 | ead9360e | ths | |
1747 | ead9360e | ths | newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); |
1748 | ead9360e | ths | |
1749 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
1750 | ead9360e | ths | |
1751 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = newval; |
1752 | 8f6f6026 | ths | FORCE_RET(); |
1753 | ead9360e | ths | } |
1754 | ead9360e | ths | |
1755 | ead9360e | ths | void op_mttc0_tcstatus (void) |
1756 | ead9360e | ths | { |
1757 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1758 | ead9360e | ths | |
1759 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
1760 | ead9360e | ths | |
1761 | ead9360e | ths | env->CP0_TCStatus[other_tc] = T0; |
1762 | 8f6f6026 | ths | FORCE_RET(); |
1763 | ead9360e | ths | } |
1764 | ead9360e | ths | |
1765 | ead9360e | ths | void op_mtc0_tcbind (void) |
1766 | ead9360e | ths | { |
1767 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
1768 | ead9360e | ths | uint32_t newval; |
1769 | ead9360e | ths | |
1770 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1771 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
1772 | ead9360e | ths | newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); |
1773 | ead9360e | ths | env->CP0_TCBind[env->current_tc] = newval; |
1774 | 8f6f6026 | ths | FORCE_RET(); |
1775 | ead9360e | ths | } |
1776 | ead9360e | ths | |
1777 | ead9360e | ths | void op_mttc0_tcbind (void) |
1778 | ead9360e | ths | { |
1779 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1780 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
1781 | ead9360e | ths | uint32_t newval; |
1782 | ead9360e | ths | |
1783 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1784 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
1785 | ead9360e | ths | newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); |
1786 | ead9360e | ths | env->CP0_TCBind[other_tc] = newval; |
1787 | 8f6f6026 | ths | FORCE_RET(); |
1788 | ead9360e | ths | } |
1789 | ead9360e | ths | |
1790 | ead9360e | ths | void op_mtc0_tcrestart (void) |
1791 | ead9360e | ths | { |
1792 | ead9360e | ths | env->PC[env->current_tc] = T0; |
1793 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
|
1794 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
1795 | ead9360e | ths | /* MIPS16 not implemented. */
|
1796 | 8f6f6026 | ths | FORCE_RET(); |
1797 | ead9360e | ths | } |
1798 | ead9360e | ths | |
1799 | ead9360e | ths | void op_mttc0_tcrestart (void) |
1800 | ead9360e | ths | { |
1801 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1802 | ead9360e | ths | |
1803 | ead9360e | ths | env->PC[other_tc] = T0; |
1804 | ead9360e | ths | env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
|
1805 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
1806 | ead9360e | ths | /* MIPS16 not implemented. */
|
1807 | 8f6f6026 | ths | FORCE_RET(); |
1808 | ead9360e | ths | } |
1809 | ead9360e | ths | |
1810 | ead9360e | ths | void op_mtc0_tchalt (void) |
1811 | ead9360e | ths | { |
1812 | ead9360e | ths | env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
|
1813 | ead9360e | ths | |
1814 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
1815 | ead9360e | ths | |
1816 | 8f6f6026 | ths | FORCE_RET(); |
1817 | ead9360e | ths | } |
1818 | ead9360e | ths | |
1819 | ead9360e | ths | void op_mttc0_tchalt (void) |
1820 | ead9360e | ths | { |
1821 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1822 | ead9360e | ths | |
1823 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
1824 | ead9360e | ths | |
1825 | ead9360e | ths | env->CP0_TCHalt[other_tc] = T0; |
1826 | 8f6f6026 | ths | FORCE_RET(); |
1827 | ead9360e | ths | } |
1828 | ead9360e | ths | |
1829 | ead9360e | ths | void op_mtc0_tccontext (void) |
1830 | ead9360e | ths | { |
1831 | ead9360e | ths | env->CP0_TCContext[env->current_tc] = T0; |
1832 | 8f6f6026 | ths | FORCE_RET(); |
1833 | ead9360e | ths | } |
1834 | ead9360e | ths | |
1835 | ead9360e | ths | void op_mttc0_tccontext (void) |
1836 | ead9360e | ths | { |
1837 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1838 | ead9360e | ths | |
1839 | ead9360e | ths | env->CP0_TCContext[other_tc] = T0; |
1840 | 8f6f6026 | ths | FORCE_RET(); |
1841 | ead9360e | ths | } |
1842 | ead9360e | ths | |
1843 | ead9360e | ths | void op_mtc0_tcschedule (void) |
1844 | ead9360e | ths | { |
1845 | ead9360e | ths | env->CP0_TCSchedule[env->current_tc] = T0; |
1846 | 8f6f6026 | ths | FORCE_RET(); |
1847 | ead9360e | ths | } |
1848 | ead9360e | ths | |
1849 | ead9360e | ths | void op_mttc0_tcschedule (void) |
1850 | ead9360e | ths | { |
1851 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1852 | ead9360e | ths | |
1853 | ead9360e | ths | env->CP0_TCSchedule[other_tc] = T0; |
1854 | 8f6f6026 | ths | FORCE_RET(); |
1855 | ead9360e | ths | } |
1856 | ead9360e | ths | |
1857 | ead9360e | ths | void op_mtc0_tcschefback (void) |
1858 | ead9360e | ths | { |
1859 | ead9360e | ths | env->CP0_TCScheFBack[env->current_tc] = T0; |
1860 | 8f6f6026 | ths | FORCE_RET(); |
1861 | ead9360e | ths | } |
1862 | ead9360e | ths | |
1863 | ead9360e | ths | void op_mttc0_tcschefback (void) |
1864 | ead9360e | ths | { |
1865 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1866 | ead9360e | ths | |
1867 | ead9360e | ths | env->CP0_TCScheFBack[other_tc] = T0; |
1868 | 8f6f6026 | ths | FORCE_RET(); |
1869 | ead9360e | ths | } |
1870 | ead9360e | ths | |
1871 | 8c0fdd85 | ths | void op_mtc0_entrylo1 (void) |
1872 | 8c0fdd85 | ths | { |
1873 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
1874 | 7a387fff | ths | /* 1k pages not implemented */
|
1875 | f1b0aa5d | ths | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
1876 | 8f6f6026 | ths | FORCE_RET(); |
1877 | 8c0fdd85 | ths | } |
1878 | 8c0fdd85 | ths | |
1879 | 8c0fdd85 | ths | void op_mtc0_context (void) |
1880 | 8c0fdd85 | ths | { |
1881 | 534ce69f | ths | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
1882 | 8f6f6026 | ths | FORCE_RET(); |
1883 | 8c0fdd85 | ths | } |
1884 | 8c0fdd85 | ths | |
1885 | 8c0fdd85 | ths | void op_mtc0_pagemask (void) |
1886 | 8c0fdd85 | ths | { |
1887 | 7a387fff | ths | /* 1k pages not implemented */
|
1888 | f2e9ebef | ths | env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
1889 | 8f6f6026 | ths | FORCE_RET(); |
1890 | 7a387fff | ths | } |
1891 | 7a387fff | ths | |
1892 | 7a387fff | ths | void op_mtc0_pagegrain (void) |
1893 | 7a387fff | ths | { |
1894 | 7a387fff | ths | /* SmartMIPS not implemented */
|
1895 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
1896 | 7a387fff | ths | /* 1k pages not implemented */
|
1897 | 7a387fff | ths | env->CP0_PageGrain = 0;
|
1898 | 8f6f6026 | ths | FORCE_RET(); |
1899 | 8c0fdd85 | ths | } |
1900 | 8c0fdd85 | ths | |
1901 | 8c0fdd85 | ths | void op_mtc0_wired (void) |
1902 | 8c0fdd85 | ths | { |
1903 | ead9360e | ths | env->CP0_Wired = T0 % env->tlb->nb_tlb; |
1904 | 8f6f6026 | ths | FORCE_RET(); |
1905 | ead9360e | ths | } |
1906 | ead9360e | ths | |
1907 | ead9360e | ths | void op_mtc0_srsconf0 (void) |
1908 | ead9360e | ths | { |
1909 | ead9360e | ths | env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; |
1910 | 8f6f6026 | ths | FORCE_RET(); |
1911 | ead9360e | ths | } |
1912 | ead9360e | ths | |
1913 | ead9360e | ths | void op_mtc0_srsconf1 (void) |
1914 | ead9360e | ths | { |
1915 | ead9360e | ths | env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; |
1916 | 8f6f6026 | ths | FORCE_RET(); |
1917 | ead9360e | ths | } |
1918 | ead9360e | ths | |
1919 | ead9360e | ths | void op_mtc0_srsconf2 (void) |
1920 | ead9360e | ths | { |
1921 | ead9360e | ths | env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; |
1922 | 8f6f6026 | ths | FORCE_RET(); |
1923 | ead9360e | ths | } |
1924 | ead9360e | ths | |
1925 | ead9360e | ths | void op_mtc0_srsconf3 (void) |
1926 | ead9360e | ths | { |
1927 | ead9360e | ths | env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; |
1928 | 8f6f6026 | ths | FORCE_RET(); |
1929 | ead9360e | ths | } |
1930 | ead9360e | ths | |
1931 | ead9360e | ths | void op_mtc0_srsconf4 (void) |
1932 | ead9360e | ths | { |
1933 | ead9360e | ths | env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; |
1934 | 8f6f6026 | ths | FORCE_RET(); |
1935 | 7a387fff | ths | } |
1936 | 7a387fff | ths | |
1937 | 7a387fff | ths | void op_mtc0_hwrena (void) |
1938 | 7a387fff | ths | { |
1939 | 7a387fff | ths | env->CP0_HWREna = T0 & 0x0000000F;
|
1940 | 8f6f6026 | ths | FORCE_RET(); |
1941 | 8c0fdd85 | ths | } |
1942 | 8c0fdd85 | ths | |
1943 | 8c0fdd85 | ths | void op_mtc0_count (void) |
1944 | 8c0fdd85 | ths | { |
1945 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
1946 | 8f6f6026 | ths | FORCE_RET(); |
1947 | 8c0fdd85 | ths | } |
1948 | 8c0fdd85 | ths | |
1949 | 8c0fdd85 | ths | void op_mtc0_entryhi (void) |
1950 | 8c0fdd85 | ths | { |
1951 | 0feef828 | ths | target_ulong old, val; |
1952 | 8c0fdd85 | ths | |
1953 | 7a387fff | ths | /* 1k pages not implemented */
|
1954 | 100ce988 | ths | val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
1955 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
1956 | e034e2c3 | ths | val &= env->SEGMask; |
1957 | 100ce988 | ths | #endif
|
1958 | 8c0fdd85 | ths | old = env->CP0_EntryHi; |
1959 | 8c0fdd85 | ths | env->CP0_EntryHi = val; |
1960 | ead9360e | ths | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1961 | ead9360e | ths | uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
|
1962 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
|
1963 | ead9360e | ths | } |
1964 | 8c0fdd85 | ths | /* If the ASID changes, flush qemu's TLB. */
|
1965 | 8c0fdd85 | ths | if ((old & 0xFF) != (val & 0xFF)) |
1966 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
1967 | 8f6f6026 | ths | FORCE_RET(); |
1968 | 8c0fdd85 | ths | } |
1969 | 8c0fdd85 | ths | |
1970 | ead9360e | ths | void op_mttc0_entryhi(void) |
1971 | ead9360e | ths | { |
1972 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1973 | ead9360e | ths | |
1974 | ead9360e | ths | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); |
1975 | ead9360e | ths | env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); |
1976 | 8f6f6026 | ths | FORCE_RET(); |
1977 | ead9360e | ths | } |
1978 | ead9360e | ths | |
1979 | 8c0fdd85 | ths | void op_mtc0_compare (void) |
1980 | 8c0fdd85 | ths | { |
1981 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
1982 | 8f6f6026 | ths | FORCE_RET(); |
1983 | 8c0fdd85 | ths | } |
1984 | 8c0fdd85 | ths | |
1985 | 8c0fdd85 | ths | void op_mtc0_status (void) |
1986 | 8c0fdd85 | ths | { |
1987 | 4de9b249 | ths | uint32_t val, old; |
1988 | ead9360e | ths | uint32_t mask = env->CP0_Status_rw_bitmask; |
1989 | 8c0fdd85 | ths | |
1990 | f1b0aa5d | ths | val = T0 & mask; |
1991 | 8c0fdd85 | ths | old = env->CP0_Status; |
1992 | 5a5012ec | ths | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1993 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
1994 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
1995 | f41c52f1 | ths | CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
1996 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
1997 | 8f6f6026 | ths | FORCE_RET(); |
1998 | 8c0fdd85 | ths | } |
1999 | 8c0fdd85 | ths | |
2000 | ead9360e | ths | void op_mttc0_status(void) |
2001 | ead9360e | ths | { |
2002 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2003 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
2004 | ead9360e | ths | |
2005 | ead9360e | ths | env->CP0_Status = T0 & ~0xf1000018;
|
2006 | ead9360e | ths | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); |
2007 | ead9360e | ths | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); |
2008 | 623a930e | ths | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); |
2009 | ead9360e | ths | env->CP0_TCStatus[other_tc] = tcstatus; |
2010 | 8f6f6026 | ths | FORCE_RET(); |
2011 | ead9360e | ths | } |
2012 | ead9360e | ths | |
2013 | 7a387fff | ths | void op_mtc0_intctl (void) |
2014 | 7a387fff | ths | { |
2015 | 42532189 | ths | /* vectored interrupts not implemented, no performance counters. */
|
2016 | 42532189 | ths | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); |
2017 | 8f6f6026 | ths | FORCE_RET(); |
2018 | 7a387fff | ths | } |
2019 | 7a387fff | ths | |
2020 | 7a387fff | ths | void op_mtc0_srsctl (void) |
2021 | 7a387fff | ths | { |
2022 | ead9360e | ths | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
2023 | ead9360e | ths | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); |
2024 | 8f6f6026 | ths | FORCE_RET(); |
2025 | 7a387fff | ths | } |
2026 | 7a387fff | ths | |
2027 | 9c2149c8 | ths | void op_mtc0_srsmap (void) |
2028 | 9c2149c8 | ths | { |
2029 | ead9360e | ths | env->CP0_SRSMap = T0; |
2030 | 8f6f6026 | ths | FORCE_RET(); |
2031 | 9c2149c8 | ths | } |
2032 | 9c2149c8 | ths | |
2033 | 8c0fdd85 | ths | void op_mtc0_cause (void) |
2034 | 8c0fdd85 | ths | { |
2035 | 39d51eb8 | ths | uint32_t mask = 0x00C00300;
|
2036 | 42532189 | ths | uint32_t old = env->CP0_Cause; |
2037 | 39d51eb8 | ths | |
2038 | e189e748 | ths | if (env->insn_flags & ISA_MIPS32R2)
|
2039 | 39d51eb8 | ths | mask |= 1 << CP0Ca_DC;
|
2040 | 39d51eb8 | ths | |
2041 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
2042 | 8c0fdd85 | ths | |
2043 | 42532189 | ths | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { |
2044 | 42532189 | ths | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
2045 | 42532189 | ths | CALL_FROM_TB1(cpu_mips_stop_count, env); |
2046 | 42532189 | ths | else
|
2047 | 42532189 | ths | CALL_FROM_TB1(cpu_mips_start_count, env); |
2048 | 42532189 | ths | } |
2049 | 42532189 | ths | |
2050 | 4de9b249 | ths | /* Handle the software interrupt as an hardware one, as they
|
2051 | 4de9b249 | ths | are very similar */
|
2052 | 4de9b249 | ths | if (T0 & CP0Ca_IP_mask) {
|
2053 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
2054 | 8c0fdd85 | ths | } |
2055 | 8f6f6026 | ths | FORCE_RET(); |
2056 | 8c0fdd85 | ths | } |
2057 | 8c0fdd85 | ths | |
2058 | 8c0fdd85 | ths | void op_mtc0_epc (void) |
2059 | 8c0fdd85 | ths | { |
2060 | f1b0aa5d | ths | env->CP0_EPC = T0; |
2061 | 8f6f6026 | ths | FORCE_RET(); |
2062 | 8c0fdd85 | ths | } |
2063 | 8c0fdd85 | ths | |
2064 | 7a387fff | ths | void op_mtc0_ebase (void) |
2065 | 7a387fff | ths | { |
2066 | 7a387fff | ths | /* vectored interrupts not implemented */
|
2067 | 7a387fff | ths | /* Multi-CPU not implemented */
|
2068 | b29a0341 | ths | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
2069 | 8f6f6026 | ths | FORCE_RET(); |
2070 | 7a387fff | ths | } |
2071 | 7a387fff | ths | |
2072 | 8c0fdd85 | ths | void op_mtc0_config0 (void) |
2073 | 8c0fdd85 | ths | { |
2074 | 7bfd934a | ths | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); |
2075 | 8f6f6026 | ths | FORCE_RET(); |
2076 | 8c0fdd85 | ths | } |
2077 | 8c0fdd85 | ths | |
2078 | 7a387fff | ths | void op_mtc0_config2 (void) |
2079 | 7a387fff | ths | { |
2080 | 7a387fff | ths | /* tertiary/secondary caches not implemented */
|
2081 | 7a387fff | ths | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
2082 | 8f6f6026 | ths | FORCE_RET(); |
2083 | 7a387fff | ths | } |
2084 | 7a387fff | ths | |
2085 | fd88b6ab | ths | void op_mtc0_watchlo (void) |
2086 | 8c0fdd85 | ths | { |
2087 | 4e7a4a4e | ths | /* Watch exceptions for instructions, data loads, data stores
|
2088 | 4e7a4a4e | ths | not implemented. */
|
2089 | fd88b6ab | ths | env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
|
2090 | 8f6f6026 | ths | FORCE_RET(); |
2091 | 8c0fdd85 | ths | } |
2092 | 8c0fdd85 | ths | |
2093 | fd88b6ab | ths | void op_mtc0_watchhi (void) |
2094 | 8c0fdd85 | ths | { |
2095 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
|
2096 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
|
2097 | 8f6f6026 | ths | FORCE_RET(); |
2098 | 8c0fdd85 | ths | } |
2099 | 8c0fdd85 | ths | |
2100 | ead9360e | ths | void op_mtc0_xcontext (void) |
2101 | ead9360e | ths | { |
2102 | ead9360e | ths | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
2103 | ead9360e | ths | env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); |
2104 | 8f6f6026 | ths | FORCE_RET(); |
2105 | ead9360e | ths | } |
2106 | ead9360e | ths | |
2107 | 7a387fff | ths | void op_mtc0_framemask (void) |
2108 | 7a387fff | ths | { |
2109 | 7a387fff | ths | env->CP0_Framemask = T0; /* XXX */
|
2110 | 8f6f6026 | ths | FORCE_RET(); |
2111 | 7a387fff | ths | } |
2112 | 7a387fff | ths | |
2113 | 8c0fdd85 | ths | void op_mtc0_debug (void) |
2114 | 8c0fdd85 | ths | { |
2115 | 8c0fdd85 | ths | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
2116 | 8c0fdd85 | ths | if (T0 & (1 << CP0DB_DM)) |
2117 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_DM; |
2118 | 8c0fdd85 | ths | else
|
2119 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_DM; |
2120 | 8f6f6026 | ths | FORCE_RET(); |
2121 | 8c0fdd85 | ths | } |
2122 | 8c0fdd85 | ths | |
2123 | ead9360e | ths | void op_mttc0_debug(void) |
2124 | ead9360e | ths | { |
2125 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2126 | ead9360e | ths | |
2127 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
2128 | ead9360e | ths | env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
2129 | ead9360e | ths | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
2130 | ead9360e | ths | (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
2131 | 8f6f6026 | ths | FORCE_RET(); |
2132 | ead9360e | ths | } |
2133 | ead9360e | ths | |
2134 | 8c0fdd85 | ths | void op_mtc0_depc (void) |
2135 | 8c0fdd85 | ths | { |
2136 | f1b0aa5d | ths | env->CP0_DEPC = T0; |
2137 | 8f6f6026 | ths | FORCE_RET(); |
2138 | 8c0fdd85 | ths | } |
2139 | 8c0fdd85 | ths | |
2140 | 7a387fff | ths | void op_mtc0_performance0 (void) |
2141 | 7a387fff | ths | { |
2142 | 1b6fd0bc | ths | env->CP0_Performance0 = T0 & 0x000007ff;
|
2143 | 8f6f6026 | ths | FORCE_RET(); |
2144 | 7a387fff | ths | } |
2145 | 7a387fff | ths | |
2146 | 8c0fdd85 | ths | void op_mtc0_taglo (void) |
2147 | 8c0fdd85 | ths | { |
2148 | 9c2149c8 | ths | env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
2149 | 8f6f6026 | ths | FORCE_RET(); |
2150 | 8c0fdd85 | ths | } |
2151 | 8c0fdd85 | ths | |
2152 | 7a387fff | ths | void op_mtc0_datalo (void) |
2153 | 7a387fff | ths | { |
2154 | 7a387fff | ths | env->CP0_DataLo = T0; /* XXX */
|
2155 | 8f6f6026 | ths | FORCE_RET(); |
2156 | 7a387fff | ths | } |
2157 | 7a387fff | ths | |
2158 | 7a387fff | ths | void op_mtc0_taghi (void) |
2159 | 7a387fff | ths | { |
2160 | 7a387fff | ths | env->CP0_TagHi = T0; /* XXX */
|
2161 | 8f6f6026 | ths | FORCE_RET(); |
2162 | 7a387fff | ths | } |
2163 | 7a387fff | ths | |
2164 | 7a387fff | ths | void op_mtc0_datahi (void) |
2165 | 7a387fff | ths | { |
2166 | 7a387fff | ths | env->CP0_DataHi = T0; /* XXX */
|
2167 | 8f6f6026 | ths | FORCE_RET(); |
2168 | 7a387fff | ths | } |
2169 | 7a387fff | ths | |
2170 | 8c0fdd85 | ths | void op_mtc0_errorepc (void) |
2171 | 8c0fdd85 | ths | { |
2172 | f1b0aa5d | ths | env->CP0_ErrorEPC = T0; |
2173 | 8f6f6026 | ths | FORCE_RET(); |
2174 | 8c0fdd85 | ths | } |
2175 | 8c0fdd85 | ths | |
2176 | 8c0fdd85 | ths | void op_mtc0_desave (void) |
2177 | 8c0fdd85 | ths | { |
2178 | 8c0fdd85 | ths | env->CP0_DESAVE = T0; |
2179 | 8f6f6026 | ths | FORCE_RET(); |
2180 | 6af0bf9c | bellard | } |
2181 | 6af0bf9c | bellard | |
2182 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
2183 | ead9360e | ths | void op_dmfc0_yqmask (void) |
2184 | f1b0aa5d | ths | { |
2185 | ead9360e | ths | T0 = env->CP0_YQMask; |
2186 | 8f6f6026 | ths | FORCE_RET(); |
2187 | ead9360e | ths | } |
2188 | ead9360e | ths | |
2189 | ead9360e | ths | void op_dmfc0_vpeschedule (void) |
2190 | ead9360e | ths | { |
2191 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
2192 | 8f6f6026 | ths | FORCE_RET(); |
2193 | ead9360e | ths | } |
2194 | ead9360e | ths | |
2195 | ead9360e | ths | void op_dmfc0_vpeschefback (void) |
2196 | ead9360e | ths | { |
2197 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
2198 | 8f6f6026 | ths | FORCE_RET(); |
2199 | f1b0aa5d | ths | } |
2200 | f1b0aa5d | ths | |
2201 | 9c2149c8 | ths | void op_dmfc0_entrylo0 (void) |
2202 | 9c2149c8 | ths | { |
2203 | 9c2149c8 | ths | T0 = env->CP0_EntryLo0; |
2204 | 8f6f6026 | ths | FORCE_RET(); |
2205 | 9c2149c8 | ths | } |
2206 | 9c2149c8 | ths | |
2207 | ead9360e | ths | void op_dmfc0_tcrestart (void) |
2208 | ead9360e | ths | { |
2209 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
2210 | 8f6f6026 | ths | FORCE_RET(); |
2211 | ead9360e | ths | } |
2212 | ead9360e | ths | |
2213 | ead9360e | ths | void op_dmfc0_tchalt (void) |
2214 | ead9360e | ths | { |
2215 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
2216 | 8f6f6026 | ths | FORCE_RET(); |
2217 | ead9360e | ths | } |
2218 | ead9360e | ths | |
2219 | ead9360e | ths | void op_dmfc0_tccontext (void) |
2220 | ead9360e | ths | { |
2221 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
2222 | 8f6f6026 | ths | FORCE_RET(); |
2223 | ead9360e | ths | } |
2224 | ead9360e | ths | |
2225 | ead9360e | ths | void op_dmfc0_tcschedule (void) |
2226 | ead9360e | ths | { |
2227 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
2228 | 8f6f6026 | ths | FORCE_RET(); |
2229 | ead9360e | ths | } |
2230 | ead9360e | ths | |
2231 | ead9360e | ths | void op_dmfc0_tcschefback (void) |
2232 | ead9360e | ths | { |
2233 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
2234 | 8f6f6026 | ths | FORCE_RET(); |
2235 | ead9360e | ths | } |
2236 | ead9360e | ths | |
2237 | 9c2149c8 | ths | void op_dmfc0_entrylo1 (void) |
2238 | 9c2149c8 | ths | { |
2239 | 9c2149c8 | ths | T0 = env->CP0_EntryLo1; |
2240 | 8f6f6026 | ths | FORCE_RET(); |
2241 | 9c2149c8 | ths | } |
2242 | 9c2149c8 | ths | |
2243 | 9c2149c8 | ths | void op_dmfc0_context (void) |
2244 | 9c2149c8 | ths | { |
2245 | 9c2149c8 | ths | T0 = env->CP0_Context; |
2246 | 8f6f6026 | ths | FORCE_RET(); |
2247 | 9c2149c8 | ths | } |
2248 | 9c2149c8 | ths | |
2249 | 9c2149c8 | ths | void op_dmfc0_badvaddr (void) |
2250 | 9c2149c8 | ths | { |
2251 | 9c2149c8 | ths | T0 = env->CP0_BadVAddr; |
2252 | 8f6f6026 | ths | FORCE_RET(); |
2253 | 9c2149c8 | ths | } |
2254 | 9c2149c8 | ths | |
2255 | 9c2149c8 | ths | void op_dmfc0_entryhi (void) |
2256 | 9c2149c8 | ths | { |
2257 | 9c2149c8 | ths | T0 = env->CP0_EntryHi; |
2258 | 8f6f6026 | ths | FORCE_RET(); |
2259 | 9c2149c8 | ths | } |
2260 | 9c2149c8 | ths | |
2261 | 9c2149c8 | ths | void op_dmfc0_epc (void) |
2262 | 9c2149c8 | ths | { |
2263 | 9c2149c8 | ths | T0 = env->CP0_EPC; |
2264 | 8f6f6026 | ths | FORCE_RET(); |
2265 | 9c2149c8 | ths | } |
2266 | 9c2149c8 | ths | |
2267 | 9c2149c8 | ths | void op_dmfc0_lladdr (void) |
2268 | 9c2149c8 | ths | { |
2269 | 9c2149c8 | ths | T0 = env->CP0_LLAddr >> 4;
|
2270 | 8f6f6026 | ths | FORCE_RET(); |
2271 | 9c2149c8 | ths | } |
2272 | 9c2149c8 | ths | |
2273 | fd88b6ab | ths | void op_dmfc0_watchlo (void) |
2274 | 9c2149c8 | ths | { |
2275 | fd88b6ab | ths | T0 = env->CP0_WatchLo[PARAM1]; |
2276 | 8f6f6026 | ths | FORCE_RET(); |
2277 | 9c2149c8 | ths | } |
2278 | 9c2149c8 | ths | |
2279 | 9c2149c8 | ths | void op_dmfc0_xcontext (void) |
2280 | 9c2149c8 | ths | { |
2281 | 9c2149c8 | ths | T0 = env->CP0_XContext; |
2282 | 8f6f6026 | ths | FORCE_RET(); |
2283 | 9c2149c8 | ths | } |
2284 | 9c2149c8 | ths | |
2285 | 9c2149c8 | ths | void op_dmfc0_depc (void) |
2286 | 9c2149c8 | ths | { |
2287 | 9c2149c8 | ths | T0 = env->CP0_DEPC; |
2288 | 8f6f6026 | ths | FORCE_RET(); |
2289 | 9c2149c8 | ths | } |
2290 | 9c2149c8 | ths | |
2291 | 9c2149c8 | ths | void op_dmfc0_errorepc (void) |
2292 | 9c2149c8 | ths | { |
2293 | 9c2149c8 | ths | T0 = env->CP0_ErrorEPC; |
2294 | 8f6f6026 | ths | FORCE_RET(); |
2295 | 9c2149c8 | ths | } |
2296 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
2297 | 9c2149c8 | ths | |
2298 | ead9360e | ths | /* MIPS MT functions */
|
2299 | ead9360e | ths | void op_mftgpr(void) |
2300 | ead9360e | ths | { |
2301 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2302 | ead9360e | ths | |
2303 | ead9360e | ths | T0 = env->gpr[PARAM1][other_tc]; |
2304 | 8f6f6026 | ths | FORCE_RET(); |
2305 | ead9360e | ths | } |
2306 | ead9360e | ths | |
2307 | ead9360e | ths | void op_mftlo(void) |
2308 | ead9360e | ths | { |
2309 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2310 | ead9360e | ths | |
2311 | ead9360e | ths | T0 = env->LO[PARAM1][other_tc]; |
2312 | 8f6f6026 | ths | FORCE_RET(); |
2313 | ead9360e | ths | } |
2314 | ead9360e | ths | |
2315 | ead9360e | ths | void op_mfthi(void) |
2316 | ead9360e | ths | { |
2317 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2318 | ead9360e | ths | |
2319 | ead9360e | ths | T0 = env->HI[PARAM1][other_tc]; |
2320 | 8f6f6026 | ths | FORCE_RET(); |
2321 | ead9360e | ths | } |
2322 | ead9360e | ths | |
2323 | ead9360e | ths | void op_mftacx(void) |
2324 | ead9360e | ths | { |
2325 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2326 | ead9360e | ths | |
2327 | ead9360e | ths | T0 = env->ACX[PARAM1][other_tc]; |
2328 | 8f6f6026 | ths | FORCE_RET(); |
2329 | ead9360e | ths | } |
2330 | ead9360e | ths | |
2331 | ead9360e | ths | void op_mftdsp(void) |
2332 | ead9360e | ths | { |
2333 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2334 | ead9360e | ths | |
2335 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
2336 | 8f6f6026 | ths | FORCE_RET(); |
2337 | ead9360e | ths | } |
2338 | ead9360e | ths | |
2339 | ead9360e | ths | void op_mttgpr(void) |
2340 | ead9360e | ths | { |
2341 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2342 | ead9360e | ths | |
2343 | ead9360e | ths | T0 = env->gpr[PARAM1][other_tc]; |
2344 | 8f6f6026 | ths | FORCE_RET(); |
2345 | ead9360e | ths | } |
2346 | ead9360e | ths | |
2347 | ead9360e | ths | void op_mttlo(void) |
2348 | ead9360e | ths | { |
2349 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2350 | ead9360e | ths | |
2351 | ead9360e | ths | T0 = env->LO[PARAM1][other_tc]; |
2352 | 8f6f6026 | ths | FORCE_RET(); |
2353 | ead9360e | ths | } |
2354 | ead9360e | ths | |
2355 | ead9360e | ths | void op_mtthi(void) |
2356 | ead9360e | ths | { |
2357 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2358 | ead9360e | ths | |
2359 | ead9360e | ths | T0 = env->HI[PARAM1][other_tc]; |
2360 | 8f6f6026 | ths | FORCE_RET(); |
2361 | ead9360e | ths | } |
2362 | ead9360e | ths | |
2363 | ead9360e | ths | void op_mttacx(void) |
2364 | ead9360e | ths | { |
2365 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2366 | ead9360e | ths | |
2367 | ead9360e | ths | T0 = env->ACX[PARAM1][other_tc]; |
2368 | 8f6f6026 | ths | FORCE_RET(); |
2369 | ead9360e | ths | } |
2370 | ead9360e | ths | |
2371 | ead9360e | ths | void op_mttdsp(void) |
2372 | ead9360e | ths | { |
2373 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2374 | ead9360e | ths | |
2375 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
2376 | 8f6f6026 | ths | FORCE_RET(); |
2377 | ead9360e | ths | } |
2378 | ead9360e | ths | |
2379 | ead9360e | ths | |
2380 | ead9360e | ths | void op_dmt(void) |
2381 | ead9360e | ths | { |
2382 | ead9360e | ths | // TODO
|
2383 | ead9360e | ths | T0 = 0;
|
2384 | ead9360e | ths | // rt = T0
|
2385 | 8f6f6026 | ths | FORCE_RET(); |
2386 | ead9360e | ths | } |
2387 | ead9360e | ths | |
2388 | ead9360e | ths | void op_emt(void) |
2389 | ead9360e | ths | { |
2390 | ead9360e | ths | // TODO
|
2391 | ead9360e | ths | T0 = 0;
|
2392 | ead9360e | ths | // rt = T0
|
2393 | 8f6f6026 | ths | FORCE_RET(); |
2394 | ead9360e | ths | } |
2395 | ead9360e | ths | |
2396 | ead9360e | ths | void op_dvpe(void) |
2397 | ead9360e | ths | { |
2398 | ead9360e | ths | // TODO
|
2399 | ead9360e | ths | T0 = 0;
|
2400 | ead9360e | ths | // rt = T0
|
2401 | 8f6f6026 | ths | FORCE_RET(); |
2402 | ead9360e | ths | } |
2403 | ead9360e | ths | |
2404 | ead9360e | ths | void op_evpe(void) |
2405 | ead9360e | ths | { |
2406 | ead9360e | ths | // TODO
|
2407 | ead9360e | ths | T0 = 0;
|
2408 | ead9360e | ths | // rt = T0
|
2409 | 8f6f6026 | ths | FORCE_RET(); |
2410 | ead9360e | ths | } |
2411 | ead9360e | ths | |
2412 | ead9360e | ths | void op_fork(void) |
2413 | ead9360e | ths | { |
2414 | ead9360e | ths | // T0 = rt, T1 = rs
|
2415 | ead9360e | ths | T0 = 0;
|
2416 | ead9360e | ths | // TODO: store to TC register
|
2417 | 8f6f6026 | ths | FORCE_RET(); |
2418 | ead9360e | ths | } |
2419 | ead9360e | ths | |
2420 | ead9360e | ths | void op_yield(void) |
2421 | ead9360e | ths | { |
2422 | ead9360e | ths | if (T0 < 0) { |
2423 | ead9360e | ths | /* No scheduling policy implemented. */
|
2424 | ead9360e | ths | if (T0 != -2) { |
2425 | ead9360e | ths | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
2426 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
|
2427 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2428 | ead9360e | ths | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
2429 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2430 | ead9360e | ths | } |
2431 | ead9360e | ths | } |
2432 | ead9360e | ths | } else if (T0 == 0) { |
2433 | ead9360e | ths | if (0 /* TODO: TC underflow */) { |
2434 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2435 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2436 | ead9360e | ths | } else {
|
2437 | ead9360e | ths | // TODO: Deallocate TC
|
2438 | ead9360e | ths | } |
2439 | ead9360e | ths | } else if (T0 > 0) { |
2440 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
2441 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2442 | ead9360e | ths | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
2443 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2444 | ead9360e | ths | } |
2445 | ead9360e | ths | T0 = env->CP0_YQMask; |
2446 | 8f6f6026 | ths | FORCE_RET(); |
2447 | ead9360e | ths | } |
2448 | ead9360e | ths | |
2449 | 5a5012ec | ths | /* CP1 functions */
|
2450 | 6ea83fed | bellard | #if 0
|
2451 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
2452 | 6ea83fed | bellard | #else
|
2453 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() do { } while(0) |
2454 | 6ea83fed | bellard | #endif
|
2455 | 6ea83fed | bellard | |
2456 | 5a5012ec | ths | void op_cfc1 (void) |
2457 | 5a5012ec | ths | { |
2458 | ead9360e | ths | CALL_FROM_TB1(do_cfc1, PARAM1); |
2459 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2460 | 8f6f6026 | ths | FORCE_RET(); |
2461 | 5a5012ec | ths | } |
2462 | 5a5012ec | ths | |
2463 | 5a5012ec | ths | void op_ctc1 (void) |
2464 | 5a5012ec | ths | { |
2465 | ead9360e | ths | CALL_FROM_TB1(do_ctc1, PARAM1); |
2466 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2467 | 8f6f6026 | ths | FORCE_RET(); |
2468 | 6ea83fed | bellard | } |
2469 | 6ea83fed | bellard | |
2470 | 6ea83fed | bellard | void op_mfc1 (void) |
2471 | 6ea83fed | bellard | { |
2472 | 6ad38722 | ths | T0 = (int32_t)WT0; |
2473 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2474 | 8f6f6026 | ths | FORCE_RET(); |
2475 | 6ea83fed | bellard | } |
2476 | 6ea83fed | bellard | |
2477 | 6ea83fed | bellard | void op_mtc1 (void) |
2478 | 6ea83fed | bellard | { |
2479 | 6ea83fed | bellard | WT0 = T0; |
2480 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2481 | 8f6f6026 | ths | FORCE_RET(); |
2482 | 6ea83fed | bellard | } |
2483 | 6ea83fed | bellard | |
2484 | 5a5012ec | ths | void op_dmfc1 (void) |
2485 | 5a5012ec | ths | { |
2486 | 5a5012ec | ths | T0 = DT0; |
2487 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2488 | 8f6f6026 | ths | FORCE_RET(); |
2489 | 5a5012ec | ths | } |
2490 | 5a5012ec | ths | |
2491 | 5a5012ec | ths | void op_dmtc1 (void) |
2492 | 5a5012ec | ths | { |
2493 | 5a5012ec | ths | DT0 = T0; |
2494 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2495 | 8f6f6026 | ths | FORCE_RET(); |
2496 | 5a5012ec | ths | } |
2497 | 5a5012ec | ths | |
2498 | 5a5012ec | ths | void op_mfhc1 (void) |
2499 | 5a5012ec | ths | { |
2500 | 6ad38722 | ths | T0 = (int32_t)WTH0; |
2501 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2502 | 8f6f6026 | ths | FORCE_RET(); |
2503 | 5a5012ec | ths | } |
2504 | 5a5012ec | ths | |
2505 | 5a5012ec | ths | void op_mthc1 (void) |
2506 | 5a5012ec | ths | { |
2507 | 5a5012ec | ths | WTH0 = T0; |
2508 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2509 | 8f6f6026 | ths | FORCE_RET(); |
2510 | 5a5012ec | ths | } |
2511 | 5a5012ec | ths | |
2512 | 6ea83fed | bellard | /* Float support.
|
2513 | 6ea83fed | bellard | Single precition routines have a "s" suffix, double precision a
|
2514 | 5a5012ec | ths | "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
|
2515 | 5a5012ec | ths | paired single lowwer "pl", paired single upper "pu". */
|
2516 | 6ea83fed | bellard | |
2517 | 6ea83fed | bellard | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
2518 | 6ea83fed | bellard | |
2519 | dd016883 | bellard | FLOAT_OP(cvtd, s) |
2520 | dd016883 | bellard | { |
2521 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_s); |
2522 | dd016883 | bellard | DEBUG_FPU_STATE(); |
2523 | 8f6f6026 | ths | FORCE_RET(); |
2524 | dd016883 | bellard | } |
2525 | 6ea83fed | bellard | FLOAT_OP(cvtd, w) |
2526 | 6ea83fed | bellard | { |
2527 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_w); |
2528 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2529 | 8f6f6026 | ths | FORCE_RET(); |
2530 | 5a5012ec | ths | } |
2531 | 5a5012ec | ths | FLOAT_OP(cvtd, l) |
2532 | 5a5012ec | ths | { |
2533 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_l); |
2534 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2535 | 8f6f6026 | ths | FORCE_RET(); |
2536 | 5a5012ec | ths | } |
2537 | 5a5012ec | ths | FLOAT_OP(cvtl, d) |
2538 | 5a5012ec | ths | { |
2539 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_d); |
2540 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2541 | 8f6f6026 | ths | FORCE_RET(); |
2542 | 5a5012ec | ths | } |
2543 | 5a5012ec | ths | FLOAT_OP(cvtl, s) |
2544 | 5a5012ec | ths | { |
2545 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_s); |
2546 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2547 | 8f6f6026 | ths | FORCE_RET(); |
2548 | 5a5012ec | ths | } |
2549 | 5a5012ec | ths | FLOAT_OP(cvtps, s) |
2550 | 5a5012ec | ths | { |
2551 | 5a5012ec | ths | WT2 = WT0; |
2552 | 5a5012ec | ths | WTH2 = WT1; |
2553 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2554 | 8f6f6026 | ths | FORCE_RET(); |
2555 | 5a5012ec | ths | } |
2556 | 5a5012ec | ths | FLOAT_OP(cvtps, pw) |
2557 | 5a5012ec | ths | { |
2558 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtps_pw); |
2559 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2560 | 8f6f6026 | ths | FORCE_RET(); |
2561 | 5a5012ec | ths | } |
2562 | 5a5012ec | ths | FLOAT_OP(cvtpw, ps) |
2563 | 5a5012ec | ths | { |
2564 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtpw_ps); |
2565 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2566 | 8f6f6026 | ths | FORCE_RET(); |
2567 | 6ea83fed | bellard | } |
2568 | dd016883 | bellard | FLOAT_OP(cvts, d) |
2569 | dd016883 | bellard | { |
2570 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_d); |
2571 | dd016883 | bellard | DEBUG_FPU_STATE(); |
2572 | 8f6f6026 | ths | FORCE_RET(); |
2573 | dd016883 | bellard | } |
2574 | 6ea83fed | bellard | FLOAT_OP(cvts, w) |
2575 | 6ea83fed | bellard | { |
2576 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_w); |
2577 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2578 | 8f6f6026 | ths | FORCE_RET(); |
2579 | 5a5012ec | ths | } |
2580 | 5a5012ec | ths | FLOAT_OP(cvts, l) |
2581 | 5a5012ec | ths | { |
2582 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_l); |
2583 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2584 | 8f6f6026 | ths | FORCE_RET(); |
2585 | 5a5012ec | ths | } |
2586 | 5a5012ec | ths | FLOAT_OP(cvts, pl) |
2587 | 5a5012ec | ths | { |
2588 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pl); |
2589 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2590 | 8f6f6026 | ths | FORCE_RET(); |
2591 | 5a5012ec | ths | } |
2592 | 5a5012ec | ths | FLOAT_OP(cvts, pu) |
2593 | 5a5012ec | ths | { |
2594 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pu); |
2595 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2596 | 8f6f6026 | ths | FORCE_RET(); |
2597 | 6ea83fed | bellard | } |
2598 | 6ea83fed | bellard | FLOAT_OP(cvtw, s) |
2599 | 6ea83fed | bellard | { |
2600 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_s); |
2601 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2602 | 8f6f6026 | ths | FORCE_RET(); |
2603 | 6ea83fed | bellard | } |
2604 | 6ea83fed | bellard | FLOAT_OP(cvtw, d) |
2605 | 6ea83fed | bellard | { |
2606 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_d); |
2607 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2608 | 8f6f6026 | ths | FORCE_RET(); |
2609 | 5a5012ec | ths | } |
2610 | 5a5012ec | ths | |
2611 | 5a5012ec | ths | FLOAT_OP(pll, ps) |
2612 | 5a5012ec | ths | { |
2613 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WT1;
|
2614 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2615 | 8f6f6026 | ths | FORCE_RET(); |
2616 | 5a5012ec | ths | } |
2617 | 5a5012ec | ths | FLOAT_OP(plu, ps) |
2618 | 5a5012ec | ths | { |
2619 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WTH1;
|
2620 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2621 | 8f6f6026 | ths | FORCE_RET(); |
2622 | 5a5012ec | ths | } |
2623 | 5a5012ec | ths | FLOAT_OP(pul, ps) |
2624 | 5a5012ec | ths | { |
2625 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WT1;
|
2626 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2627 | 8f6f6026 | ths | FORCE_RET(); |
2628 | 5a5012ec | ths | } |
2629 | 5a5012ec | ths | FLOAT_OP(puu, ps) |
2630 | 5a5012ec | ths | { |
2631 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WTH1;
|
2632 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2633 | 8f6f6026 | ths | FORCE_RET(); |
2634 | 6ea83fed | bellard | } |
2635 | 6ea83fed | bellard | |
2636 | fd4a04eb | ths | #define FLOAT_ROUNDOP(op, ttype, stype) \
|
2637 | fd4a04eb | ths | FLOAT_OP(op ## ttype, stype) \ |
2638 | fd4a04eb | ths | { \ |
2639 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \ |
2640 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2641 | 8f6f6026 | ths | FORCE_RET(); \ |
2642 | 6ea83fed | bellard | } |
2643 | 6ea83fed | bellard | |
2644 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, d) |
2645 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, s) |
2646 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, d) |
2647 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, s) |
2648 | 6ea83fed | bellard | |
2649 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, d) |
2650 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, s) |
2651 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, d) |
2652 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, s) |
2653 | 6ea83fed | bellard | |
2654 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, d) |
2655 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, s) |
2656 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, d) |
2657 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, s) |
2658 | fd4a04eb | ths | |
2659 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, d) |
2660 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, s) |
2661 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, d) |
2662 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, s) |
2663 | fd4a04eb | ths | #undef FLOAR_ROUNDOP
|
2664 | 6ea83fed | bellard | |
2665 | 5a5012ec | ths | FLOAT_OP(movf, d) |
2666 | 5a5012ec | ths | { |
2667 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
2668 | 5a5012ec | ths | DT2 = DT0; |
2669 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2670 | 8f6f6026 | ths | FORCE_RET(); |
2671 | 5a5012ec | ths | } |
2672 | 5a5012ec | ths | FLOAT_OP(movf, s) |
2673 | 5a5012ec | ths | { |
2674 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
2675 | 5a5012ec | ths | WT2 = WT0; |
2676 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2677 | 8f6f6026 | ths | FORCE_RET(); |
2678 | 5a5012ec | ths | } |
2679 | 5a5012ec | ths | FLOAT_OP(movf, ps) |
2680 | 5a5012ec | ths | { |
2681 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1)) {
|
2682 | 5a5012ec | ths | WT2 = WT0; |
2683 | 5a5012ec | ths | WTH2 = WTH0; |
2684 | 5a5012ec | ths | } |
2685 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2686 | 8f6f6026 | ths | FORCE_RET(); |
2687 | 5a5012ec | ths | } |
2688 | 5a5012ec | ths | FLOAT_OP(movt, d) |
2689 | 5a5012ec | ths | { |
2690 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
2691 | 5a5012ec | ths | DT2 = DT0; |
2692 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2693 | 8f6f6026 | ths | FORCE_RET(); |
2694 | 5a5012ec | ths | } |
2695 | 5a5012ec | ths | FLOAT_OP(movt, s) |
2696 | 5a5012ec | ths | { |
2697 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
2698 | 5a5012ec | ths | WT2 = WT0; |
2699 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2700 | 8f6f6026 | ths | FORCE_RET(); |
2701 | 5a5012ec | ths | } |
2702 | 5a5012ec | ths | FLOAT_OP(movt, ps) |
2703 | 5a5012ec | ths | { |
2704 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1) {
|
2705 | 5a5012ec | ths | WT2 = WT0; |
2706 | 5a5012ec | ths | WTH2 = WTH0; |
2707 | 5a5012ec | ths | } |
2708 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2709 | 8f6f6026 | ths | FORCE_RET(); |
2710 | 5a5012ec | ths | } |
2711 | 5a5012ec | ths | FLOAT_OP(movz, d) |
2712 | 5a5012ec | ths | { |
2713 | 5a5012ec | ths | if (!T0)
|
2714 | 5a5012ec | ths | DT2 = DT0; |
2715 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2716 | 8f6f6026 | ths | FORCE_RET(); |
2717 | 5a5012ec | ths | } |
2718 | 5a5012ec | ths | FLOAT_OP(movz, s) |
2719 | 5a5012ec | ths | { |
2720 | 5a5012ec | ths | if (!T0)
|
2721 | 5a5012ec | ths | WT2 = WT0; |
2722 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2723 | 8f6f6026 | ths | FORCE_RET(); |
2724 | 5a5012ec | ths | } |
2725 | 5a5012ec | ths | FLOAT_OP(movz, ps) |
2726 | 5a5012ec | ths | { |
2727 | 5a5012ec | ths | if (!T0) {
|
2728 | 5a5012ec | ths | WT2 = WT0; |
2729 | 5a5012ec | ths | WTH2 = WTH0; |
2730 | 5a5012ec | ths | } |
2731 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2732 | 8f6f6026 | ths | FORCE_RET(); |
2733 | 5a5012ec | ths | } |
2734 | 5a5012ec | ths | FLOAT_OP(movn, d) |
2735 | 5a5012ec | ths | { |
2736 | 5a5012ec | ths | if (T0)
|
2737 | 5a5012ec | ths | DT2 = DT0; |
2738 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2739 | 8f6f6026 | ths | FORCE_RET(); |
2740 | 5a5012ec | ths | } |
2741 | 5a5012ec | ths | FLOAT_OP(movn, s) |
2742 | 5a5012ec | ths | { |
2743 | 5a5012ec | ths | if (T0)
|
2744 | 5a5012ec | ths | WT2 = WT0; |
2745 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2746 | 8f6f6026 | ths | FORCE_RET(); |
2747 | 5a5012ec | ths | } |
2748 | 5a5012ec | ths | FLOAT_OP(movn, ps) |
2749 | 5a5012ec | ths | { |
2750 | 5a5012ec | ths | if (T0) {
|
2751 | 5a5012ec | ths | WT2 = WT0; |
2752 | 5a5012ec | ths | WTH2 = WTH0; |
2753 | 5a5012ec | ths | } |
2754 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2755 | 8f6f6026 | ths | FORCE_RET(); |
2756 | 5a5012ec | ths | } |
2757 | 5a5012ec | ths | |
2758 | 57fa1fb3 | ths | /* operations calling helpers, for s, d and ps */
|
2759 | 8f6f6026 | ths | #define FLOAT_HOP(name) \
|
2760 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2761 | 6ea83fed | bellard | { \ |
2762 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
2763 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2764 | 8f6f6026 | ths | FORCE_RET(); \ |
2765 | 6ea83fed | bellard | } \ |
2766 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2767 | 6ea83fed | bellard | { \ |
2768 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
2769 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2770 | 8f6f6026 | ths | FORCE_RET(); \ |
2771 | 5a5012ec | ths | } \ |
2772 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2773 | 5a5012ec | ths | { \ |
2774 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
2775 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2776 | 8f6f6026 | ths | FORCE_RET(); \ |
2777 | 6ea83fed | bellard | } |
2778 | 57fa1fb3 | ths | FLOAT_HOP(add) |
2779 | 57fa1fb3 | ths | FLOAT_HOP(sub) |
2780 | 57fa1fb3 | ths | FLOAT_HOP(mul) |
2781 | 57fa1fb3 | ths | FLOAT_HOP(div) |
2782 | 57fa1fb3 | ths | FLOAT_HOP(recip2) |
2783 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt2) |
2784 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt1) |
2785 | 57fa1fb3 | ths | FLOAT_HOP(recip1) |
2786 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2787 | 57fa1fb3 | ths | |
2788 | 57fa1fb3 | ths | /* operations calling helpers, for s and d */
|
2789 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
2790 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
2791 | 57fa1fb3 | ths | { \ |
2792 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
2793 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2794 | 8f6f6026 | ths | FORCE_RET(); \ |
2795 | 57fa1fb3 | ths | } \ |
2796 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
2797 | 57fa1fb3 | ths | { \ |
2798 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
2799 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2800 | 8f6f6026 | ths | FORCE_RET(); \ |
2801 | 57fa1fb3 | ths | } |
2802 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt) |
2803 | 57fa1fb3 | ths | FLOAT_HOP(recip) |
2804 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2805 | 6ea83fed | bellard | |
2806 | 57fa1fb3 | ths | /* operations calling helpers, for ps */
|
2807 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
2808 | 57fa1fb3 | ths | FLOAT_OP(name, ps) \ |
2809 | 57fa1fb3 | ths | { \ |
2810 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
2811 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2812 | 8f6f6026 | ths | FORCE_RET(); \ |
2813 | fbcc6828 | ths | } |
2814 | 57fa1fb3 | ths | FLOAT_HOP(addr) |
2815 | 57fa1fb3 | ths | FLOAT_HOP(mulr) |
2816 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2817 | fbcc6828 | ths | |
2818 | 5a5012ec | ths | /* ternary operations */
|
2819 | 5a5012ec | ths | #define FLOAT_TERNOP(name1, name2) \
|
2820 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, d) \ |
2821 | 5a5012ec | ths | { \ |
2822 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
2823 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
2824 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2825 | 8f6f6026 | ths | FORCE_RET(); \ |
2826 | 5a5012ec | ths | } \ |
2827 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, s) \ |
2828 | 5a5012ec | ths | { \ |
2829 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2830 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2831 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2832 | 8f6f6026 | ths | FORCE_RET(); \ |
2833 | 5a5012ec | ths | } \ |
2834 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, ps) \ |
2835 | 5a5012ec | ths | { \ |
2836 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2837 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
2838 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2839 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
2840 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2841 | 8f6f6026 | ths | FORCE_RET(); \ |
2842 | 5a5012ec | ths | } |
2843 | 5a5012ec | ths | FLOAT_TERNOP(mul, add) |
2844 | 5a5012ec | ths | FLOAT_TERNOP(mul, sub) |
2845 | 5a5012ec | ths | #undef FLOAT_TERNOP
|
2846 | 5a5012ec | ths | |
2847 | fbcc6828 | ths | /* negated ternary operations */
|
2848 | fbcc6828 | ths | #define FLOAT_NTERNOP(name1, name2) \
|
2849 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, d) \ |
2850 | fbcc6828 | ths | { \ |
2851 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
2852 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
2853 | 5747c073 | pbrook | FDT2 = float64_chs(FDT2); \ |
2854 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2855 | 8f6f6026 | ths | FORCE_RET(); \ |
2856 | fbcc6828 | ths | } \ |
2857 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, s) \ |
2858 | fbcc6828 | ths | { \ |
2859 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2860 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2861 | 5747c073 | pbrook | FST2 = float32_chs(FST2); \ |
2862 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2863 | 8f6f6026 | ths | FORCE_RET(); \ |
2864 | fbcc6828 | ths | } \ |
2865 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, ps) \ |
2866 | fbcc6828 | ths | { \ |
2867 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2868 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
2869 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2870 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
2871 | 5747c073 | pbrook | FST2 = float32_chs(FST2); \ |
2872 | 5747c073 | pbrook | FSTH2 = float32_chs(FSTH2); \ |
2873 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2874 | 8f6f6026 | ths | FORCE_RET(); \ |
2875 | fbcc6828 | ths | } |
2876 | fbcc6828 | ths | FLOAT_NTERNOP(mul, add) |
2877 | fbcc6828 | ths | FLOAT_NTERNOP(mul, sub) |
2878 | fbcc6828 | ths | #undef FLOAT_NTERNOP
|
2879 | fbcc6828 | ths | |
2880 | 6ea83fed | bellard | /* unary operations, modifying fp status */
|
2881 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2882 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2883 | 6ea83fed | bellard | { \ |
2884 | 8f6f6026 | ths | FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \ |
2885 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2886 | 8f6f6026 | ths | FORCE_RET(); \ |
2887 | 6ea83fed | bellard | } \ |
2888 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2889 | 6ea83fed | bellard | { \ |
2890 | 8f6f6026 | ths | FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \ |
2891 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2892 | 8f6f6026 | ths | FORCE_RET(); \ |
2893 | 6ea83fed | bellard | } |
2894 | 6ea83fed | bellard | FLOAT_UNOP(sqrt) |
2895 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2896 | 6ea83fed | bellard | |
2897 | 6ea83fed | bellard | /* unary operations, not modifying fp status */
|
2898 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2899 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2900 | 6ea83fed | bellard | { \ |
2901 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0); \ |
2902 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2903 | 8f6f6026 | ths | FORCE_RET(); \ |
2904 | 6ea83fed | bellard | } \ |
2905 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2906 | 6ea83fed | bellard | { \ |
2907 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0); \ |
2908 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2909 | 8f6f6026 | ths | FORCE_RET(); \ |
2910 | 5a5012ec | ths | } \ |
2911 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2912 | 5a5012ec | ths | { \ |
2913 | 5a5012ec | ths | FST2 = float32_ ## name(FST0); \ |
2914 | 5a5012ec | ths | FSTH2 = float32_ ## name(FSTH0); \ |
2915 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2916 | 8f6f6026 | ths | FORCE_RET(); \ |
2917 | 6ea83fed | bellard | } |
2918 | 6ea83fed | bellard | FLOAT_UNOP(abs) |
2919 | 6ea83fed | bellard | FLOAT_UNOP(chs) |
2920 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2921 | 6ea83fed | bellard | |
2922 | 6ea83fed | bellard | FLOAT_OP(mov, d) |
2923 | 6ea83fed | bellard | { |
2924 | 6ea83fed | bellard | FDT2 = FDT0; |
2925 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2926 | 8f6f6026 | ths | FORCE_RET(); |
2927 | 6ea83fed | bellard | } |
2928 | 6ea83fed | bellard | FLOAT_OP(mov, s) |
2929 | 6ea83fed | bellard | { |
2930 | 6ea83fed | bellard | FST2 = FST0; |
2931 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2932 | 8f6f6026 | ths | FORCE_RET(); |
2933 | 6ea83fed | bellard | } |
2934 | 5a5012ec | ths | FLOAT_OP(mov, ps) |
2935 | 5a5012ec | ths | { |
2936 | 5a5012ec | ths | FST2 = FST0; |
2937 | 5a5012ec | ths | FSTH2 = FSTH0; |
2938 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2939 | 8f6f6026 | ths | FORCE_RET(); |
2940 | 5a5012ec | ths | } |
2941 | 5a5012ec | ths | FLOAT_OP(alnv, ps) |
2942 | 5a5012ec | ths | { |
2943 | 5a5012ec | ths | switch (T0 & 0x7) { |
2944 | 5a5012ec | ths | case 0: |
2945 | 5a5012ec | ths | FST2 = FST0; |
2946 | 5a5012ec | ths | FSTH2 = FSTH0; |
2947 | 5a5012ec | ths | break;
|
2948 | 5a5012ec | ths | case 4: |
2949 | 5a5012ec | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
2950 | 5a5012ec | ths | FSTH2 = FST0; |
2951 | 5a5012ec | ths | FST2 = FSTH1; |
2952 | 5a5012ec | ths | #else
|
2953 | 5a5012ec | ths | FSTH2 = FST1; |
2954 | 5a5012ec | ths | FST2 = FSTH0; |
2955 | 5a5012ec | ths | #endif
|
2956 | 5a5012ec | ths | break;
|
2957 | 5a5012ec | ths | default: /* unpredictable */ |
2958 | 5a5012ec | ths | break;
|
2959 | 5a5012ec | ths | } |
2960 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2961 | 8f6f6026 | ths | FORCE_RET(); |
2962 | 5a5012ec | ths | } |
2963 | 6ea83fed | bellard | |
2964 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
2965 | 6ea83fed | bellard | #define clear_invalid() do { \ |
2966 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status); \
|
2967 | 6ea83fed | bellard | flags &= ~float_flag_invalid; \ |
2968 | 8f6f6026 | ths | set_float_exception_flags(flags, &env->fpu->fp_status); \ |
2969 | 6ea83fed | bellard | } while(0) |
2970 | 6ea83fed | bellard | #else
|
2971 | 6ea83fed | bellard | #define clear_invalid() do { } while(0) |
2972 | 6ea83fed | bellard | #endif
|
2973 | 6ea83fed | bellard | |
2974 | 6ea83fed | bellard | extern void dump_fpu_s(CPUState *env); |
2975 | 6ea83fed | bellard | |
2976 | fd4a04eb | ths | #define CMP_OP(fmt, op) \
|
2977 | fd4a04eb | ths | void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \ |
2978 | fd4a04eb | ths | { \ |
2979 | fd4a04eb | ths | CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \ |
2980 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2981 | 8f6f6026 | ths | FORCE_RET(); \ |
2982 | fd4a04eb | ths | } \ |
2983 | fd4a04eb | ths | void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \ |
2984 | fd4a04eb | ths | { \ |
2985 | fd4a04eb | ths | CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \ |
2986 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2987 | 8f6f6026 | ths | FORCE_RET(); \ |
2988 | fd4a04eb | ths | } |
2989 | fd4a04eb | ths | #define CMP_OPS(op) \
|
2990 | fd4a04eb | ths | CMP_OP(d, op) \ |
2991 | fd4a04eb | ths | CMP_OP(s, op) \ |
2992 | fd4a04eb | ths | CMP_OP(ps, op) |
2993 | fd4a04eb | ths | |
2994 | fd4a04eb | ths | CMP_OPS(f) |
2995 | fd4a04eb | ths | CMP_OPS(un) |
2996 | fd4a04eb | ths | CMP_OPS(eq) |
2997 | fd4a04eb | ths | CMP_OPS(ueq) |
2998 | fd4a04eb | ths | CMP_OPS(olt) |
2999 | fd4a04eb | ths | CMP_OPS(ult) |
3000 | fd4a04eb | ths | CMP_OPS(ole) |
3001 | fd4a04eb | ths | CMP_OPS(ule) |
3002 | fd4a04eb | ths | CMP_OPS(sf) |
3003 | fd4a04eb | ths | CMP_OPS(ngle) |
3004 | fd4a04eb | ths | CMP_OPS(seq) |
3005 | fd4a04eb | ths | CMP_OPS(ngl) |
3006 | fd4a04eb | ths | CMP_OPS(lt) |
3007 | fd4a04eb | ths | CMP_OPS(nge) |
3008 | fd4a04eb | ths | CMP_OPS(le) |
3009 | fd4a04eb | ths | CMP_OPS(ngt) |
3010 | fd4a04eb | ths | #undef CMP_OPS
|
3011 | fd4a04eb | ths | #undef CMP_OP
|
3012 | 6ea83fed | bellard | |
3013 | 6ea83fed | bellard | void op_bc1f (void) |
3014 | 6ea83fed | bellard | { |
3015 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
3016 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
3017 | 8f6f6026 | ths | FORCE_RET(); |
3018 | 5a5012ec | ths | } |
3019 | fd4a04eb | ths | void op_bc1any2f (void) |
3020 | 5a5012ec | ths | { |
3021 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
3022 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
3023 | 8f6f6026 | ths | FORCE_RET(); |
3024 | 5a5012ec | ths | } |
3025 | fd4a04eb | ths | void op_bc1any4f (void) |
3026 | 5a5012ec | ths | { |
3027 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
3028 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
3029 | 8f6f6026 | ths | FORCE_RET(); |
3030 | 6ea83fed | bellard | } |
3031 | 6ea83fed | bellard | |
3032 | 6ea83fed | bellard | void op_bc1t (void) |
3033 | 6ea83fed | bellard | { |
3034 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
3035 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
3036 | 8f6f6026 | ths | FORCE_RET(); |
3037 | 5a5012ec | ths | } |
3038 | fd4a04eb | ths | void op_bc1any2t (void) |
3039 | 5a5012ec | ths | { |
3040 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
3041 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
3042 | 8f6f6026 | ths | FORCE_RET(); |
3043 | 5a5012ec | ths | } |
3044 | fd4a04eb | ths | void op_bc1any4t (void) |
3045 | 5a5012ec | ths | { |
3046 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
3047 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
3048 | 8f6f6026 | ths | FORCE_RET(); |
3049 | 6ea83fed | bellard | } |
3050 | 6ea83fed | bellard | |
3051 | 6af0bf9c | bellard | void op_tlbwi (void) |
3052 | 6af0bf9c | bellard | { |
3053 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwi); |
3054 | 8f6f6026 | ths | FORCE_RET(); |
3055 | 6af0bf9c | bellard | } |
3056 | 6af0bf9c | bellard | |
3057 | 6af0bf9c | bellard | void op_tlbwr (void) |
3058 | 6af0bf9c | bellard | { |
3059 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwr); |
3060 | 8f6f6026 | ths | FORCE_RET(); |
3061 | 6af0bf9c | bellard | } |
3062 | 6af0bf9c | bellard | |
3063 | 6af0bf9c | bellard | void op_tlbp (void) |
3064 | 6af0bf9c | bellard | { |
3065 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbp); |
3066 | 8f6f6026 | ths | FORCE_RET(); |
3067 | 6af0bf9c | bellard | } |
3068 | 6af0bf9c | bellard | |
3069 | 6af0bf9c | bellard | void op_tlbr (void) |
3070 | 6af0bf9c | bellard | { |
3071 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbr); |
3072 | 8f6f6026 | ths | FORCE_RET(); |
3073 | 6af0bf9c | bellard | } |
3074 | 6af0bf9c | bellard | |
3075 | 6af0bf9c | bellard | /* Specials */
|
3076 | 6f5b89a0 | ths | #if defined (CONFIG_USER_ONLY)
|
3077 | 6f5b89a0 | ths | void op_tls_value (void) |
3078 | 6f5b89a0 | ths | { |
3079 | 5a5012ec | ths | T0 = env->tls_value; |
3080 | 6f5b89a0 | ths | } |
3081 | 6f5b89a0 | ths | #endif
|
3082 | 6f5b89a0 | ths | |
3083 | 6af0bf9c | bellard | void op_pmon (void) |
3084 | 6af0bf9c | bellard | { |
3085 | 6af0bf9c | bellard | CALL_FROM_TB1(do_pmon, PARAM1); |
3086 | 8f6f6026 | ths | FORCE_RET(); |
3087 | 7a387fff | ths | } |
3088 | 7a387fff | ths | |
3089 | 7a387fff | ths | void op_di (void) |
3090 | 7a387fff | ths | { |
3091 | 7a387fff | ths | T0 = env->CP0_Status; |
3092 | 4de9b249 | ths | env->CP0_Status = T0 & ~(1 << CP0St_IE);
|
3093 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
3094 | 8f6f6026 | ths | FORCE_RET(); |
3095 | 7a387fff | ths | } |
3096 | 7a387fff | ths | |
3097 | 7a387fff | ths | void op_ei (void) |
3098 | 7a387fff | ths | { |
3099 | 7a387fff | ths | T0 = env->CP0_Status; |
3100 | 4de9b249 | ths | env->CP0_Status = T0 | (1 << CP0St_IE);
|
3101 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
3102 | 8f6f6026 | ths | FORCE_RET(); |
3103 | 6af0bf9c | bellard | } |
3104 | 6af0bf9c | bellard | |
3105 | 6af0bf9c | bellard | void op_trap (void) |
3106 | 6af0bf9c | bellard | { |
3107 | 6af0bf9c | bellard | if (T0) {
|
3108 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
3109 | 6af0bf9c | bellard | } |
3110 | 8f6f6026 | ths | FORCE_RET(); |
3111 | 6af0bf9c | bellard | } |
3112 | 6af0bf9c | bellard | |
3113 | 4ad40f36 | bellard | void op_debug (void) |
3114 | 4ad40f36 | bellard | { |
3115 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
3116 | 8f6f6026 | ths | FORCE_RET(); |
3117 | 4ad40f36 | bellard | } |
3118 | 4ad40f36 | bellard | |
3119 | 6af0bf9c | bellard | void op_set_lladdr (void) |
3120 | 6af0bf9c | bellard | { |
3121 | 6af0bf9c | bellard | env->CP0_LLAddr = T2; |
3122 | 8f6f6026 | ths | FORCE_RET(); |
3123 | 6af0bf9c | bellard | } |
3124 | 6af0bf9c | bellard | |
3125 | f41c52f1 | ths | void debug_pre_eret (void); |
3126 | f41c52f1 | ths | void debug_post_eret (void); |
3127 | 6af0bf9c | bellard | void op_eret (void) |
3128 | 6af0bf9c | bellard | { |
3129 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3130 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
3131 | 24c7b0e3 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
3132 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_ErrorEPC; |
3133 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_ERL);
|
3134 | 51e11d9e | bellard | } else {
|
3135 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_EPC; |
3136 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_EXL);
|
3137 | 51e11d9e | bellard | } |
3138 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
3139 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3140 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
3141 | 6af0bf9c | bellard | env->CP0_LLAddr = 1;
|
3142 | 8f6f6026 | ths | FORCE_RET(); |
3143 | 6af0bf9c | bellard | } |
3144 | 6af0bf9c | bellard | |
3145 | 6af0bf9c | bellard | void op_deret (void) |
3146 | 6af0bf9c | bellard | { |
3147 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3148 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
3149 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_DEPC; |
3150 | 08fa4bab | ths | env->hflags &= MIPS_HFLAG_DM; |
3151 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
3152 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3153 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
3154 | 24c7b0e3 | ths | env->CP0_LLAddr = 1;
|
3155 | 8f6f6026 | ths | FORCE_RET(); |
3156 | 7a387fff | ths | } |
3157 | 7a387fff | ths | |
3158 | 7a387fff | ths | void op_rdhwr_cpunum(void) |
3159 | 7a387fff | ths | { |
3160 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
3161 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 0))) |
3162 | 1579a72e | ths | T0 = env->CP0_EBase & 0x3ff;
|
3163 | 7a387fff | ths | else
|
3164 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3165 | 8f6f6026 | ths | FORCE_RET(); |
3166 | 7a387fff | ths | } |
3167 | 7a387fff | ths | |
3168 | 7a387fff | ths | void op_rdhwr_synci_step(void) |
3169 | 7a387fff | ths | { |
3170 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
3171 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 1))) |
3172 | 1579a72e | ths | T0 = env->SYNCI_Step; |
3173 | 7a387fff | ths | else
|
3174 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3175 | 8f6f6026 | ths | FORCE_RET(); |
3176 | 7a387fff | ths | } |
3177 | 7a387fff | ths | |
3178 | 7a387fff | ths | void op_rdhwr_cc(void) |
3179 | 7a387fff | ths | { |
3180 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
3181 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 2))) |
3182 | 1579a72e | ths | T0 = env->CP0_Count; |
3183 | 7a387fff | ths | else
|
3184 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3185 | 8f6f6026 | ths | FORCE_RET(); |
3186 | 7a387fff | ths | } |
3187 | 7a387fff | ths | |
3188 | 7a387fff | ths | void op_rdhwr_ccres(void) |
3189 | 7a387fff | ths | { |
3190 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
3191 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 3))) |
3192 | 1579a72e | ths | T0 = env->CCRes; |
3193 | 7a387fff | ths | else
|
3194 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3195 | 8f6f6026 | ths | FORCE_RET(); |
3196 | 1579a72e | ths | } |
3197 | 1579a72e | ths | |
3198 | 6af0bf9c | bellard | void op_save_state (void) |
3199 | 6af0bf9c | bellard | { |
3200 | 6af0bf9c | bellard | env->hflags = PARAM1; |
3201 | 8f6f6026 | ths | FORCE_RET(); |
3202 | 6af0bf9c | bellard | } |
3203 | 6af0bf9c | bellard | |
3204 | 6af0bf9c | bellard | void op_save_pc (void) |
3205 | 6af0bf9c | bellard | { |
3206 | ead9360e | ths | env->PC[env->current_tc] = PARAM1; |
3207 | 8f6f6026 | ths | FORCE_RET(); |
3208 | 6af0bf9c | bellard | } |
3209 | 6af0bf9c | bellard | |
3210 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
3211 | 9b9e4393 | ths | void op_save_pc64 (void) |
3212 | 9b9e4393 | ths | { |
3213 | ead9360e | ths | env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
3214 | 8f6f6026 | ths | FORCE_RET(); |
3215 | 9b9e4393 | ths | } |
3216 | 9b9e4393 | ths | #endif
|
3217 | 9b9e4393 | ths | |
3218 | 16c00cb2 | ths | void op_interrupt_restart (void) |
3219 | 16c00cb2 | ths | { |
3220 | 16c00cb2 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
3221 | 16c00cb2 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
3222 | 16c00cb2 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
3223 | 16c00cb2 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
|
3224 | 16c00cb2 | ths | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
3225 | 16c00cb2 | ths | env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
|
3226 | 16c00cb2 | ths | CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); |
3227 | 16c00cb2 | ths | } |
3228 | 8f6f6026 | ths | FORCE_RET(); |
3229 | 16c00cb2 | ths | } |
3230 | 16c00cb2 | ths | |
3231 | 6af0bf9c | bellard | void op_raise_exception (void) |
3232 | 6af0bf9c | bellard | { |
3233 | 6af0bf9c | bellard | CALL_FROM_TB1(do_raise_exception, PARAM1); |
3234 | 8f6f6026 | ths | FORCE_RET(); |
3235 | 6af0bf9c | bellard | } |
3236 | 6af0bf9c | bellard | |
3237 | 6af0bf9c | bellard | void op_raise_exception_err (void) |
3238 | 6af0bf9c | bellard | { |
3239 | 6af0bf9c | bellard | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
3240 | 8f6f6026 | ths | FORCE_RET(); |
3241 | 6af0bf9c | bellard | } |
3242 | 6af0bf9c | bellard | |
3243 | 4ad40f36 | bellard | void op_wait (void) |
3244 | 4ad40f36 | bellard | { |
3245 | 4ad40f36 | bellard | env->halted = 1;
|
3246 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
3247 | 8f6f6026 | ths | FORCE_RET(); |
3248 | 7a387fff | ths | } |
3249 | 7a387fff | ths | |
3250 | 7a387fff | ths | /* Bitfield operations. */
|
3251 | 7a387fff | ths | void op_ext(void) |
3252 | 7a387fff | ths | { |
3253 | 7a387fff | ths | unsigned int pos = PARAM1; |
3254 | 7a387fff | ths | unsigned int size = PARAM2; |
3255 | 7a387fff | ths | |
3256 | c6d6dd7c | ths | T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0)); |
3257 | 8f6f6026 | ths | FORCE_RET(); |
3258 | 7a387fff | ths | } |
3259 | 7a387fff | ths | |
3260 | 7a387fff | ths | void op_ins(void) |
3261 | 7a387fff | ths | { |
3262 | 7a387fff | ths | unsigned int pos = PARAM1; |
3263 | 7a387fff | ths | unsigned int size = PARAM2; |
3264 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
3265 | 7a387fff | ths | |
3266 | c6d6dd7c | ths | T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask)); |
3267 | 8f6f6026 | ths | FORCE_RET(); |
3268 | 7a387fff | ths | } |
3269 | 7a387fff | ths | |
3270 | 7a387fff | ths | void op_wsbh(void) |
3271 | 7a387fff | ths | { |
3272 | c6d6dd7c | ths | T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF)); |
3273 | 8f6f6026 | ths | FORCE_RET(); |
3274 | 7a387fff | ths | } |
3275 | 7a387fff | ths | |
3276 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
3277 | c570fd16 | ths | void op_dext(void) |
3278 | c570fd16 | ths | { |
3279 | c570fd16 | ths | unsigned int pos = PARAM1; |
3280 | c570fd16 | ths | unsigned int size = PARAM2; |
3281 | c570fd16 | ths | |
3282 | c6d6dd7c | ths | T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL); |
3283 | 8f6f6026 | ths | FORCE_RET(); |
3284 | c570fd16 | ths | } |
3285 | c570fd16 | ths | |
3286 | c570fd16 | ths | void op_dins(void) |
3287 | c570fd16 | ths | { |
3288 | c570fd16 | ths | unsigned int pos = PARAM1; |
3289 | c570fd16 | ths | unsigned int size = PARAM2; |
3290 | c6d6dd7c | ths | target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos; |
3291 | c570fd16 | ths | |
3292 | 171b31e7 | ths | T0 = (T0 & ~mask) | ((T1 << pos) & mask); |
3293 | 8f6f6026 | ths | FORCE_RET(); |
3294 | c570fd16 | ths | } |
3295 | c570fd16 | ths | |
3296 | 7a387fff | ths | void op_dsbh(void) |
3297 | 7a387fff | ths | { |
3298 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
3299 | 8f6f6026 | ths | FORCE_RET(); |
3300 | 7a387fff | ths | } |
3301 | 7a387fff | ths | |
3302 | 7a387fff | ths | void op_dshd(void) |
3303 | 7a387fff | ths | { |
3304 | c6d6dd7c | ths | T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
3305 | c6d6dd7c | ths | T0 = (T1 << 32) | (T1 >> 32); |
3306 | 8f6f6026 | ths | FORCE_RET(); |
3307 | 7a387fff | ths | } |
3308 | c570fd16 | ths | #endif
|
3309 | 7a387fff | ths | |
3310 | 7a387fff | ths | void op_seb(void) |
3311 | 7a387fff | ths | { |
3312 | 7a387fff | ths | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
3313 | 8f6f6026 | ths | FORCE_RET(); |
3314 | 7a387fff | ths | } |
3315 | 7a387fff | ths | |
3316 | 7a387fff | ths | void op_seh(void) |
3317 | 7a387fff | ths | { |
3318 | 7a387fff | ths | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
3319 | 8f6f6026 | ths | FORCE_RET(); |
3320 | 4ad40f36 | bellard | } |