root / tcg / sparc / tcg-target.c @ 583d1215
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1 | 8289b279 | blueswir1 | /*
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2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
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3 | 8289b279 | blueswir1 | *
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4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
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5 | 8289b279 | blueswir1 | *
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6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 8289b279 | blueswir1 | *
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13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
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15 | 8289b279 | blueswir1 | *
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16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8289b279 | blueswir1 | * THE SOFTWARE.
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23 | 8289b279 | blueswir1 | */
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24 | 8289b279 | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
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26 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | 8289b279 | blueswir1 | "%g0",
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28 | 8289b279 | blueswir1 | "%g1",
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29 | 8289b279 | blueswir1 | "%g2",
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30 | 8289b279 | blueswir1 | "%g3",
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31 | 8289b279 | blueswir1 | "%g4",
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32 | 8289b279 | blueswir1 | "%g5",
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33 | 8289b279 | blueswir1 | "%g6",
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34 | 8289b279 | blueswir1 | "%g7",
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35 | 8289b279 | blueswir1 | "%o0",
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36 | 8289b279 | blueswir1 | "%o1",
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37 | 8289b279 | blueswir1 | "%o2",
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38 | 8289b279 | blueswir1 | "%o3",
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39 | 8289b279 | blueswir1 | "%o4",
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40 | 8289b279 | blueswir1 | "%o5",
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41 | 8289b279 | blueswir1 | "%o6",
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42 | 8289b279 | blueswir1 | "%o7",
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43 | 8289b279 | blueswir1 | "%l0",
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44 | 8289b279 | blueswir1 | "%l1",
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45 | 8289b279 | blueswir1 | "%l2",
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46 | 8289b279 | blueswir1 | "%l3",
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47 | 8289b279 | blueswir1 | "%l4",
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48 | 8289b279 | blueswir1 | "%l5",
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49 | 8289b279 | blueswir1 | "%l6",
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50 | 8289b279 | blueswir1 | "%l7",
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51 | 8289b279 | blueswir1 | "%i0",
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52 | 8289b279 | blueswir1 | "%i1",
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53 | 8289b279 | blueswir1 | "%i2",
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54 | 8289b279 | blueswir1 | "%i3",
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55 | 8289b279 | blueswir1 | "%i4",
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56 | 8289b279 | blueswir1 | "%i5",
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57 | 8289b279 | blueswir1 | "%i6",
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58 | 8289b279 | blueswir1 | "%i7",
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59 | 8289b279 | blueswir1 | }; |
60 | d4a9eb1f | blueswir1 | #endif
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61 | 8289b279 | blueswir1 | |
62 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
63 | 8289b279 | blueswir1 | TCG_REG_L0, |
64 | 8289b279 | blueswir1 | TCG_REG_L1, |
65 | 8289b279 | blueswir1 | TCG_REG_L2, |
66 | 8289b279 | blueswir1 | TCG_REG_L3, |
67 | 8289b279 | blueswir1 | TCG_REG_L4, |
68 | 8289b279 | blueswir1 | TCG_REG_L5, |
69 | 8289b279 | blueswir1 | TCG_REG_L6, |
70 | 8289b279 | blueswir1 | TCG_REG_L7, |
71 | 8289b279 | blueswir1 | TCG_REG_I0, |
72 | 8289b279 | blueswir1 | TCG_REG_I1, |
73 | 8289b279 | blueswir1 | TCG_REG_I2, |
74 | 8289b279 | blueswir1 | TCG_REG_I3, |
75 | 8289b279 | blueswir1 | TCG_REG_I4, |
76 | 8289b279 | blueswir1 | }; |
77 | 8289b279 | blueswir1 | |
78 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
79 | 8289b279 | blueswir1 | TCG_REG_O0, |
80 | 8289b279 | blueswir1 | TCG_REG_O1, |
81 | 8289b279 | blueswir1 | TCG_REG_O2, |
82 | 8289b279 | blueswir1 | TCG_REG_O3, |
83 | 8289b279 | blueswir1 | TCG_REG_O4, |
84 | 8289b279 | blueswir1 | TCG_REG_O5, |
85 | 8289b279 | blueswir1 | }; |
86 | 8289b279 | blueswir1 | |
87 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
88 | 8289b279 | blueswir1 | TCG_REG_O0, |
89 | 8289b279 | blueswir1 | TCG_REG_O1, |
90 | 8289b279 | blueswir1 | }; |
91 | 8289b279 | blueswir1 | |
92 | 57e49b40 | blueswir1 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
93 | f5ef6aac | blueswir1 | { |
94 | 57e49b40 | blueswir1 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
95 | 57e49b40 | blueswir1 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
96 | 57e49b40 | blueswir1 | } |
97 | 57e49b40 | blueswir1 | |
98 | 57e49b40 | blueswir1 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
99 | 57e49b40 | blueswir1 | { |
100 | 57e49b40 | blueswir1 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
101 | f5ef6aac | blueswir1 | } |
102 | f5ef6aac | blueswir1 | |
103 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
104 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
105 | 8289b279 | blueswir1 | { |
106 | f54b3f92 | aurel32 | value += addend; |
107 | 8289b279 | blueswir1 | switch (type) {
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108 | 8289b279 | blueswir1 | case R_SPARC_32:
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109 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
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110 | 8289b279 | blueswir1 | tcg_abort(); |
111 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
112 | 8289b279 | blueswir1 | break;
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113 | f5ef6aac | blueswir1 | case R_SPARC_WDISP22:
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114 | f5ef6aac | blueswir1 | value -= (long)code_ptr;
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115 | f5ef6aac | blueswir1 | value >>= 2;
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116 | 57e49b40 | blueswir1 | if (!check_fit_tl(value, 22)) |
117 | f5ef6aac | blueswir1 | tcg_abort(); |
118 | f5ef6aac | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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119 | f5ef6aac | blueswir1 | break;
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120 | 1da92db2 | blueswir1 | case R_SPARC_WDISP19:
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121 | 1da92db2 | blueswir1 | value -= (long)code_ptr;
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122 | 1da92db2 | blueswir1 | value >>= 2;
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123 | 1da92db2 | blueswir1 | if (!check_fit_tl(value, 19)) |
124 | 1da92db2 | blueswir1 | tcg_abort(); |
125 | 1da92db2 | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
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126 | 1da92db2 | blueswir1 | break;
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127 | 8289b279 | blueswir1 | default:
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128 | 8289b279 | blueswir1 | tcg_abort(); |
129 | 8289b279 | blueswir1 | } |
130 | 8289b279 | blueswir1 | } |
131 | 8289b279 | blueswir1 | |
132 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
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133 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
134 | 8289b279 | blueswir1 | { |
135 | 8289b279 | blueswir1 | return 6; |
136 | 8289b279 | blueswir1 | } |
137 | 8289b279 | blueswir1 | |
138 | 8289b279 | blueswir1 | /* parse target specific constraints */
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139 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
140 | 8289b279 | blueswir1 | { |
141 | 8289b279 | blueswir1 | const char *ct_str; |
142 | 8289b279 | blueswir1 | |
143 | 8289b279 | blueswir1 | ct_str = *pct_str; |
144 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
145 | 8289b279 | blueswir1 | case 'r': |
146 | 5e143c43 | Richard Henderson | ct->ct |= TCG_CT_REG; |
147 | 5e143c43 | Richard Henderson | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
148 | 5e143c43 | Richard Henderson | break;
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149 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
150 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
151 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
152 | 53c37487 | blueswir1 | // Helper args
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153 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
154 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
155 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
156 | 8289b279 | blueswir1 | break;
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157 | 8289b279 | blueswir1 | case 'I': |
158 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
159 | 8289b279 | blueswir1 | break;
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160 | 8289b279 | blueswir1 | case 'J': |
161 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
162 | 8289b279 | blueswir1 | break;
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163 | 8289b279 | blueswir1 | default:
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164 | 8289b279 | blueswir1 | return -1; |
165 | 8289b279 | blueswir1 | } |
166 | 8289b279 | blueswir1 | ct_str++; |
167 | 8289b279 | blueswir1 | *pct_str = ct_str; |
168 | 8289b279 | blueswir1 | return 0; |
169 | 8289b279 | blueswir1 | } |
170 | 8289b279 | blueswir1 | |
171 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
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172 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
173 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
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174 | 8289b279 | blueswir1 | { |
175 | 8289b279 | blueswir1 | int ct;
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176 | 8289b279 | blueswir1 | |
177 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
178 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
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179 | 8289b279 | blueswir1 | return 1; |
180 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
181 | 8289b279 | blueswir1 | return 1; |
182 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
183 | 8289b279 | blueswir1 | return 1; |
184 | 8289b279 | blueswir1 | else
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185 | 8289b279 | blueswir1 | return 0; |
186 | 8289b279 | blueswir1 | } |
187 | 8289b279 | blueswir1 | |
188 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
189 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
190 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
191 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
192 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
193 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
194 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
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195 | 8384dd67 | blueswir1 | #define INSN_ASI(x) ((x) << 5) |
196 | 8289b279 | blueswir1 | |
197 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
198 | 1da92db2 | blueswir1 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
199 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
200 | 8289b279 | blueswir1 | |
201 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
202 | cf7c2ca5 | blueswir1 | #define COND_N 0x0 |
203 | cf7c2ca5 | blueswir1 | #define COND_E 0x1 |
204 | cf7c2ca5 | blueswir1 | #define COND_LE 0x2 |
205 | cf7c2ca5 | blueswir1 | #define COND_L 0x3 |
206 | cf7c2ca5 | blueswir1 | #define COND_LEU 0x4 |
207 | cf7c2ca5 | blueswir1 | #define COND_CS 0x5 |
208 | cf7c2ca5 | blueswir1 | #define COND_NEG 0x6 |
209 | cf7c2ca5 | blueswir1 | #define COND_VS 0x7 |
210 | b3db8758 | blueswir1 | #define COND_A 0x8 |
211 | cf7c2ca5 | blueswir1 | #define COND_NE 0x9 |
212 | cf7c2ca5 | blueswir1 | #define COND_G 0xa |
213 | cf7c2ca5 | blueswir1 | #define COND_GE 0xb |
214 | cf7c2ca5 | blueswir1 | #define COND_GU 0xc |
215 | cf7c2ca5 | blueswir1 | #define COND_CC 0xd |
216 | cf7c2ca5 | blueswir1 | #define COND_POS 0xe |
217 | cf7c2ca5 | blueswir1 | #define COND_VC 0xf |
218 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
219 | 8289b279 | blueswir1 | |
220 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
221 | 7a3766f3 | Richard Henderson | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
222 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
223 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
224 | 9a7f3228 | blueswir1 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
225 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
226 | f5ef6aac | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
227 | f5ef6aac | blueswir1 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
228 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
229 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
230 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
231 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
232 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
233 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
234 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
235 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
236 | 8289b279 | blueswir1 | |
237 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
238 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
239 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
240 | 8289b279 | blueswir1 | |
241 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
242 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
243 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
244 | 8289b279 | blueswir1 | |
245 | 7a3766f3 | Richard Henderson | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
246 | 583d1215 | Richard Henderson | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
247 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
248 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
249 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
250 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
251 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
252 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
253 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
254 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
255 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
256 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
257 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
258 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
259 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
260 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
261 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
262 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
263 | 8384dd67 | blueswir1 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
264 | 8384dd67 | blueswir1 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
265 | 8384dd67 | blueswir1 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
266 | 8384dd67 | blueswir1 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
267 | 8384dd67 | blueswir1 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
268 | 8384dd67 | blueswir1 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
269 | 8384dd67 | blueswir1 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
270 | 8384dd67 | blueswir1 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
271 | 8384dd67 | blueswir1 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
272 | 8384dd67 | blueswir1 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
273 | 8384dd67 | blueswir1 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
274 | 8384dd67 | blueswir1 | |
275 | 8384dd67 | blueswir1 | #ifndef ASI_PRIMARY_LITTLE
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276 | 8384dd67 | blueswir1 | #define ASI_PRIMARY_LITTLE 0x88 |
277 | 8384dd67 | blueswir1 | #endif
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278 | 8289b279 | blueswir1 | |
279 | 26cc915c | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
280 | 26cc915c | blueswir1 | int op)
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281 | 26cc915c | blueswir1 | { |
282 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
283 | 26cc915c | blueswir1 | INSN_RS2(rs2)); |
284 | 26cc915c | blueswir1 | } |
285 | 26cc915c | blueswir1 | |
286 | 6f41b777 | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
287 | 6f41b777 | blueswir1 | uint32_t offset, int op)
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288 | 26cc915c | blueswir1 | { |
289 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
290 | 26cc915c | blueswir1 | INSN_IMM13(offset)); |
291 | 26cc915c | blueswir1 | } |
292 | 26cc915c | blueswir1 | |
293 | ba225198 | Richard Henderson | static void tcg_out_arithc(TCGContext *s, int rd, int rs1, |
294 | ba225198 | Richard Henderson | int val2, int val2const, int op) |
295 | ba225198 | Richard Henderson | { |
296 | ba225198 | Richard Henderson | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
297 | ba225198 | Richard Henderson | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); |
298 | ba225198 | Richard Henderson | } |
299 | ba225198 | Richard Henderson | |
300 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
301 | 8289b279 | blueswir1 | { |
302 | 26cc915c | blueswir1 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
303 | 26cc915c | blueswir1 | } |
304 | 26cc915c | blueswir1 | |
305 | 26cc915c | blueswir1 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
306 | 26cc915c | blueswir1 | { |
307 | 26cc915c | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
308 | 8289b279 | blueswir1 | } |
309 | 8289b279 | blueswir1 | |
310 | b101234a | blueswir1 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
311 | b101234a | blueswir1 | { |
312 | b101234a | blueswir1 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
313 | b101234a | blueswir1 | } |
314 | b101234a | blueswir1 | |
315 | b101234a | blueswir1 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
316 | 8289b279 | blueswir1 | { |
317 | 4a09aa89 | Richard Henderson | if (check_fit_tl(arg, 13)) |
318 | b101234a | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
319 | 8289b279 | blueswir1 | else {
|
320 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
321 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
322 | b101234a | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
323 | 8289b279 | blueswir1 | } |
324 | 8289b279 | blueswir1 | } |
325 | 8289b279 | blueswir1 | |
326 | b101234a | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
327 | b101234a | blueswir1 | int ret, tcg_target_long arg)
|
328 | b101234a | blueswir1 | { |
329 | 43172207 | Richard Henderson | /* All 32-bit constants, as well as 64-bit constants with
|
330 | 43172207 | Richard Henderson | no high bits set go through movi_imm32. */
|
331 | 43172207 | Richard Henderson | if (TCG_TARGET_REG_BITS == 32 |
332 | 43172207 | Richard Henderson | || type == TCG_TYPE_I32 |
333 | 43172207 | Richard Henderson | || (arg & ~(tcg_target_long)0xffffffff) == 0) { |
334 | 43172207 | Richard Henderson | tcg_out_movi_imm32(s, ret, arg); |
335 | 43172207 | Richard Henderson | } else if (check_fit_tl(arg, 13)) { |
336 | 43172207 | Richard Henderson | /* A 13-bit constant sign-extended to 64-bits. */
|
337 | 43172207 | Richard Henderson | tcg_out_movi_imm13(s, ret, arg); |
338 | 43172207 | Richard Henderson | } else if (check_fit_tl(arg, 32)) { |
339 | 43172207 | Richard Henderson | /* A 32-bit constant sign-extended to 64-bits. */
|
340 | 43172207 | Richard Henderson | tcg_out_sethi(s, ret, ~arg); |
341 | 43172207 | Richard Henderson | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); |
342 | 43172207 | Richard Henderson | } else {
|
343 | 43172207 | Richard Henderson | tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
|
344 | d795eb86 | blueswir1 | tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
|
345 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
346 | d795eb86 | blueswir1 | tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); |
347 | 6f41b777 | blueswir1 | } |
348 | b101234a | blueswir1 | } |
349 | b101234a | blueswir1 | |
350 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
351 | 8289b279 | blueswir1 | tcg_target_long arg) |
352 | 8289b279 | blueswir1 | { |
353 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
354 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
355 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
356 | 8289b279 | blueswir1 | } |
357 | 8289b279 | blueswir1 | |
358 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
359 | b3db8758 | blueswir1 | tcg_target_long arg) |
360 | b3db8758 | blueswir1 | { |
361 | b101234a | blueswir1 | if (!check_fit_tl(arg, 10)) |
362 | b101234a | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
363 | a212ea75 | Richard Henderson | if (TCG_TARGET_REG_BITS == 64) { |
364 | a212ea75 | Richard Henderson | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
365 | a212ea75 | Richard Henderson | INSN_IMM13(arg & 0x3ff));
|
366 | a212ea75 | Richard Henderson | } else {
|
367 | a212ea75 | Richard Henderson | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
368 | a212ea75 | Richard Henderson | INSN_IMM13(arg & 0x3ff));
|
369 | a212ea75 | Richard Henderson | } |
370 | b3db8758 | blueswir1 | } |
371 | b3db8758 | blueswir1 | |
372 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
373 | 8289b279 | blueswir1 | { |
374 | 57e49b40 | blueswir1 | if (check_fit_tl(offset, 13)) |
375 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
376 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
377 | cf7c2ca5 | blueswir1 | else {
|
378 | cf7c2ca5 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
379 | cf7c2ca5 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
380 | cf7c2ca5 | blueswir1 | INSN_RS2(addr)); |
381 | cf7c2ca5 | blueswir1 | } |
382 | 8289b279 | blueswir1 | } |
383 | 8289b279 | blueswir1 | |
384 | 8384dd67 | blueswir1 | static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
385 | 8384dd67 | blueswir1 | int offset, int op, int asi) |
386 | 8384dd67 | blueswir1 | { |
387 | 8384dd67 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
388 | 8384dd67 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
389 | 8384dd67 | blueswir1 | INSN_ASI(asi) | INSN_RS2(addr)); |
390 | 8384dd67 | blueswir1 | } |
391 | 8384dd67 | blueswir1 | |
392 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
393 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
394 | 8289b279 | blueswir1 | { |
395 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
396 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
397 | 7d551702 | blueswir1 | else
|
398 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDX); |
399 | 8289b279 | blueswir1 | } |
400 | 8289b279 | blueswir1 | |
401 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
402 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
403 | 8289b279 | blueswir1 | { |
404 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
405 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STW); |
406 | 7d551702 | blueswir1 | else
|
407 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STX); |
408 | 8289b279 | blueswir1 | } |
409 | 8289b279 | blueswir1 | |
410 | 583d1215 | Richard Henderson | static inline void tcg_out_sety(TCGContext *s, int rs) |
411 | 8289b279 | blueswir1 | { |
412 | 583d1215 | Richard Henderson | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
413 | 8289b279 | blueswir1 | } |
414 | 8289b279 | blueswir1 | |
415 | 7a3766f3 | Richard Henderson | static inline void tcg_out_rdy(TCGContext *s, int rd) |
416 | 7a3766f3 | Richard Henderson | { |
417 | 7a3766f3 | Richard Henderson | tcg_out32(s, RDY | INSN_RD(rd)); |
418 | 7a3766f3 | Richard Henderson | } |
419 | 7a3766f3 | Richard Henderson | |
420 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
421 | 8289b279 | blueswir1 | { |
422 | 8289b279 | blueswir1 | if (val != 0) { |
423 | 57e49b40 | blueswir1 | if (check_fit_tl(val, 13)) |
424 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
425 | f5ef6aac | blueswir1 | else {
|
426 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
427 | f5ef6aac | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
428 | f5ef6aac | blueswir1 | } |
429 | 8289b279 | blueswir1 | } |
430 | 8289b279 | blueswir1 | } |
431 | 8289b279 | blueswir1 | |
432 | 53c37487 | blueswir1 | static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val) |
433 | 53c37487 | blueswir1 | { |
434 | 53c37487 | blueswir1 | if (val != 0) { |
435 | 53c37487 | blueswir1 | if (check_fit_tl(val, 13)) |
436 | 53c37487 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_AND); |
437 | 53c37487 | blueswir1 | else {
|
438 | 53c37487 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val); |
439 | 53c37487 | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND); |
440 | 53c37487 | blueswir1 | } |
441 | 53c37487 | blueswir1 | } |
442 | 53c37487 | blueswir1 | } |
443 | 53c37487 | blueswir1 | |
444 | 583d1215 | Richard Henderson | static void tcg_out_div32(TCGContext *s, int rd, int rs1, |
445 | 583d1215 | Richard Henderson | int val2, int val2const, int uns) |
446 | 583d1215 | Richard Henderson | { |
447 | 583d1215 | Richard Henderson | /* Load Y with the sign/zero extension of RS1 to 64-bits. */
|
448 | 583d1215 | Richard Henderson | if (uns) {
|
449 | 583d1215 | Richard Henderson | tcg_out_sety(s, TCG_REG_G0); |
450 | 583d1215 | Richard Henderson | } else {
|
451 | 583d1215 | Richard Henderson | tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
|
452 | 583d1215 | Richard Henderson | tcg_out_sety(s, TCG_REG_I5); |
453 | 583d1215 | Richard Henderson | } |
454 | 583d1215 | Richard Henderson | |
455 | 583d1215 | Richard Henderson | tcg_out_arithc(s, rd, rs1, val2, val2const, |
456 | 583d1215 | Richard Henderson | uns ? ARITH_UDIV : ARITH_SDIV); |
457 | 583d1215 | Richard Henderson | } |
458 | 583d1215 | Richard Henderson | |
459 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
460 | 8289b279 | blueswir1 | { |
461 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_G0, 0);
|
462 | 8289b279 | blueswir1 | } |
463 | 8289b279 | blueswir1 | |
464 | 1da92db2 | blueswir1 | static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index) |
465 | cf7c2ca5 | blueswir1 | { |
466 | cf7c2ca5 | blueswir1 | int32_t val; |
467 | cf7c2ca5 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
468 | cf7c2ca5 | blueswir1 | |
469 | cf7c2ca5 | blueswir1 | if (l->has_value) {
|
470 | cf7c2ca5 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
471 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
472 | cf7c2ca5 | blueswir1 | | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
473 | f5ef6aac | blueswir1 | } else {
|
474 | f5ef6aac | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
475 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
476 | f5ef6aac | blueswir1 | } |
477 | cf7c2ca5 | blueswir1 | } |
478 | cf7c2ca5 | blueswir1 | |
479 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
480 | 1da92db2 | blueswir1 | static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) |
481 | 1da92db2 | blueswir1 | { |
482 | 1da92db2 | blueswir1 | int32_t val; |
483 | 1da92db2 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
484 | 1da92db2 | blueswir1 | |
485 | 1da92db2 | blueswir1 | if (l->has_value) {
|
486 | 1da92db2 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
487 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
488 | 1da92db2 | blueswir1 | (0x5 << 19) | |
489 | 1da92db2 | blueswir1 | INSN_OFF19(l->u.value - (unsigned long)s->code_ptr))); |
490 | 1da92db2 | blueswir1 | } else {
|
491 | 1da92db2 | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
|
492 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
493 | 1da92db2 | blueswir1 | (0x5 << 19) | 0)); |
494 | 1da92db2 | blueswir1 | } |
495 | 1da92db2 | blueswir1 | } |
496 | 1da92db2 | blueswir1 | #endif
|
497 | 1da92db2 | blueswir1 | |
498 | cf7c2ca5 | blueswir1 | static const uint8_t tcg_cond_to_bcond[10] = { |
499 | cf7c2ca5 | blueswir1 | [TCG_COND_EQ] = COND_E, |
500 | cf7c2ca5 | blueswir1 | [TCG_COND_NE] = COND_NE, |
501 | cf7c2ca5 | blueswir1 | [TCG_COND_LT] = COND_L, |
502 | cf7c2ca5 | blueswir1 | [TCG_COND_GE] = COND_GE, |
503 | cf7c2ca5 | blueswir1 | [TCG_COND_LE] = COND_LE, |
504 | cf7c2ca5 | blueswir1 | [TCG_COND_GT] = COND_G, |
505 | cf7c2ca5 | blueswir1 | [TCG_COND_LTU] = COND_CS, |
506 | cf7c2ca5 | blueswir1 | [TCG_COND_GEU] = COND_CC, |
507 | cf7c2ca5 | blueswir1 | [TCG_COND_LEU] = COND_LEU, |
508 | cf7c2ca5 | blueswir1 | [TCG_COND_GTU] = COND_GU, |
509 | cf7c2ca5 | blueswir1 | }; |
510 | cf7c2ca5 | blueswir1 | |
511 | 56f4927e | Richard Henderson | static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const) |
512 | 56f4927e | Richard Henderson | { |
513 | ba225198 | Richard Henderson | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
514 | 56f4927e | Richard Henderson | } |
515 | 56f4927e | Richard Henderson | |
516 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i32(TCGContext *s, int cond, |
517 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
518 | 1da92db2 | blueswir1 | int label_index)
|
519 | cf7c2ca5 | blueswir1 | { |
520 | 56f4927e | Richard Henderson | tcg_out_cmp(s, arg1, arg2, const_arg2); |
521 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index); |
522 | cf7c2ca5 | blueswir1 | tcg_out_nop(s); |
523 | cf7c2ca5 | blueswir1 | } |
524 | cf7c2ca5 | blueswir1 | |
525 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
526 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i64(TCGContext *s, int cond, |
527 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
528 | 1da92db2 | blueswir1 | int label_index)
|
529 | 1da92db2 | blueswir1 | { |
530 | 56f4927e | Richard Henderson | tcg_out_cmp(s, arg1, arg2, const_arg2); |
531 | 1da92db2 | blueswir1 | tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index); |
532 | 1da92db2 | blueswir1 | tcg_out_nop(s); |
533 | 1da92db2 | blueswir1 | } |
534 | 56f4927e | Richard Henderson | #else
|
535 | 56f4927e | Richard Henderson | static void tcg_out_brcond2_i32(TCGContext *s, int cond, |
536 | 56f4927e | Richard Henderson | TCGArg al, TCGArg ah, |
537 | 56f4927e | Richard Henderson | TCGArg bl, int blconst,
|
538 | 56f4927e | Richard Henderson | TCGArg bh, int bhconst, int label_dest) |
539 | 56f4927e | Richard Henderson | { |
540 | 56f4927e | Richard Henderson | int cc, label_next = gen_new_label();
|
541 | 56f4927e | Richard Henderson | |
542 | 56f4927e | Richard Henderson | tcg_out_cmp(s, ah, bh, bhconst); |
543 | 56f4927e | Richard Henderson | |
544 | 56f4927e | Richard Henderson | /* Note that we fill one of the delay slots with the second compare. */
|
545 | 56f4927e | Richard Henderson | switch (cond) {
|
546 | 56f4927e | Richard Henderson | case TCG_COND_EQ:
|
547 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
548 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_next); |
549 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
550 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
|
551 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
552 | 56f4927e | Richard Henderson | break;
|
553 | 56f4927e | Richard Henderson | |
554 | 56f4927e | Richard Henderson | case TCG_COND_NE:
|
555 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
556 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
557 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
558 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
559 | 56f4927e | Richard Henderson | break;
|
560 | 56f4927e | Richard Henderson | |
561 | 56f4927e | Richard Henderson | default:
|
562 | 56f4927e | Richard Henderson | /* ??? One could fairly easily special-case 64-bit unsigned
|
563 | 56f4927e | Richard Henderson | compares against 32-bit zero-extended constants. For instance,
|
564 | 56f4927e | Richard Henderson | we know that (unsigned)AH < 0 is false and need not emit it.
|
565 | 56f4927e | Richard Henderson | Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
|
566 | 56f4927e | Richard Henderson | second branch will never be taken. */
|
567 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
|
568 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
569 | 56f4927e | Richard Henderson | tcg_out_nop(s); |
570 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
571 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_next); |
572 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
573 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
|
574 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
575 | 56f4927e | Richard Henderson | break;
|
576 | 56f4927e | Richard Henderson | } |
577 | 56f4927e | Richard Henderson | tcg_out_nop(s); |
578 | 56f4927e | Richard Henderson | |
579 | 56f4927e | Richard Henderson | tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); |
580 | 56f4927e | Richard Henderson | } |
581 | 1da92db2 | blueswir1 | #endif
|
582 | 1da92db2 | blueswir1 | |
583 | 7d551702 | blueswir1 | /* Generate global QEMU prologue and epilogue code */
|
584 | 7d551702 | blueswir1 | void tcg_target_qemu_prologue(TCGContext *s)
|
585 | b3db8758 | blueswir1 | { |
586 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
587 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
588 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
589 | 7d551702 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
590 | 7d551702 | blueswir1 | tcg_out_nop(s); |
591 | b3db8758 | blueswir1 | } |
592 | b3db8758 | blueswir1 | |
593 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
594 | f5ef6aac | blueswir1 | |
595 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
596 | f5ef6aac | blueswir1 | |
597 | 9a7f3228 | blueswir1 | static const void * const qemu_ld_helpers[4] = { |
598 | f5ef6aac | blueswir1 | __ldb_mmu, |
599 | f5ef6aac | blueswir1 | __ldw_mmu, |
600 | f5ef6aac | blueswir1 | __ldl_mmu, |
601 | f5ef6aac | blueswir1 | __ldq_mmu, |
602 | f5ef6aac | blueswir1 | }; |
603 | f5ef6aac | blueswir1 | |
604 | 9a7f3228 | blueswir1 | static const void * const qemu_st_helpers[4] = { |
605 | f5ef6aac | blueswir1 | __stb_mmu, |
606 | f5ef6aac | blueswir1 | __stw_mmu, |
607 | f5ef6aac | blueswir1 | __stl_mmu, |
608 | f5ef6aac | blueswir1 | __stq_mmu, |
609 | f5ef6aac | blueswir1 | }; |
610 | f5ef6aac | blueswir1 | #endif
|
611 | f5ef6aac | blueswir1 | |
612 | bffe1431 | blueswir1 | #if TARGET_LONG_BITS == 32 |
613 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDUW
|
614 | bffe1431 | blueswir1 | #else
|
615 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDX
|
616 | bffe1431 | blueswir1 | #endif
|
617 | bffe1431 | blueswir1 | |
618 | 9d0efc88 | blueswir1 | #if TARGET_PHYS_ADDR_BITS == 32 |
619 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDUW
|
620 | 9d0efc88 | blueswir1 | #else
|
621 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDX
|
622 | 9d0efc88 | blueswir1 | #endif
|
623 | 9d0efc88 | blueswir1 | |
624 | bffe1431 | blueswir1 | #ifdef __arch64__
|
625 | bffe1431 | blueswir1 | #define HOST_LD_OP LDX
|
626 | bffe1431 | blueswir1 | #define HOST_ST_OP STX
|
627 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLLX
|
628 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRAX
|
629 | bffe1431 | blueswir1 | #else
|
630 | bffe1431 | blueswir1 | #define HOST_LD_OP LDUW
|
631 | bffe1431 | blueswir1 | #define HOST_ST_OP STW
|
632 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLL
|
633 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRA
|
634 | bffe1431 | blueswir1 | #endif
|
635 | bffe1431 | blueswir1 | |
636 | f5ef6aac | blueswir1 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
637 | f5ef6aac | blueswir1 | int opc)
|
638 | f5ef6aac | blueswir1 | { |
639 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
640 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
641 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
642 | f5ef6aac | blueswir1 | #endif
|
643 | f5ef6aac | blueswir1 | |
644 | f5ef6aac | blueswir1 | data_reg = *args++; |
645 | f5ef6aac | blueswir1 | addr_reg = *args++; |
646 | f5ef6aac | blueswir1 | mem_index = *args; |
647 | f5ef6aac | blueswir1 | s_bits = opc & 3;
|
648 | f5ef6aac | blueswir1 | |
649 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
650 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
651 | 56fc64df | blueswir1 | arg2 = TCG_REG_O2; |
652 | f5ef6aac | blueswir1 | |
653 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
654 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
655 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
656 | f5ef6aac | blueswir1 | SHIFT_SRL); |
657 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
658 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
659 | f5ef6aac | blueswir1 | ARITH_AND); |
660 | f5ef6aac | blueswir1 | |
661 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
662 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
663 | f5ef6aac | blueswir1 | |
664 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
665 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
666 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_read));
|
667 | 53c37487 | blueswir1 | |
668 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
669 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
670 | f5ef6aac | blueswir1 | |
671 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
672 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
673 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
674 | f5ef6aac | blueswir1 | |
675 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
676 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
677 | f5ef6aac | blueswir1 | |
678 | f5ef6aac | blueswir1 | /* will become:
|
679 | 1da92db2 | blueswir1 | be label1
|
680 | 1da92db2 | blueswir1 | or
|
681 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
682 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
683 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
684 | f5ef6aac | blueswir1 | |
685 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
686 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
687 | f5ef6aac | blueswir1 | |
688 | bffe1431 | blueswir1 | /* mov */
|
689 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); |
690 | bffe1431 | blueswir1 | |
691 | f5ef6aac | blueswir1 | /* XXX: move that code at the end of the TB */
|
692 | 53c37487 | blueswir1 | /* qemu_ld_helper[s_bits](arg0, arg1) */
|
693 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
694 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
695 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
696 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
697 | bffe1431 | blueswir1 | global registers */
|
698 | bffe1431 | blueswir1 | // delay slot
|
699 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
700 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
701 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
702 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
703 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
704 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
705 | f5ef6aac | blueswir1 | |
706 | 53c37487 | blueswir1 | /* data_reg = sign_extend(arg0) */
|
707 | f5ef6aac | blueswir1 | switch(opc) {
|
708 | f5ef6aac | blueswir1 | case 0 | 4: |
709 | 53c37487 | blueswir1 | /* sll arg0, 24/56, data_reg */
|
710 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8, |
711 | bffe1431 | blueswir1 | HOST_SLL_OP); |
712 | 53c37487 | blueswir1 | /* sra data_reg, 24/56, data_reg */
|
713 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
714 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP); |
715 | f5ef6aac | blueswir1 | break;
|
716 | f5ef6aac | blueswir1 | case 1 | 4: |
717 | 53c37487 | blueswir1 | /* sll arg0, 16/48, data_reg */
|
718 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, |
719 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP); |
720 | 53c37487 | blueswir1 | /* sra data_reg, 16/48, data_reg */
|
721 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
722 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP); |
723 | f5ef6aac | blueswir1 | break;
|
724 | f5ef6aac | blueswir1 | case 2 | 4: |
725 | 53c37487 | blueswir1 | /* sll arg0, 32, data_reg */
|
726 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
727 | 53c37487 | blueswir1 | /* sra data_reg, 32, data_reg */
|
728 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
729 | f5ef6aac | blueswir1 | break;
|
730 | f5ef6aac | blueswir1 | case 0: |
731 | f5ef6aac | blueswir1 | case 1: |
732 | f5ef6aac | blueswir1 | case 2: |
733 | f5ef6aac | blueswir1 | case 3: |
734 | f5ef6aac | blueswir1 | default:
|
735 | f5ef6aac | blueswir1 | /* mov */
|
736 | 53c37487 | blueswir1 | tcg_out_mov(s, data_reg, arg0); |
737 | f5ef6aac | blueswir1 | break;
|
738 | f5ef6aac | blueswir1 | } |
739 | f5ef6aac | blueswir1 | |
740 | f5ef6aac | blueswir1 | /* will become:
|
741 | f5ef6aac | blueswir1 | ba label2 */
|
742 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
743 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
744 | f5ef6aac | blueswir1 | |
745 | 53c37487 | blueswir1 | /* nop (delay slot */
|
746 | 53c37487 | blueswir1 | tcg_out_nop(s); |
747 | 53c37487 | blueswir1 | |
748 | f5ef6aac | blueswir1 | /* label1: */
|
749 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
750 | 1da92db2 | blueswir1 | /* be label1 */
|
751 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
752 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
753 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
754 | 1da92db2 | blueswir1 | #else
|
755 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
756 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
757 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
758 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
759 | 1da92db2 | blueswir1 | #endif
|
760 | f5ef6aac | blueswir1 | |
761 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
762 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
763 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP); |
764 | 90cbed46 | blueswir1 | |
765 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
766 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
767 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
768 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
769 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
770 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
771 | 90cbed46 | blueswir1 | #else
|
772 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
773 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
774 | 90cbed46 | blueswir1 | #endif
|
775 | 90cbed46 | blueswir1 | |
776 | f5ef6aac | blueswir1 | #else
|
777 | 56fc64df | blueswir1 | arg0 = addr_reg; |
778 | f5ef6aac | blueswir1 | #endif
|
779 | f5ef6aac | blueswir1 | |
780 | f5ef6aac | blueswir1 | switch(opc) {
|
781 | f5ef6aac | blueswir1 | case 0: |
782 | 56fc64df | blueswir1 | /* ldub [arg0], data_reg */
|
783 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
784 | f5ef6aac | blueswir1 | break;
|
785 | f5ef6aac | blueswir1 | case 0 | 4: |
786 | 56fc64df | blueswir1 | /* ldsb [arg0], data_reg */
|
787 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
788 | f5ef6aac | blueswir1 | break;
|
789 | f5ef6aac | blueswir1 | case 1: |
790 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
791 | 56fc64df | blueswir1 | /* lduh [arg0], data_reg */
|
792 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
793 | 8384dd67 | blueswir1 | #else
|
794 | 56fc64df | blueswir1 | /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
795 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
796 | 8384dd67 | blueswir1 | #endif
|
797 | f5ef6aac | blueswir1 | break;
|
798 | f5ef6aac | blueswir1 | case 1 | 4: |
799 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
800 | 56fc64df | blueswir1 | /* ldsh [arg0], data_reg */
|
801 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
802 | 8384dd67 | blueswir1 | #else
|
803 | 56fc64df | blueswir1 | /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
804 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
805 | 8384dd67 | blueswir1 | #endif
|
806 | f5ef6aac | blueswir1 | break;
|
807 | f5ef6aac | blueswir1 | case 2: |
808 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
809 | 56fc64df | blueswir1 | /* lduw [arg0], data_reg */
|
810 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
811 | 8384dd67 | blueswir1 | #else
|
812 | 56fc64df | blueswir1 | /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
813 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
814 | 8384dd67 | blueswir1 | #endif
|
815 | f5ef6aac | blueswir1 | break;
|
816 | f5ef6aac | blueswir1 | case 2 | 4: |
817 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
818 | 56fc64df | blueswir1 | /* ldsw [arg0], data_reg */
|
819 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
820 | 8384dd67 | blueswir1 | #else
|
821 | 56fc64df | blueswir1 | /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
822 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
823 | 8384dd67 | blueswir1 | #endif
|
824 | f5ef6aac | blueswir1 | break;
|
825 | f5ef6aac | blueswir1 | case 3: |
826 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
827 | 56fc64df | blueswir1 | /* ldx [arg0], data_reg */
|
828 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
829 | 8384dd67 | blueswir1 | #else
|
830 | 56fc64df | blueswir1 | /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
831 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
832 | 8384dd67 | blueswir1 | #endif
|
833 | f5ef6aac | blueswir1 | break;
|
834 | f5ef6aac | blueswir1 | default:
|
835 | f5ef6aac | blueswir1 | tcg_abort(); |
836 | f5ef6aac | blueswir1 | } |
837 | f5ef6aac | blueswir1 | |
838 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
839 | f5ef6aac | blueswir1 | /* label2: */
|
840 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
841 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
842 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
843 | f5ef6aac | blueswir1 | #endif
|
844 | f5ef6aac | blueswir1 | } |
845 | f5ef6aac | blueswir1 | |
846 | f5ef6aac | blueswir1 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
847 | f5ef6aac | blueswir1 | int opc)
|
848 | f5ef6aac | blueswir1 | { |
849 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
850 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
851 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
852 | f5ef6aac | blueswir1 | #endif
|
853 | f5ef6aac | blueswir1 | |
854 | f5ef6aac | blueswir1 | data_reg = *args++; |
855 | f5ef6aac | blueswir1 | addr_reg = *args++; |
856 | f5ef6aac | blueswir1 | mem_index = *args; |
857 | f5ef6aac | blueswir1 | |
858 | f5ef6aac | blueswir1 | s_bits = opc; |
859 | f5ef6aac | blueswir1 | |
860 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
861 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
862 | 53c37487 | blueswir1 | arg2 = TCG_REG_O2; |
863 | f5ef6aac | blueswir1 | |
864 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
865 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
866 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
867 | f5ef6aac | blueswir1 | SHIFT_SRL); |
868 | 53c37487 | blueswir1 | |
869 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
870 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
871 | f5ef6aac | blueswir1 | ARITH_AND); |
872 | f5ef6aac | blueswir1 | |
873 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
874 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
875 | f5ef6aac | blueswir1 | |
876 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
877 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
878 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_write));
|
879 | f5ef6aac | blueswir1 | |
880 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
881 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
882 | f5ef6aac | blueswir1 | |
883 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
884 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
885 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
886 | 53c37487 | blueswir1 | |
887 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
888 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
889 | f5ef6aac | blueswir1 | |
890 | f5ef6aac | blueswir1 | /* will become:
|
891 | 1da92db2 | blueswir1 | be label1
|
892 | 1da92db2 | blueswir1 | or
|
893 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
894 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
895 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
896 | f5ef6aac | blueswir1 | |
897 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
898 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
899 | 53c37487 | blueswir1 | |
900 | 53c37487 | blueswir1 | /* mov */
|
901 | 56fc64df | blueswir1 | tcg_out_mov(s, arg1, data_reg); |
902 | 53c37487 | blueswir1 | |
903 | bffe1431 | blueswir1 | /* mov */
|
904 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); |
905 | bffe1431 | blueswir1 | |
906 | 53c37487 | blueswir1 | /* XXX: move that code at the end of the TB */
|
907 | 53c37487 | blueswir1 | /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
908 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
909 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
910 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
911 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
912 | bffe1431 | blueswir1 | global registers */
|
913 | bffe1431 | blueswir1 | // delay slot
|
914 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
915 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
916 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
917 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
918 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
919 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
920 | f5ef6aac | blueswir1 | |
921 | f5ef6aac | blueswir1 | /* will become:
|
922 | f5ef6aac | blueswir1 | ba label2 */
|
923 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
924 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
925 | f5ef6aac | blueswir1 | |
926 | 53c37487 | blueswir1 | /* nop (delay slot) */
|
927 | 53c37487 | blueswir1 | tcg_out_nop(s); |
928 | 53c37487 | blueswir1 | |
929 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
930 | 1da92db2 | blueswir1 | /* be label1 */
|
931 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
932 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
933 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
934 | 1da92db2 | blueswir1 | #else
|
935 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
936 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
937 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
938 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
939 | 1da92db2 | blueswir1 | #endif
|
940 | f5ef6aac | blueswir1 | |
941 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
942 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
943 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP); |
944 | 53c37487 | blueswir1 | |
945 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
946 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
947 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
948 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
949 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
950 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
951 | 90cbed46 | blueswir1 | #else
|
952 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
953 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
954 | 90cbed46 | blueswir1 | #endif
|
955 | 90cbed46 | blueswir1 | |
956 | f5ef6aac | blueswir1 | #else
|
957 | 56fc64df | blueswir1 | arg0 = addr_reg; |
958 | f5ef6aac | blueswir1 | #endif
|
959 | f5ef6aac | blueswir1 | |
960 | f5ef6aac | blueswir1 | switch(opc) {
|
961 | f5ef6aac | blueswir1 | case 0: |
962 | 56fc64df | blueswir1 | /* stb data_reg, [arg0] */
|
963 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
964 | f5ef6aac | blueswir1 | break;
|
965 | f5ef6aac | blueswir1 | case 1: |
966 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
967 | 56fc64df | blueswir1 | /* sth data_reg, [arg0] */
|
968 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
969 | 8384dd67 | blueswir1 | #else
|
970 | 56fc64df | blueswir1 | /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
971 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
972 | 8384dd67 | blueswir1 | #endif
|
973 | f5ef6aac | blueswir1 | break;
|
974 | f5ef6aac | blueswir1 | case 2: |
975 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
976 | 56fc64df | blueswir1 | /* stw data_reg, [arg0] */
|
977 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
978 | 8384dd67 | blueswir1 | #else
|
979 | 56fc64df | blueswir1 | /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
980 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
981 | 8384dd67 | blueswir1 | #endif
|
982 | f5ef6aac | blueswir1 | break;
|
983 | f5ef6aac | blueswir1 | case 3: |
984 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
985 | 56fc64df | blueswir1 | /* stx data_reg, [arg0] */
|
986 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
987 | 8384dd67 | blueswir1 | #else
|
988 | 56fc64df | blueswir1 | /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
989 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
990 | 8384dd67 | blueswir1 | #endif
|
991 | f5ef6aac | blueswir1 | break;
|
992 | f5ef6aac | blueswir1 | default:
|
993 | f5ef6aac | blueswir1 | tcg_abort(); |
994 | f5ef6aac | blueswir1 | } |
995 | f5ef6aac | blueswir1 | |
996 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
997 | f5ef6aac | blueswir1 | /* label2: */
|
998 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
999 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
1000 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
1001 | f5ef6aac | blueswir1 | #endif
|
1002 | f5ef6aac | blueswir1 | } |
1003 | f5ef6aac | blueswir1 | |
1004 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
1005 | 8289b279 | blueswir1 | const int *const_args) |
1006 | 8289b279 | blueswir1 | { |
1007 | 8289b279 | blueswir1 | int c;
|
1008 | 8289b279 | blueswir1 | |
1009 | 8289b279 | blueswir1 | switch (opc) {
|
1010 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
1011 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
1012 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
1013 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
1014 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
1015 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
1016 | 8289b279 | blueswir1 | break;
|
1017 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
1018 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
1019 | 8289b279 | blueswir1 | /* direct jump method */
|
1020 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
1021 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
1022 | cf7c2ca5 | blueswir1 | INSN_IMM13((args[0] & 0x1fff))); |
1023 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
1024 | 8289b279 | blueswir1 | } else {
|
1025 | 8289b279 | blueswir1 | /* indirect jump method */
|
1026 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
1027 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
1028 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
1029 | 8289b279 | blueswir1 | } |
1030 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
1031 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
1032 | 8289b279 | blueswir1 | break;
|
1033 | 8289b279 | blueswir1 | case INDEX_op_call:
|
1034 | bffe1431 | blueswir1 | if (const_args[0]) |
1035 | bffe1431 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
1036 | bffe1431 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
1037 | bffe1431 | blueswir1 | & 0x3fffffff));
|
1038 | bffe1431 | blueswir1 | else {
|
1039 | bffe1431 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, |
1040 | bffe1431 | blueswir1 | (tcg_target_long)(s->tb_next + args[0]));
|
1041 | bffe1431 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
1042 | bffe1431 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
1043 | 8289b279 | blueswir1 | } |
1044 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
1045 | bffe1431 | blueswir1 | global registers */
|
1046 | bffe1431 | blueswir1 | // delay slot
|
1047 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
1048 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
1049 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
1050 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
1051 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
1052 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
1053 | 8289b279 | blueswir1 | break;
|
1054 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
1055 | 8289b279 | blueswir1 | case INDEX_op_br:
|
1056 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, COND_A, args[0]);
|
1057 | f5ef6aac | blueswir1 | tcg_out_nop(s); |
1058 | 8289b279 | blueswir1 | break;
|
1059 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
1060 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
1061 | 8289b279 | blueswir1 | break;
|
1062 | 8289b279 | blueswir1 | |
1063 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1064 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
1065 | ba225198 | Richard Henderson | glue(glue(case INDEX_op_, x), _i32): \
|
1066 | ba225198 | Richard Henderson | glue(glue(case INDEX_op_, x), _i64)
|
1067 | 8289b279 | blueswir1 | #else
|
1068 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
1069 | ba225198 | Richard Henderson | glue(glue(case INDEX_op_, x), _i32)
|
1070 | 8289b279 | blueswir1 | #endif
|
1071 | ba225198 | Richard Henderson | OP_32_64(ld8u): |
1072 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
1073 | 8289b279 | blueswir1 | break;
|
1074 | ba225198 | Richard Henderson | OP_32_64(ld8s): |
1075 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
1076 | 8289b279 | blueswir1 | break;
|
1077 | ba225198 | Richard Henderson | OP_32_64(ld16u): |
1078 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
1079 | 8289b279 | blueswir1 | break;
|
1080 | ba225198 | Richard Henderson | OP_32_64(ld16s): |
1081 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
1082 | 8289b279 | blueswir1 | break;
|
1083 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
1084 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1085 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
1086 | 8289b279 | blueswir1 | #endif
|
1087 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
1088 | 8289b279 | blueswir1 | break;
|
1089 | ba225198 | Richard Henderson | OP_32_64(st8): |
1090 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
1091 | 8289b279 | blueswir1 | break;
|
1092 | ba225198 | Richard Henderson | OP_32_64(st16): |
1093 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
1094 | 8289b279 | blueswir1 | break;
|
1095 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
1096 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1097 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
1098 | 8289b279 | blueswir1 | #endif
|
1099 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
1100 | 8289b279 | blueswir1 | break;
|
1101 | ba225198 | Richard Henderson | OP_32_64(add): |
1102 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
1103 | ba225198 | Richard Henderson | goto gen_arith;
|
1104 | ba225198 | Richard Henderson | OP_32_64(sub): |
1105 | 8289b279 | blueswir1 | c = ARITH_SUB; |
1106 | ba225198 | Richard Henderson | goto gen_arith;
|
1107 | ba225198 | Richard Henderson | OP_32_64(and): |
1108 | 8289b279 | blueswir1 | c = ARITH_AND; |
1109 | ba225198 | Richard Henderson | goto gen_arith;
|
1110 | ba225198 | Richard Henderson | OP_32_64(or): |
1111 | 8289b279 | blueswir1 | c = ARITH_OR; |
1112 | ba225198 | Richard Henderson | goto gen_arith;
|
1113 | ba225198 | Richard Henderson | OP_32_64(xor): |
1114 | 8289b279 | blueswir1 | c = ARITH_XOR; |
1115 | ba225198 | Richard Henderson | goto gen_arith;
|
1116 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
1117 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
1118 | ba225198 | Richard Henderson | goto gen_arith;
|
1119 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
1120 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
1121 | ba225198 | Richard Henderson | goto gen_arith;
|
1122 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
1123 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
1124 | ba225198 | Richard Henderson | goto gen_arith;
|
1125 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
1126 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
1127 | ba225198 | Richard Henderson | goto gen_arith;
|
1128 | 583d1215 | Richard Henderson | |
1129 | 583d1215 | Richard Henderson | case INDEX_op_div_i32:
|
1130 | 583d1215 | Richard Henderson | tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0); |
1131 | 583d1215 | Richard Henderson | break;
|
1132 | 583d1215 | Richard Henderson | case INDEX_op_divu_i32:
|
1133 | 583d1215 | Richard Henderson | tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1); |
1134 | 583d1215 | Richard Henderson | break;
|
1135 | 583d1215 | Richard Henderson | |
1136 | 583d1215 | Richard Henderson | case INDEX_op_rem_i32:
|
1137 | 583d1215 | Richard Henderson | case INDEX_op_remu_i32:
|
1138 | 583d1215 | Richard Henderson | tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2], |
1139 | 583d1215 | Richard Henderson | opc == INDEX_op_remu_i32); |
1140 | 583d1215 | Richard Henderson | tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2], |
1141 | 583d1215 | Richard Henderson | ARITH_UMUL); |
1142 | 583d1215 | Richard Henderson | tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB); |
1143 | 583d1215 | Richard Henderson | break;
|
1144 | 8289b279 | blueswir1 | |
1145 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
1146 | 1da92db2 | blueswir1 | tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], |
1147 | 1da92db2 | blueswir1 | args[3]);
|
1148 | 8289b279 | blueswir1 | break;
|
1149 | 56f4927e | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
1150 | 56f4927e | Richard Henderson | case INDEX_op_brcond2_i32:
|
1151 | 56f4927e | Richard Henderson | tcg_out_brcond2_i32(s, args[4], args[0], args[1], |
1152 | 56f4927e | Richard Henderson | args[2], const_args[2], |
1153 | 56f4927e | Richard Henderson | args[3], const_args[3], args[5]); |
1154 | 56f4927e | Richard Henderson | break;
|
1155 | 7a3766f3 | Richard Henderson | case INDEX_op_add2_i32:
|
1156 | 7a3766f3 | Richard Henderson | tcg_out_arithc(s, args[0], args[2], args[4], const_args[4], |
1157 | 7a3766f3 | Richard Henderson | ARITH_ADDCC); |
1158 | 7a3766f3 | Richard Henderson | tcg_out_arithc(s, args[1], args[3], args[5], const_args[5], |
1159 | 7a3766f3 | Richard Henderson | ARITH_ADDX); |
1160 | 7a3766f3 | Richard Henderson | break;
|
1161 | 7a3766f3 | Richard Henderson | case INDEX_op_sub2_i32:
|
1162 | 7a3766f3 | Richard Henderson | tcg_out_arithc(s, args[0], args[2], args[4], const_args[4], |
1163 | 7a3766f3 | Richard Henderson | ARITH_SUBCC); |
1164 | 7a3766f3 | Richard Henderson | tcg_out_arithc(s, args[1], args[3], args[5], const_args[5], |
1165 | 7a3766f3 | Richard Henderson | ARITH_SUBX); |
1166 | 7a3766f3 | Richard Henderson | break;
|
1167 | 7a3766f3 | Richard Henderson | case INDEX_op_mulu2_i32:
|
1168 | 7a3766f3 | Richard Henderson | tcg_out_arithc(s, args[0], args[2], args[3], const_args[3], |
1169 | 7a3766f3 | Richard Henderson | ARITH_UMUL); |
1170 | 7a3766f3 | Richard Henderson | tcg_out_rdy(s, args[1]);
|
1171 | 7a3766f3 | Richard Henderson | break;
|
1172 | 56f4927e | Richard Henderson | #endif
|
1173 | 8289b279 | blueswir1 | |
1174 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
1175 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0);
|
1176 | 8289b279 | blueswir1 | break;
|
1177 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
1178 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0 | 4); |
1179 | 8289b279 | blueswir1 | break;
|
1180 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
1181 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1);
|
1182 | 8289b279 | blueswir1 | break;
|
1183 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
1184 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1 | 4); |
1185 | 8289b279 | blueswir1 | break;
|
1186 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
1187 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2);
|
1188 | 8289b279 | blueswir1 | break;
|
1189 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
1190 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2 | 4); |
1191 | 8289b279 | blueswir1 | break;
|
1192 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
1193 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 0);
|
1194 | 8289b279 | blueswir1 | break;
|
1195 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
1196 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 1);
|
1197 | 8289b279 | blueswir1 | break;
|
1198 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
1199 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 2);
|
1200 | 8289b279 | blueswir1 | break;
|
1201 | 8289b279 | blueswir1 | |
1202 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1203 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
1204 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1205 | 8289b279 | blueswir1 | break;
|
1206 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
1207 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
1208 | 53cd9273 | blueswir1 | break;
|
1209 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
1210 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
1211 | 8289b279 | blueswir1 | break;
|
1212 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
1213 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
1214 | 8289b279 | blueswir1 | break;
|
1215 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
1216 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
1217 | ba225198 | Richard Henderson | goto gen_arith;
|
1218 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
1219 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
1220 | ba225198 | Richard Henderson | goto gen_arith;
|
1221 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
1222 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
1223 | ba225198 | Richard Henderson | goto gen_arith;
|
1224 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
1225 | 8289b279 | blueswir1 | c = ARITH_MULX; |
1226 | ba225198 | Richard Henderson | goto gen_arith;
|
1227 | 583d1215 | Richard Henderson | case INDEX_op_div_i64:
|
1228 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
1229 | ba225198 | Richard Henderson | goto gen_arith;
|
1230 | 583d1215 | Richard Henderson | case INDEX_op_divu_i64:
|
1231 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1232 | ba225198 | Richard Henderson | goto gen_arith;
|
1233 | 583d1215 | Richard Henderson | case INDEX_op_rem_i64:
|
1234 | 583d1215 | Richard Henderson | case INDEX_op_remu_i64:
|
1235 | 583d1215 | Richard Henderson | tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2], |
1236 | 583d1215 | Richard Henderson | opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX); |
1237 | 583d1215 | Richard Henderson | tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2], |
1238 | 583d1215 | Richard Henderson | ARITH_MULX); |
1239 | 583d1215 | Richard Henderson | tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB); |
1240 | 583d1215 | Richard Henderson | break;
|
1241 | 8289b279 | blueswir1 | |
1242 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
1243 | 1da92db2 | blueswir1 | tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1], |
1244 | 1da92db2 | blueswir1 | args[3]);
|
1245 | 8289b279 | blueswir1 | break;
|
1246 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
1247 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 3);
|
1248 | 8289b279 | blueswir1 | break;
|
1249 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
1250 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 3);
|
1251 | 8289b279 | blueswir1 | break;
|
1252 | 8289b279 | blueswir1 | |
1253 | 8289b279 | blueswir1 | #endif
|
1254 | ba225198 | Richard Henderson | gen_arith:
|
1255 | ba225198 | Richard Henderson | tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c); |
1256 | 53cd9273 | blueswir1 | break;
|
1257 | 53cd9273 | blueswir1 | |
1258 | 8289b279 | blueswir1 | default:
|
1259 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
1260 | 8289b279 | blueswir1 | tcg_abort(); |
1261 | 8289b279 | blueswir1 | } |
1262 | 8289b279 | blueswir1 | } |
1263 | 8289b279 | blueswir1 | |
1264 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
1265 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
1266 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
1267 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
1268 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
1269 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
1270 | 8289b279 | blueswir1 | |
1271 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
1272 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
1273 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1274 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1275 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1276 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1277 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
1278 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
1279 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
1280 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
1281 | 8289b279 | blueswir1 | |
1282 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
1283 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
1284 | 583d1215 | Richard Henderson | { INDEX_op_div_i32, { "r", "r", "rJ" } }, |
1285 | 583d1215 | Richard Henderson | { INDEX_op_divu_i32, { "r", "r", "rJ" } }, |
1286 | 583d1215 | Richard Henderson | { INDEX_op_rem_i32, { "r", "r", "rJ" } }, |
1287 | 583d1215 | Richard Henderson | { INDEX_op_remu_i32, { "r", "r", "rJ" } }, |
1288 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
1289 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
1290 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
1291 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
1292 | 8289b279 | blueswir1 | |
1293 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
1294 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
1295 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
1296 | 8289b279 | blueswir1 | |
1297 | 56f4927e | Richard Henderson | { INDEX_op_brcond_i32, { "r", "rJ" } }, |
1298 | 56f4927e | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
1299 | 56f4927e | Richard Henderson | { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } }, |
1300 | 7a3766f3 | Richard Henderson | { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } }, |
1301 | 7a3766f3 | Richard Henderson | { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } }, |
1302 | 7a3766f3 | Richard Henderson | { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } }, |
1303 | 56f4927e | Richard Henderson | #endif
|
1304 | 8289b279 | blueswir1 | |
1305 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1306 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1307 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1308 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1309 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1310 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1311 | 8289b279 | blueswir1 | |
1312 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
1313 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
1314 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
1315 | 8289b279 | blueswir1 | |
1316 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1317 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
1318 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
|
1319 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1320 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1321 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1322 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1323 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1324 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1325 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
1326 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
1327 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
1328 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
1329 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
1330 | 56fc64df | blueswir1 | { INDEX_op_qemu_ld64, { "L", "L" } }, |
1331 | 56fc64df | blueswir1 | { INDEX_op_qemu_st64, { "L", "L" } }, |
1332 | 8289b279 | blueswir1 | |
1333 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
1334 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
1335 | 583d1215 | Richard Henderson | { INDEX_op_div_i64, { "r", "r", "rJ" } }, |
1336 | 583d1215 | Richard Henderson | { INDEX_op_divu_i64, { "r", "r", "rJ" } }, |
1337 | 583d1215 | Richard Henderson | { INDEX_op_rem_i64, { "r", "r", "rJ" } }, |
1338 | 583d1215 | Richard Henderson | { INDEX_op_remu_i64, { "r", "r", "rJ" } }, |
1339 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
1340 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
1341 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
1342 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
1343 | 8289b279 | blueswir1 | |
1344 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
1345 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
1346 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
1347 | 8289b279 | blueswir1 | |
1348 | 56f4927e | Richard Henderson | { INDEX_op_brcond_i64, { "r", "rJ" } }, |
1349 | 8289b279 | blueswir1 | #endif
|
1350 | 8289b279 | blueswir1 | { -1 },
|
1351 | 8289b279 | blueswir1 | }; |
1352 | 8289b279 | blueswir1 | |
1353 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
|
1354 | 8289b279 | blueswir1 | { |
1355 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1356 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1357 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1358 | 8289b279 | blueswir1 | #endif
|
1359 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1360 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
|
1361 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
|
1362 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
|
1363 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
|
1364 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
|
1365 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
|
1366 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
|
1367 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
|
1368 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
|
1369 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
|
1370 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
|
1371 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
|
1372 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
|
1373 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
|
1374 | 8289b279 | blueswir1 | |
1375 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
1376 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
1377 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1378 | d795eb86 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
1379 | d795eb86 | blueswir1 | #endif
|
1380 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
1381 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
1382 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
1383 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
1384 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
1385 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
1386 | 8289b279 | blueswir1 | } |