| 207 |
207 |
PCIDevice pci_dev;
|
| 208 |
208 |
MemoryRegion mem;
|
| 209 |
209 |
|
|
210 |
/* Behavior control */
|
|
211 |
uint32_t flags;
|
|
212 |
|
| 210 |
213 |
/* Sub-regions */
|
| 211 |
214 |
MemoryRegion sub_io_mem[7];
|
| 212 |
215 |
|
| ... | ... | |
| 234 |
237 |
int irq_ipi0;
|
| 235 |
238 |
int irq_tim0;
|
| 236 |
239 |
void (*reset) (void *);
|
| 237 |
|
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
|
| 238 |
240 |
} openpic_t;
|
| 239 |
241 |
|
|
242 |
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
|
|
243 |
|
| 240 |
244 |
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
|
| 241 |
245 |
{
|
| 242 |
246 |
set_bit(q->queue, n_IRQ);
|
| ... | ... | |
| 321 |
325 |
return;
|
| 322 |
326 |
}
|
| 323 |
327 |
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
|
| 324 |
|
opp->irq_raise(opp, n_CPU, src);
|
|
328 |
openpic_irq_raise(opp, n_CPU, src);
|
| 325 |
329 |
}
|
| 326 |
330 |
|
| 327 |
331 |
/* update pic state because registers for n_IRQ have changed value */
|
| ... | ... | |
| 753 |
757 |
IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
|
| 754 |
758 |
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
| 755 |
759 |
idx, n_IRQ);
|
| 756 |
|
opp->irq_raise(opp, idx, src);
|
|
760 |
openpic_irq_raise(opp, idx, src);
|
| 757 |
761 |
}
|
| 758 |
762 |
break;
|
| 759 |
763 |
default:
|
| ... | ... | |
| 996 |
1000 |
|
| 997 |
1001 |
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
|
| 998 |
1002 |
{
|
| 999 |
|
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
|
|
1003 |
int n_ci = IDR_CI0 - n_CPU;
|
|
1004 |
|
|
1005 |
if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && test_bit(&src->ide, n_ci)) {
|
|
1006 |
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
|
|
1007 |
} else {
|
|
1008 |
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
|
|
1009 |
}
|
| 1000 |
1010 |
}
|
| 1001 |
1011 |
|
| 1002 |
1012 |
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
|
| ... | ... | |
| 1059 |
1069 |
openpic_save, openpic_load, opp);
|
| 1060 |
1070 |
qemu_register_reset(openpic_reset, opp);
|
| 1061 |
1071 |
|
| 1062 |
|
opp->irq_raise = openpic_irq_raise;
|
| 1063 |
1072 |
opp->reset = openpic_reset;
|
| 1064 |
1073 |
|
| 1065 |
1074 |
if (pmem)
|
| ... | ... | |
| 1068 |
1077 |
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
|
| 1069 |
1078 |
}
|
| 1070 |
1079 |
|
| 1071 |
|
static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
|
| 1072 |
|
{
|
| 1073 |
|
int n_ci = IDR_CI0 - n_CPU;
|
| 1074 |
|
|
| 1075 |
|
if(test_bit(&src->ide, n_ci)) {
|
| 1076 |
|
qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
|
| 1077 |
|
}
|
| 1078 |
|
else {
|
| 1079 |
|
qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
|
| 1080 |
|
}
|
| 1081 |
|
}
|
| 1082 |
|
|
| 1083 |
1080 |
static void mpic_reset (void *opaque)
|
| 1084 |
1081 |
{
|
| 1085 |
1082 |
openpic_t *mpp = (openpic_t *)opaque;
|
| ... | ... | |
| 1265 |
1262 |
mpp->dst[i].irqs = irqs[i];
|
| 1266 |
1263 |
mpp->irq_out = irq_out;
|
| 1267 |
1264 |
|
| 1268 |
|
mpp->irq_raise = mpic_irq_raise;
|
|
1265 |
/* Enable critical interrupt support */
|
|
1266 |
mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
|
| 1269 |
1267 |
mpp->reset = mpic_reset;
|
| 1270 |
1268 |
|
| 1271 |
1269 |
register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
|