2 |
2 |
* QEMU Parallel PORT emulation
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3 |
3 |
*
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4 |
4 |
* Copyright (c) 2003-2005 Fabrice Bellard
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5 |
* Copyright (c) 2007 Marko Kohtala
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5 |
6 |
*
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6 |
7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
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7 |
8 |
* of this software and associated documentation files (the "Software"), to deal
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... | ... | |
25 |
26 |
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26 |
27 |
//#define DEBUG_PARALLEL
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27 |
28 |
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29 |
#ifdef DEBUG_PARALLEL
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30 |
#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
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31 |
#else
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32 |
#define pdebug(fmt, arg...) ((void)0)
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33 |
#endif
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34 |
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35 |
#define PARA_REG_DATA 0
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36 |
#define PARA_REG_STS 1
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37 |
#define PARA_REG_CTR 2
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38 |
#define PARA_REG_EPP_ADDR 3
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39 |
#define PARA_REG_EPP_DATA 4
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40 |
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28 |
41 |
/*
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29 |
42 |
* These are the definitions for the Printer Status Register
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30 |
43 |
*/
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... | ... | |
33 |
46 |
#define PARA_STS_PAPER 0x20 /* Out of paper */
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34 |
47 |
#define PARA_STS_ONLINE 0x10 /* Online */
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35 |
48 |
#define PARA_STS_ERROR 0x08 /* Error complement */
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49 |
#define PARA_STS_TMOUT 0x01 /* EPP timeout */
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36 |
50 |
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37 |
51 |
/*
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38 |
52 |
* These are the definitions for the Printer Control Register
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39 |
53 |
*/
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54 |
#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
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40 |
55 |
#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
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41 |
56 |
#define PARA_CTR_SELECT 0x08 /* Select In complement */
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42 |
57 |
#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
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43 |
58 |
#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
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44 |
59 |
#define PARA_CTR_STROBE 0x01 /* Strobe complement */
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45 |
60 |
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61 |
#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
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62 |
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46 |
63 |
struct ParallelState {
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47 |
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uint8_t data;
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48 |
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uint8_t status; /* read only register */
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64 |
uint8_t dataw;
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65 |
uint8_t datar;
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66 |
uint8_t status;
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49 |
67 |
uint8_t control;
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50 |
68 |
int irq;
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51 |
69 |
int irq_pending;
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52 |
70 |
CharDriverState *chr;
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53 |
71 |
int hw_driver;
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72 |
int epp_timeout;
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73 |
uint32_t last_read_offset; /* For debugging */
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54 |
74 |
};
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55 |
75 |
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56 |
76 |
static void parallel_update_irq(ParallelState *s)
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... | ... | |
61 |
81 |
pic_set_irq(s->irq, 0);
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62 |
82 |
}
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63 |
83 |
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64 |
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static void parallel_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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84 |
static void
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85 |
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
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65 |
86 |
{
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66 |
87 |
ParallelState *s = opaque;
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67 |
88 |
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89 |
pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
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90 |
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91 |
addr &= 7;
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92 |
switch(addr) {
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93 |
case PARA_REG_DATA:
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94 |
s->dataw = val;
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95 |
parallel_update_irq(s);
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96 |
break;
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97 |
case PARA_REG_CTR:
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98 |
if ((val & PARA_CTR_INIT) == 0 ) {
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99 |
s->status = PARA_STS_BUSY;
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100 |
s->status |= PARA_STS_ACK;
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101 |
s->status |= PARA_STS_ONLINE;
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102 |
s->status |= PARA_STS_ERROR;
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103 |
}
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104 |
else if (val & PARA_CTR_SELECT) {
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105 |
if (val & PARA_CTR_STROBE) {
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106 |
s->status &= ~PARA_STS_BUSY;
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107 |
if ((s->control & PARA_CTR_STROBE) == 0)
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108 |
qemu_chr_write(s->chr, &s->dataw, 1);
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109 |
} else {
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110 |
if (s->control & PARA_CTR_INTEN) {
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111 |
s->irq_pending = 1;
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112 |
}
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113 |
}
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114 |
}
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115 |
parallel_update_irq(s);
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116 |
s->control = val;
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117 |
break;
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118 |
}
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119 |
}
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120 |
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121 |
static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
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122 |
{
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123 |
ParallelState *s = opaque;
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124 |
uint8_t parm = val;
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125 |
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126 |
/* Sometimes programs do several writes for timing purposes on old
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|
127 |
HW. Take care not to waste time on writes that do nothing. */
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128 |
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129 |
s->last_read_offset = ~0U;
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130 |
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68 |
131 |
addr &= 7;
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69 |
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#ifdef DEBUG_PARALLEL
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70 |
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printf("parallel: write addr=0x%02x val=0x%02x\n", addr, val);
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71 |
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#endif
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72 |
132 |
switch(addr) {
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73 |
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case 0:
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74 |
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if (s->hw_driver) {
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75 |
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s->data = val;
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76 |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &s->data);
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77 |
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} else {
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78 |
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s->data = val;
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79 |
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parallel_update_irq(s);
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80 |
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}
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133 |
case PARA_REG_DATA:
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134 |
if (s->dataw == val)
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135 |
return;
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136 |
pdebug("wd%02x\n", val);
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137 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
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138 |
s->dataw = val;
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81 |
139 |
break;
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82 |
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case 2:
|
83 |
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if (s->hw_driver) {
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84 |
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s->control = val;
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85 |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &s->control);
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86 |
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} else {
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87 |
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if ((val & PARA_CTR_INIT) == 0 ) {
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88 |
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s->status = PARA_STS_BUSY;
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89 |
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s->status |= PARA_STS_ACK;
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90 |
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s->status |= PARA_STS_ONLINE;
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91 |
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s->status |= PARA_STS_ERROR;
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92 |
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}
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93 |
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else if (val & PARA_CTR_SELECT) {
|
94 |
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if (val & PARA_CTR_STROBE) {
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95 |
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s->status &= ~PARA_STS_BUSY;
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96 |
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if ((s->control & PARA_CTR_STROBE) == 0)
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97 |
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qemu_chr_write(s->chr, &s->data, 1);
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98 |
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} else {
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99 |
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if (s->control & PARA_CTR_INTEN) {
|
100 |
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s->irq_pending = 1;
|
101 |
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}
|
102 |
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}
|
103 |
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}
|
104 |
|
parallel_update_irq(s);
|
105 |
|
s->control = val;
|
106 |
|
}
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|
140 |
case PARA_REG_STS:
|
|
141 |
pdebug("ws%02x\n", val);
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|
142 |
if (val & PARA_STS_TMOUT)
|
|
143 |
s->epp_timeout = 0;
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|
144 |
break;
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|
145 |
case PARA_REG_CTR:
|
|
146 |
val |= 0xc0;
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|
147 |
if (s->control == val)
|
|
148 |
return;
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|
149 |
pdebug("wc%02x\n", val);
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|
150 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
|
|
151 |
s->control = val;
|
107 |
152 |
break;
|
|
153 |
case PARA_REG_EPP_ADDR:
|
|
154 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
|
|
155 |
/* Controls not correct for EPP address cycle, so do nothing */
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|
156 |
pdebug("wa%02x s\n", val);
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157 |
else {
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|
158 |
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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|
159 |
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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|
160 |
s->epp_timeout = 1;
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161 |
pdebug("wa%02x t\n", val);
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162 |
}
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163 |
else
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164 |
pdebug("wa%02x\n", val);
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|
165 |
}
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166 |
break;
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167 |
case PARA_REG_EPP_DATA:
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|
168 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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169 |
/* Controls not correct for EPP data cycle, so do nothing */
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|
170 |
pdebug("we%02x s\n", val);
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171 |
else {
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172 |
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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173 |
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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|
174 |
s->epp_timeout = 1;
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|
175 |
pdebug("we%02x t\n", val);
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|
176 |
}
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177 |
else
|
|
178 |
pdebug("we%02x\n", val);
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|
179 |
}
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|
180 |
break;
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|
181 |
}
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182 |
}
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|
183 |
|
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184 |
static void
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|
185 |
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
|
|
186 |
{
|
|
187 |
ParallelState *s = opaque;
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|
188 |
uint16_t eppdata = cpu_to_le16(val);
|
|
189 |
int err;
|
|
190 |
struct ParallelIOArg ioarg = {
|
|
191 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
|
192 |
};
|
|
193 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
|
194 |
/* Controls not correct for EPP data cycle, so do nothing */
|
|
195 |
pdebug("we%04x s\n", val);
|
|
196 |
return;
|
|
197 |
}
|
|
198 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
|
|
199 |
if (err) {
|
|
200 |
s->epp_timeout = 1;
|
|
201 |
pdebug("we%04x t\n", val);
|
|
202 |
}
|
|
203 |
else
|
|
204 |
pdebug("we%04x\n", val);
|
|
205 |
}
|
|
206 |
|
|
207 |
static void
|
|
208 |
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
|
|
209 |
{
|
|
210 |
ParallelState *s = opaque;
|
|
211 |
uint32_t eppdata = cpu_to_le32(val);
|
|
212 |
int err;
|
|
213 |
struct ParallelIOArg ioarg = {
|
|
214 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
|
215 |
};
|
|
216 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
|
217 |
/* Controls not correct for EPP data cycle, so do nothing */
|
|
218 |
pdebug("we%08x s\n", val);
|
|
219 |
return;
|
|
220 |
}
|
|
221 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
|
|
222 |
if (err) {
|
|
223 |
s->epp_timeout = 1;
|
|
224 |
pdebug("we%08x t\n", val);
|
108 |
225 |
}
|
|
226 |
else
|
|
227 |
pdebug("we%08x\n", val);
|
109 |
228 |
}
|
110 |
229 |
|
111 |
|
static uint32_t parallel_ioport_read(void *opaque, uint32_t addr)
|
|
230 |
static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
|
112 |
231 |
{
|
113 |
232 |
ParallelState *s = opaque;
|
114 |
233 |
uint32_t ret = 0xff;
|
115 |
234 |
|
116 |
235 |
addr &= 7;
|
117 |
236 |
switch(addr) {
|
118 |
|
case 0:
|
119 |
|
if (s->hw_driver) {
|
120 |
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &s->data);
|
121 |
|
}
|
122 |
|
ret = s->data;
|
|
237 |
case PARA_REG_DATA:
|
|
238 |
if (s->control & PARA_CTR_DIR)
|
|
239 |
ret = s->datar;
|
|
240 |
else
|
|
241 |
ret = s->dataw;
|
123 |
242 |
break;
|
124 |
|
case 1:
|
125 |
|
if (s->hw_driver) {
|
126 |
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &s->status);
|
127 |
|
ret = s->status;
|
128 |
|
} else {
|
129 |
|
ret = s->status;
|
130 |
|
s->irq_pending = 0;
|
131 |
|
if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
|
132 |
|
/* XXX Fixme: wait 5 microseconds */
|
133 |
|
if (s->status & PARA_STS_ACK)
|
134 |
|
s->status &= ~PARA_STS_ACK;
|
135 |
|
else {
|
136 |
|
/* XXX Fixme: wait 5 microseconds */
|
137 |
|
s->status |= PARA_STS_ACK;
|
138 |
|
s->status |= PARA_STS_BUSY;
|
139 |
|
}
|
140 |
|
}
|
141 |
|
parallel_update_irq(s);
|
142 |
|
}
|
|
243 |
case PARA_REG_STS:
|
|
244 |
ret = s->status;
|
|
245 |
s->irq_pending = 0;
|
|
246 |
if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
|
|
247 |
/* XXX Fixme: wait 5 microseconds */
|
|
248 |
if (s->status & PARA_STS_ACK)
|
|
249 |
s->status &= ~PARA_STS_ACK;
|
|
250 |
else {
|
|
251 |
/* XXX Fixme: wait 5 microseconds */
|
|
252 |
s->status |= PARA_STS_ACK;
|
|
253 |
s->status |= PARA_STS_BUSY;
|
|
254 |
}
|
|
255 |
}
|
|
256 |
parallel_update_irq(s);
|
143 |
257 |
break;
|
144 |
|
case 2:
|
145 |
|
if (s->hw_driver) {
|
146 |
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &s->control);
|
147 |
|
}
|
|
258 |
case PARA_REG_CTR:
|
148 |
259 |
ret = s->control;
|
149 |
260 |
break;
|
150 |
261 |
}
|
151 |
|
#ifdef DEBUG_PARALLEL
|
152 |
|
printf("parallel: read addr=0x%02x val=0x%02x\n", addr, ret);
|
153 |
|
#endif
|
|
262 |
pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
|
|
263 |
return ret;
|
|
264 |
}
|
|
265 |
|
|
266 |
static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
|
|
267 |
{
|
|
268 |
ParallelState *s = opaque;
|
|
269 |
uint8_t ret = 0xff;
|
|
270 |
addr &= 7;
|
|
271 |
switch(addr) {
|
|
272 |
case PARA_REG_DATA:
|
|
273 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
|
|
274 |
if (s->last_read_offset != addr || s->datar != ret)
|
|
275 |
pdebug("rd%02x\n", ret);
|
|
276 |
s->datar = ret;
|
|
277 |
break;
|
|
278 |
case PARA_REG_STS:
|
|
279 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
|
|
280 |
ret &= ~PARA_STS_TMOUT;
|
|
281 |
if (s->epp_timeout)
|
|
282 |
ret |= PARA_STS_TMOUT;
|
|
283 |
if (s->last_read_offset != addr || s->status != ret)
|
|
284 |
pdebug("rs%02x\n", ret);
|
|
285 |
s->status = ret;
|
|
286 |
break;
|
|
287 |
case PARA_REG_CTR:
|
|
288 |
/* s->control has some bits fixed to 1. It is zero only when
|
|
289 |
it has not been yet written to. */
|
|
290 |
if (s->control == 0) {
|
|
291 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
|
|
292 |
if (s->last_read_offset != addr)
|
|
293 |
pdebug("rc%02x\n", ret);
|
|
294 |
s->control = ret;
|
|
295 |
}
|
|
296 |
else {
|
|
297 |
ret = s->control;
|
|
298 |
if (s->last_read_offset != addr)
|
|
299 |
pdebug("rc%02x\n", ret);
|
|
300 |
}
|
|
301 |
break;
|
|
302 |
case PARA_REG_EPP_ADDR:
|
|
303 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
|
304 |
/* Controls not correct for EPP addr cycle, so do nothing */
|
|
305 |
pdebug("ra%02x s\n", ret);
|
|
306 |
else {
|
|
307 |
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
|
|
308 |
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
|
|
309 |
s->epp_timeout = 1;
|
|
310 |
pdebug("ra%02x t\n", ret);
|
|
311 |
}
|
|
312 |
else
|
|
313 |
pdebug("ra%02x\n", ret);
|
|
314 |
}
|
|
315 |
break;
|
|
316 |
case PARA_REG_EPP_DATA:
|
|
317 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
|
318 |
/* Controls not correct for EPP data cycle, so do nothing */
|
|
319 |
pdebug("re%02x s\n", ret);
|
|
320 |
else {
|
|
321 |
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
|
|
322 |
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
|
|
323 |
s->epp_timeout = 1;
|
|
324 |
pdebug("re%02x t\n", ret);
|
|
325 |
}
|
|
326 |
else
|
|
327 |
pdebug("re%02x\n", ret);
|
|
328 |
}
|
|
329 |
break;
|
|
330 |
}
|
|
331 |
s->last_read_offset = addr;
|
|
332 |
return ret;
|
|
333 |
}
|
|
334 |
|
|
335 |
static uint32_t
|
|
336 |
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
|
337 |
{
|
|
338 |
ParallelState *s = opaque;
|
|
339 |
uint32_t ret;
|
|
340 |
uint16_t eppdata = ~0;
|
|
341 |
int err;
|
|
342 |
struct ParallelIOArg ioarg = {
|
|
343 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
|
344 |
};
|
|
345 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
|
346 |
/* Controls not correct for EPP data cycle, so do nothing */
|
|
347 |
pdebug("re%04x s\n", eppdata);
|
|
348 |
return eppdata;
|
|
349 |
}
|
|
350 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
|
|
351 |
ret = le16_to_cpu(eppdata);
|
|
352 |
|
|
353 |
if (err) {
|
|
354 |
s->epp_timeout = 1;
|
|
355 |
pdebug("re%04x t\n", ret);
|
|
356 |
}
|
|
357 |
else
|
|
358 |
pdebug("re%04x\n", ret);
|
|
359 |
return ret;
|
|
360 |
}
|
|
361 |
|
|
362 |
static uint32_t
|
|
363 |
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
|
364 |
{
|
|
365 |
ParallelState *s = opaque;
|
|
366 |
uint32_t ret;
|
|
367 |
uint32_t eppdata = ~0U;
|
|
368 |
int err;
|
|
369 |
struct ParallelIOArg ioarg = {
|
|
370 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
|
371 |
};
|
|
372 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
|
373 |
/* Controls not correct for EPP data cycle, so do nothing */
|
|
374 |
pdebug("re%08x s\n", eppdata);
|
|
375 |
return eppdata;
|
|
376 |
}
|
|
377 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
|
|
378 |
ret = le32_to_cpu(eppdata);
|
|
379 |
|
|
380 |
if (err) {
|
|
381 |
s->epp_timeout = 1;
|
|
382 |
pdebug("re%08x t\n", ret);
|
|
383 |
}
|
|
384 |
else
|
|
385 |
pdebug("re%08x\n", ret);
|
|
386 |
return ret;
|
|
387 |
}
|
|
388 |
|
|
389 |
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
|
|
390 |
{
|
|
391 |
addr &= 7;
|
|
392 |
pdebug("wecp%d=%02x\n", addr, val);
|
|
393 |
}
|
|
394 |
|
|
395 |
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
|
|
396 |
{
|
|
397 |
uint8_t ret = 0xff;
|
|
398 |
addr &= 7;
|
|
399 |
pdebug("recp%d:%02x\n", addr, ret);
|
154 |
400 |
return ret;
|
155 |
401 |
}
|
156 |
402 |
|
... | ... | |
163 |
409 |
s = qemu_mallocz(sizeof(ParallelState));
|
164 |
410 |
if (!s)
|
165 |
411 |
return NULL;
|
166 |
|
s->chr = chr;
|
167 |
|
s->hw_driver = 0;
|
168 |
|
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0)
|
169 |
|
s->hw_driver = 1;
|
170 |
|
|
171 |
|
s->irq = irq;
|
172 |
|
s->data = 0;
|
|
412 |
s->datar = ~0;
|
|
413 |
s->dataw = ~0;
|
173 |
414 |
s->status = PARA_STS_BUSY;
|
174 |
415 |
s->status |= PARA_STS_ACK;
|
175 |
416 |
s->status |= PARA_STS_ONLINE;
|
176 |
417 |
s->status |= PARA_STS_ERROR;
|
177 |
418 |
s->control = PARA_CTR_SELECT;
|
178 |
419 |
s->control |= PARA_CTR_INIT;
|
|
420 |
s->irq = irq;
|
|
421 |
s->irq_pending = 0;
|
|
422 |
s->chr = chr;
|
|
423 |
s->hw_driver = 0;
|
|
424 |
s->epp_timeout = 0;
|
|
425 |
s->last_read_offset = ~0U;
|
179 |
426 |
|
180 |
|
register_ioport_write(base, 8, 1, parallel_ioport_write, s);
|
181 |
|
register_ioport_read(base, 8, 1, parallel_ioport_read, s);
|
|
427 |
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
|
|
428 |
s->hw_driver = 1;
|
|
429 |
s->status = dummy;
|
|
430 |
}
|
|
431 |
|
|
432 |
if (s->hw_driver) {
|
|
433 |
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
|
|
434 |
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
|
|
435 |
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
|
|
436 |
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
|
|
437 |
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
|
|
438 |
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
|
|
439 |
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
|
|
440 |
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
|
|
441 |
}
|
|
442 |
else {
|
|
443 |
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
|
|
444 |
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
|
|
445 |
}
|
182 |
446 |
return s;
|
183 |
447 |
}
|