root / hw / sh_pci.c @ 59369b08
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1 | 1e5459a3 | balrog | /*
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2 | 1e5459a3 | balrog | * SuperH on-chip PCIC emulation.
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3 | 1e5459a3 | balrog | *
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4 | 1e5459a3 | balrog | * Copyright (c) 2008 Takashi YOSHII
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5 | 1e5459a3 | balrog | *
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6 | 1e5459a3 | balrog | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1e5459a3 | balrog | * of this software and associated documentation files (the "Software"), to deal
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8 | 1e5459a3 | balrog | * in the Software without restriction, including without limitation the rights
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9 | 1e5459a3 | balrog | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1e5459a3 | balrog | * copies of the Software, and to permit persons to whom the Software is
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11 | 1e5459a3 | balrog | * furnished to do so, subject to the following conditions:
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12 | 1e5459a3 | balrog | *
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13 | 1e5459a3 | balrog | * The above copyright notice and this permission notice shall be included in
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14 | 1e5459a3 | balrog | * all copies or substantial portions of the Software.
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15 | 1e5459a3 | balrog | *
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16 | 1e5459a3 | balrog | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1e5459a3 | balrog | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1e5459a3 | balrog | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1e5459a3 | balrog | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1e5459a3 | balrog | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1e5459a3 | balrog | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1e5459a3 | balrog | * THE SOFTWARE.
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23 | 1e5459a3 | balrog | */
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24 | 1e5459a3 | balrog | #include "hw.h" |
25 | 1e5459a3 | balrog | #include "sh.h" |
26 | 1e5459a3 | balrog | #include "pci.h" |
27 | b6243d99 | Isaku Yamahata | #include "pci_host.h" |
28 | 18e08a55 | Michael S. Tsirkin | #include "sh_pci.h" |
29 | 1e5459a3 | balrog | #include "bswap.h" |
30 | 1e5459a3 | balrog | |
31 | 1e5459a3 | balrog | typedef struct { |
32 | 1e5459a3 | balrog | PCIBus *bus; |
33 | 1e5459a3 | balrog | PCIDevice *dev; |
34 | 1e5459a3 | balrog | uint32_t par; |
35 | 1e5459a3 | balrog | uint32_t mbr; |
36 | 1e5459a3 | balrog | uint32_t iobr; |
37 | 1e5459a3 | balrog | } SHPCIC; |
38 | 1e5459a3 | balrog | |
39 | c227f099 | Anthony Liguori | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
40 | 1e5459a3 | balrog | { |
41 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
42 | 1e5459a3 | balrog | switch(addr) {
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43 | 1e5459a3 | balrog | case 0 ... 0xfc: |
44 | 1e5459a3 | balrog | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
45 | 1e5459a3 | balrog | break;
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46 | 1e5459a3 | balrog | case 0x1c0: |
47 | 1e5459a3 | balrog | pcic->par = val; |
48 | 1e5459a3 | balrog | break;
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49 | 1e5459a3 | balrog | case 0x1c4: |
50 | 5ba9e952 | Aurelien Jarno | pcic->mbr = val & 0xff000001;
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51 | 1e5459a3 | balrog | break;
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52 | 1e5459a3 | balrog | case 0x1c8: |
53 | 5ba9e952 | Aurelien Jarno | if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { |
54 | 5ba9e952 | Aurelien Jarno | cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, |
55 | 5ba9e952 | Aurelien Jarno | IO_MEM_UNASSIGNED); |
56 | 5ba9e952 | Aurelien Jarno | pcic->iobr = val & 0xfffc0001;
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57 | 968d683c | Alexander Graf | isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); |
58 | 5ba9e952 | Aurelien Jarno | } |
59 | 1e5459a3 | balrog | break;
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60 | 1e5459a3 | balrog | case 0x220: |
61 | 1e5459a3 | balrog | pci_data_write(pcic->bus, pcic->par, val, 4);
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62 | 1e5459a3 | balrog | break;
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63 | 1e5459a3 | balrog | } |
64 | 1e5459a3 | balrog | } |
65 | 1e5459a3 | balrog | |
66 | c227f099 | Anthony Liguori | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
67 | 1e5459a3 | balrog | { |
68 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
69 | 1e5459a3 | balrog | switch(addr) {
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70 | 1e5459a3 | balrog | case 0 ... 0xfc: |
71 | 1e5459a3 | balrog | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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72 | 1e5459a3 | balrog | case 0x1c0: |
73 | 1e5459a3 | balrog | return pcic->par;
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74 | 5ba9e952 | Aurelien Jarno | case 0x1c4: |
75 | 5ba9e952 | Aurelien Jarno | return pcic->mbr;
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76 | 5ba9e952 | Aurelien Jarno | case 0x1c8: |
77 | 5ba9e952 | Aurelien Jarno | return pcic->iobr;
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78 | 1e5459a3 | balrog | case 0x220: |
79 | 1e5459a3 | balrog | return pci_data_read(pcic->bus, pcic->par, 4); |
80 | 1e5459a3 | balrog | } |
81 | 1e5459a3 | balrog | return 0; |
82 | 1e5459a3 | balrog | } |
83 | 1e5459a3 | balrog | |
84 | 1e5459a3 | balrog | typedef struct { |
85 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const r[3]; |
86 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const w[3]; |
87 | 1e5459a3 | balrog | } MemOp; |
88 | 1e5459a3 | balrog | |
89 | 1e5459a3 | balrog | static MemOp sh_pci_reg = {
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90 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_read }, |
91 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_write }, |
92 | 1e5459a3 | balrog | }; |
93 | 1e5459a3 | balrog | |
94 | 1e5459a3 | balrog | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
95 | 5d4e84c8 | Juan Quintela | void *opaque, int devfn_min, int nirq) |
96 | 1e5459a3 | balrog | { |
97 | 1e5459a3 | balrog | SHPCIC *p; |
98 | 5ba9e952 | Aurelien Jarno | int reg;
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99 | 1e5459a3 | balrog | |
100 | 1e5459a3 | balrog | p = qemu_mallocz(sizeof(SHPCIC));
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101 | 02e2da45 | Paul Brook | p->bus = pci_register_bus(NULL, "pci", |
102 | 5d4e84c8 | Juan Quintela | set_irq, map_irq, opaque, devfn_min, nirq); |
103 | 1e5459a3 | balrog | |
104 | 1e5459a3 | balrog | p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), |
105 | 1e5459a3 | balrog | -1, NULL, NULL); |
106 | 2507c12a | Alexander Graf | reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p, |
107 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
108 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1e200000, 0x224, reg); |
109 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfe200000, 0x224, reg); |
110 | 5ba9e952 | Aurelien Jarno | |
111 | 5ba9e952 | Aurelien Jarno | p->iobr = 0xfe240000;
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112 | 968d683c | Alexander Graf | isa_mmio_init(p->iobr, 0x40000);
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113 | 1e5459a3 | balrog | |
114 | deb54399 | aliguori | pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI); |
115 | a770dc7e | aliguori | pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R); |
116 | 1e5459a3 | balrog | p->dev->config[0x04] = 0x80; |
117 | 1e5459a3 | balrog | p->dev->config[0x05] = 0x00; |
118 | 1e5459a3 | balrog | p->dev->config[0x06] = 0x90; |
119 | 1e5459a3 | balrog | p->dev->config[0x07] = 0x02; |
120 | 1e5459a3 | balrog | |
121 | 1e5459a3 | balrog | return p->bus;
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122 | 1e5459a3 | balrog | } |