root / hw / sm501.c @ 59d94130
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1 | ffd39257 | blueswir1 | /*
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2 | ffd39257 | blueswir1 | * QEMU SM501 Device
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3 | ffd39257 | blueswir1 | *
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4 | ffd39257 | blueswir1 | * Copyright (c) 2008 Shin-ichiro KAWASAKI
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5 | ffd39257 | blueswir1 | *
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6 | ffd39257 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | ffd39257 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | ffd39257 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | ffd39257 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | ffd39257 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | ffd39257 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | ffd39257 | blueswir1 | *
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13 | ffd39257 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | ffd39257 | blueswir1 | * all copies or substantial portions of the Software.
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15 | ffd39257 | blueswir1 | *
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16 | ffd39257 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | ffd39257 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | ffd39257 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | ffd39257 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | ffd39257 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | ffd39257 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | ffd39257 | blueswir1 | * THE SOFTWARE.
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23 | ffd39257 | blueswir1 | */
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24 | ffd39257 | blueswir1 | |
25 | ffd39257 | blueswir1 | #include <stdio.h> |
26 | ffd39257 | blueswir1 | #include <assert.h> |
27 | ffd39257 | blueswir1 | #include "hw.h" |
28 | ffd39257 | blueswir1 | #include "pc.h" |
29 | ffd39257 | blueswir1 | #include "console.h" |
30 | b79e1752 | aurel32 | #include "devices.h" |
31 | ffd39257 | blueswir1 | |
32 | ffd39257 | blueswir1 | /*
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33 | ffd39257 | blueswir1 | * Status: 2008/11/02
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34 | ffd39257 | blueswir1 | * - Minimum implementation for Linux console : mmio regs and CRT layer.
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35 | ffd39257 | blueswir1 | * - Always updates full screen.
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36 | ffd39257 | blueswir1 | *
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37 | ffd39257 | blueswir1 | * TODO:
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38 | ffd39257 | blueswir1 | * - Panel support
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39 | ffd39257 | blueswir1 | * - Hardware cursor support
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40 | ffd39257 | blueswir1 | * - Touch panel support
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41 | ffd39257 | blueswir1 | * - USB support
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42 | ffd39257 | blueswir1 | * - UART support
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43 | ffd39257 | blueswir1 | * - Performance tuning
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44 | ffd39257 | blueswir1 | */
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45 | ffd39257 | blueswir1 | |
46 | ffd39257 | blueswir1 | //#define DEBUG_SM501
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47 | ffd39257 | blueswir1 | //#define DEBUG_BITBLT
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48 | ffd39257 | blueswir1 | |
49 | ffd39257 | blueswir1 | #ifdef DEBUG_SM501
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50 | ffd39257 | blueswir1 | #define SM501_DPRINTF(fmt...) printf(fmt)
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51 | ffd39257 | blueswir1 | #else
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52 | ffd39257 | blueswir1 | #define SM501_DPRINTF(fmt...) do {} while(0) |
53 | ffd39257 | blueswir1 | #endif
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54 | ffd39257 | blueswir1 | |
55 | ffd39257 | blueswir1 | |
56 | ffd39257 | blueswir1 | #define MMIO_BASE_OFFSET 0x3e00000 |
57 | ffd39257 | blueswir1 | |
58 | ffd39257 | blueswir1 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
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59 | ffd39257 | blueswir1 | |
60 | ffd39257 | blueswir1 | /* System Configuration area */
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61 | ffd39257 | blueswir1 | /* System config base */
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62 | ffd39257 | blueswir1 | #define SM501_SYS_CONFIG (0x000000) |
63 | ffd39257 | blueswir1 | |
64 | ffd39257 | blueswir1 | /* config 1 */
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65 | ffd39257 | blueswir1 | #define SM501_SYSTEM_CONTROL (0x000000) |
66 | ffd39257 | blueswir1 | |
67 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) |
68 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_MEM_TRISTATE (1<<1) |
69 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_CRT_TRISTATE (1<<2) |
70 | ffd39257 | blueswir1 | |
71 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) |
72 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) |
73 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) |
74 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) |
75 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) |
76 | ffd39257 | blueswir1 | |
77 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) |
78 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) |
79 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) |
80 | ffd39257 | blueswir1 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) |
81 | ffd39257 | blueswir1 | |
82 | ffd39257 | blueswir1 | /* miscellaneous control */
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83 | ffd39257 | blueswir1 | |
84 | ffd39257 | blueswir1 | #define SM501_MISC_CONTROL (0x000004) |
85 | ffd39257 | blueswir1 | |
86 | ffd39257 | blueswir1 | #define SM501_MISC_BUS_SH (0x0) |
87 | ffd39257 | blueswir1 | #define SM501_MISC_BUS_PCI (0x1) |
88 | ffd39257 | blueswir1 | #define SM501_MISC_BUS_XSCALE (0x2) |
89 | ffd39257 | blueswir1 | #define SM501_MISC_BUS_NEC (0x6) |
90 | ffd39257 | blueswir1 | #define SM501_MISC_BUS_MASK (0x7) |
91 | ffd39257 | blueswir1 | |
92 | ffd39257 | blueswir1 | #define SM501_MISC_VR_62MB (1<<3) |
93 | ffd39257 | blueswir1 | #define SM501_MISC_CDR_RESET (1<<7) |
94 | ffd39257 | blueswir1 | #define SM501_MISC_USB_LB (1<<8) |
95 | ffd39257 | blueswir1 | #define SM501_MISC_USB_SLAVE (1<<9) |
96 | ffd39257 | blueswir1 | #define SM501_MISC_BL_1 (1<<10) |
97 | ffd39257 | blueswir1 | #define SM501_MISC_MC (1<<11) |
98 | ffd39257 | blueswir1 | #define SM501_MISC_DAC_POWER (1<<12) |
99 | ffd39257 | blueswir1 | #define SM501_MISC_IRQ_INVERT (1<<16) |
100 | ffd39257 | blueswir1 | #define SM501_MISC_SH (1<<17) |
101 | ffd39257 | blueswir1 | |
102 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_EMPTY (0<<18) |
103 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_8 (1<<18) |
104 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_16 (2<<18) |
105 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_24 (3<<18) |
106 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_32 (4<<18) |
107 | ffd39257 | blueswir1 | #define SM501_MISC_HOLD_MASK (7<<18) |
108 | ffd39257 | blueswir1 | |
109 | ffd39257 | blueswir1 | #define SM501_MISC_FREQ_12 (1<<24) |
110 | ffd39257 | blueswir1 | #define SM501_MISC_PNL_24BIT (1<<25) |
111 | ffd39257 | blueswir1 | #define SM501_MISC_8051_LE (1<<26) |
112 | ffd39257 | blueswir1 | |
113 | ffd39257 | blueswir1 | |
114 | ffd39257 | blueswir1 | |
115 | ffd39257 | blueswir1 | #define SM501_GPIO31_0_CONTROL (0x000008) |
116 | ffd39257 | blueswir1 | #define SM501_GPIO63_32_CONTROL (0x00000C) |
117 | ffd39257 | blueswir1 | #define SM501_DRAM_CONTROL (0x000010) |
118 | ffd39257 | blueswir1 | |
119 | ffd39257 | blueswir1 | /* command list */
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120 | ffd39257 | blueswir1 | #define SM501_ARBTRTN_CONTROL (0x000014) |
121 | ffd39257 | blueswir1 | |
122 | ffd39257 | blueswir1 | /* command list */
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123 | ffd39257 | blueswir1 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
124 | ffd39257 | blueswir1 | |
125 | ffd39257 | blueswir1 | /* interrupt debug */
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126 | ffd39257 | blueswir1 | #define SM501_RAW_IRQ_STATUS (0x000028) |
127 | ffd39257 | blueswir1 | #define SM501_RAW_IRQ_CLEAR (0x000028) |
128 | ffd39257 | blueswir1 | #define SM501_IRQ_STATUS (0x00002C) |
129 | ffd39257 | blueswir1 | #define SM501_IRQ_MASK (0x000030) |
130 | ffd39257 | blueswir1 | #define SM501_DEBUG_CONTROL (0x000034) |
131 | ffd39257 | blueswir1 | |
132 | ffd39257 | blueswir1 | /* power management */
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133 | ffd39257 | blueswir1 | #define SM501_POWERMODE_P2X_SRC (1<<29) |
134 | ffd39257 | blueswir1 | #define SM501_POWERMODE_V2X_SRC (1<<20) |
135 | ffd39257 | blueswir1 | #define SM501_POWERMODE_M_SRC (1<<12) |
136 | ffd39257 | blueswir1 | #define SM501_POWERMODE_M1_SRC (1<<4) |
137 | ffd39257 | blueswir1 | |
138 | ffd39257 | blueswir1 | #define SM501_CURRENT_GATE (0x000038) |
139 | ffd39257 | blueswir1 | #define SM501_CURRENT_CLOCK (0x00003C) |
140 | ffd39257 | blueswir1 | #define SM501_POWER_MODE_0_GATE (0x000040) |
141 | ffd39257 | blueswir1 | #define SM501_POWER_MODE_0_CLOCK (0x000044) |
142 | ffd39257 | blueswir1 | #define SM501_POWER_MODE_1_GATE (0x000048) |
143 | ffd39257 | blueswir1 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) |
144 | ffd39257 | blueswir1 | #define SM501_SLEEP_MODE_GATE (0x000050) |
145 | ffd39257 | blueswir1 | #define SM501_POWER_MODE_CONTROL (0x000054) |
146 | ffd39257 | blueswir1 | |
147 | ffd39257 | blueswir1 | /* power gates for units within the 501 */
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148 | ffd39257 | blueswir1 | #define SM501_GATE_HOST (0) |
149 | ffd39257 | blueswir1 | #define SM501_GATE_MEMORY (1) |
150 | ffd39257 | blueswir1 | #define SM501_GATE_DISPLAY (2) |
151 | ffd39257 | blueswir1 | #define SM501_GATE_2D_ENGINE (3) |
152 | ffd39257 | blueswir1 | #define SM501_GATE_CSC (4) |
153 | ffd39257 | blueswir1 | #define SM501_GATE_ZVPORT (5) |
154 | ffd39257 | blueswir1 | #define SM501_GATE_GPIO (6) |
155 | ffd39257 | blueswir1 | #define SM501_GATE_UART0 (7) |
156 | ffd39257 | blueswir1 | #define SM501_GATE_UART1 (8) |
157 | ffd39257 | blueswir1 | #define SM501_GATE_SSP (10) |
158 | ffd39257 | blueswir1 | #define SM501_GATE_USB_HOST (11) |
159 | ffd39257 | blueswir1 | #define SM501_GATE_USB_GADGET (12) |
160 | ffd39257 | blueswir1 | #define SM501_GATE_UCONTROLLER (17) |
161 | ffd39257 | blueswir1 | #define SM501_GATE_AC97 (18) |
162 | ffd39257 | blueswir1 | |
163 | ffd39257 | blueswir1 | /* panel clock */
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164 | ffd39257 | blueswir1 | #define SM501_CLOCK_P2XCLK (24) |
165 | ffd39257 | blueswir1 | /* crt clock */
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166 | ffd39257 | blueswir1 | #define SM501_CLOCK_V2XCLK (16) |
167 | ffd39257 | blueswir1 | /* main clock */
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168 | ffd39257 | blueswir1 | #define SM501_CLOCK_MCLK (8) |
169 | ffd39257 | blueswir1 | /* SDRAM controller clock */
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170 | ffd39257 | blueswir1 | #define SM501_CLOCK_M1XCLK (0) |
171 | ffd39257 | blueswir1 | |
172 | ffd39257 | blueswir1 | /* config 2 */
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173 | ffd39257 | blueswir1 | #define SM501_PCI_MASTER_BASE (0x000058) |
174 | ffd39257 | blueswir1 | #define SM501_ENDIAN_CONTROL (0x00005C) |
175 | ffd39257 | blueswir1 | #define SM501_DEVICEID (0x000060) |
176 | ffd39257 | blueswir1 | /* 0x050100A0 */
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177 | ffd39257 | blueswir1 | |
178 | ffd39257 | blueswir1 | #define SM501_DEVICEID_SM501 (0x05010000) |
179 | ffd39257 | blueswir1 | #define SM501_DEVICEID_IDMASK (0xffff0000) |
180 | ffd39257 | blueswir1 | #define SM501_DEVICEID_REVMASK (0x000000ff) |
181 | ffd39257 | blueswir1 | |
182 | ffd39257 | blueswir1 | #define SM501_PLLCLOCK_COUNT (0x000064) |
183 | ffd39257 | blueswir1 | #define SM501_MISC_TIMING (0x000068) |
184 | ffd39257 | blueswir1 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) |
185 | ffd39257 | blueswir1 | |
186 | ffd39257 | blueswir1 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
187 | ffd39257 | blueswir1 | |
188 | ffd39257 | blueswir1 | /* GPIO base */
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189 | ffd39257 | blueswir1 | #define SM501_GPIO (0x010000) |
190 | ffd39257 | blueswir1 | #define SM501_GPIO_DATA_LOW (0x00) |
191 | ffd39257 | blueswir1 | #define SM501_GPIO_DATA_HIGH (0x04) |
192 | ffd39257 | blueswir1 | #define SM501_GPIO_DDR_LOW (0x08) |
193 | ffd39257 | blueswir1 | #define SM501_GPIO_DDR_HIGH (0x0C) |
194 | ffd39257 | blueswir1 | #define SM501_GPIO_IRQ_SETUP (0x10) |
195 | ffd39257 | blueswir1 | #define SM501_GPIO_IRQ_STATUS (0x14) |
196 | ffd39257 | blueswir1 | #define SM501_GPIO_IRQ_RESET (0x14) |
197 | ffd39257 | blueswir1 | |
198 | ffd39257 | blueswir1 | /* I2C controller base */
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199 | ffd39257 | blueswir1 | #define SM501_I2C (0x010040) |
200 | ffd39257 | blueswir1 | #define SM501_I2C_BYTE_COUNT (0x00) |
201 | ffd39257 | blueswir1 | #define SM501_I2C_CONTROL (0x01) |
202 | ffd39257 | blueswir1 | #define SM501_I2C_STATUS (0x02) |
203 | ffd39257 | blueswir1 | #define SM501_I2C_RESET (0x02) |
204 | ffd39257 | blueswir1 | #define SM501_I2C_SLAVE_ADDRESS (0x03) |
205 | ffd39257 | blueswir1 | #define SM501_I2C_DATA (0x04) |
206 | ffd39257 | blueswir1 | |
207 | ffd39257 | blueswir1 | /* SSP base */
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208 | ffd39257 | blueswir1 | #define SM501_SSP (0x020000) |
209 | ffd39257 | blueswir1 | |
210 | ffd39257 | blueswir1 | /* Uart 0 base */
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211 | ffd39257 | blueswir1 | #define SM501_UART0 (0x030000) |
212 | ffd39257 | blueswir1 | |
213 | ffd39257 | blueswir1 | /* Uart 1 base */
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214 | ffd39257 | blueswir1 | #define SM501_UART1 (0x030020) |
215 | ffd39257 | blueswir1 | |
216 | ffd39257 | blueswir1 | /* USB host port base */
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217 | ffd39257 | blueswir1 | #define SM501_USB_HOST (0x040000) |
218 | ffd39257 | blueswir1 | |
219 | ffd39257 | blueswir1 | /* USB slave/gadget base */
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220 | ffd39257 | blueswir1 | #define SM501_USB_GADGET (0x060000) |
221 | ffd39257 | blueswir1 | |
222 | ffd39257 | blueswir1 | /* USB slave/gadget data port base */
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223 | ffd39257 | blueswir1 | #define SM501_USB_GADGET_DATA (0x070000) |
224 | ffd39257 | blueswir1 | |
225 | ffd39257 | blueswir1 | /* Display controller/video engine base */
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226 | ffd39257 | blueswir1 | #define SM501_DC (0x080000) |
227 | ffd39257 | blueswir1 | |
228 | ffd39257 | blueswir1 | /* common defines for the SM501 address registers */
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229 | ffd39257 | blueswir1 | #define SM501_ADDR_FLIP (1<<31) |
230 | ffd39257 | blueswir1 | #define SM501_ADDR_EXT (1<<27) |
231 | ffd39257 | blueswir1 | #define SM501_ADDR_CS1 (1<<26) |
232 | ffd39257 | blueswir1 | #define SM501_ADDR_MASK (0x3f << 26) |
233 | ffd39257 | blueswir1 | |
234 | ffd39257 | blueswir1 | #define SM501_FIFO_MASK (0x3 << 16) |
235 | ffd39257 | blueswir1 | #define SM501_FIFO_1 (0x0 << 16) |
236 | ffd39257 | blueswir1 | #define SM501_FIFO_3 (0x1 << 16) |
237 | ffd39257 | blueswir1 | #define SM501_FIFO_7 (0x2 << 16) |
238 | ffd39257 | blueswir1 | #define SM501_FIFO_11 (0x3 << 16) |
239 | ffd39257 | blueswir1 | |
240 | ffd39257 | blueswir1 | /* common registers for panel and the crt */
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241 | ffd39257 | blueswir1 | #define SM501_OFF_DC_H_TOT (0x000) |
242 | ffd39257 | blueswir1 | #define SM501_OFF_DC_V_TOT (0x008) |
243 | ffd39257 | blueswir1 | #define SM501_OFF_DC_H_SYNC (0x004) |
244 | ffd39257 | blueswir1 | #define SM501_OFF_DC_V_SYNC (0x00C) |
245 | ffd39257 | blueswir1 | |
246 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL (0x000) |
247 | ffd39257 | blueswir1 | |
248 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_FPEN (1<<27) |
249 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_BIAS (1<<26) |
250 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_DATA (1<<25) |
251 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_VDD (1<<24) |
252 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_DP (1<<23) |
253 | ffd39257 | blueswir1 | |
254 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) |
255 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) |
256 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) |
257 | ffd39257 | blueswir1 | |
258 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_DE (1<<20) |
259 | ffd39257 | blueswir1 | |
260 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) |
261 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) |
262 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) |
263 | ffd39257 | blueswir1 | |
264 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_CP (1<<14) |
265 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_VSP (1<<13) |
266 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_HSP (1<<12) |
267 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_CK (1<<9) |
268 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_TE (1<<8) |
269 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_VPD (1<<7) |
270 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_VP (1<<6) |
271 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_HPD (1<<5) |
272 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_HP (1<<4) |
273 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) |
274 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_EN (1<<2) |
275 | ffd39257 | blueswir1 | |
276 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_8BPP (0<<0) |
277 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_16BPP (1<<0) |
278 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CONTROL_32BPP (2<<0) |
279 | ffd39257 | blueswir1 | |
280 | ffd39257 | blueswir1 | |
281 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) |
282 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_COLOR_KEY (0x008) |
283 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_FB_ADDR (0x00C) |
284 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_FB_OFFSET (0x010) |
285 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_FB_WIDTH (0x014) |
286 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) |
287 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_TL_LOC (0x01C) |
288 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_BR_LOC (0x020) |
289 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_H_TOT (0x024) |
290 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_H_SYNC (0x028) |
291 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_V_TOT (0x02C) |
292 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_V_SYNC (0x030) |
293 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_CUR_LINE (0x034) |
294 | ffd39257 | blueswir1 | |
295 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_CONTROL (0x040) |
296 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) |
297 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) |
298 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) |
299 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_TL_LOC (0x050) |
300 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_BR_LOC (0x054) |
301 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_SCALE (0x058) |
302 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) |
303 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) |
304 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) |
305 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) |
306 | ffd39257 | blueswir1 | |
307 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) |
308 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) |
309 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) |
310 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) |
311 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) |
312 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) |
313 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) |
314 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) |
315 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) |
316 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) |
317 | ffd39257 | blueswir1 | |
318 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) |
319 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) |
320 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) |
321 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) |
322 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) |
323 | ffd39257 | blueswir1 | |
324 | ffd39257 | blueswir1 | #define SM501_HWC_EN (1<<31) |
325 | ffd39257 | blueswir1 | |
326 | ffd39257 | blueswir1 | #define SM501_OFF_HWC_ADDR (0x00) |
327 | ffd39257 | blueswir1 | #define SM501_OFF_HWC_LOC (0x04) |
328 | ffd39257 | blueswir1 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) |
329 | ffd39257 | blueswir1 | #define SM501_OFF_HWC_COLOR_3 (0x0C) |
330 | ffd39257 | blueswir1 | |
331 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_CONTROL (0x100) |
332 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_FB_ADDR (0x104) |
333 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) |
334 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_TL_LOC (0x10C) |
335 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_BR_LOC (0x110) |
336 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) |
337 | ffd39257 | blueswir1 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) |
338 | ffd39257 | blueswir1 | |
339 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL (0x200) |
340 | ffd39257 | blueswir1 | |
341 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_TVP (1<<15) |
342 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_CP (1<<14) |
343 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_VSP (1<<13) |
344 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_HSP (1<<12) |
345 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_VS (1<<11) |
346 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_BLANK (1<<10) |
347 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_SEL (1<<9) |
348 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_TE (1<<8) |
349 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
350 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_GAMMA (1<<3) |
351 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_ENABLE (1<<2) |
352 | ffd39257 | blueswir1 | |
353 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_8BPP (0<<0) |
354 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_16BPP (1<<0) |
355 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CONTROL_32BPP (2<<0) |
356 | ffd39257 | blueswir1 | |
357 | ffd39257 | blueswir1 | #define SM501_DC_CRT_FB_ADDR (0x204) |
358 | ffd39257 | blueswir1 | #define SM501_DC_CRT_FB_OFFSET (0x208) |
359 | ffd39257 | blueswir1 | #define SM501_DC_CRT_H_TOT (0x20C) |
360 | ffd39257 | blueswir1 | #define SM501_DC_CRT_H_SYNC (0x210) |
361 | ffd39257 | blueswir1 | #define SM501_DC_CRT_V_TOT (0x214) |
362 | ffd39257 | blueswir1 | #define SM501_DC_CRT_V_SYNC (0x218) |
363 | ffd39257 | blueswir1 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) |
364 | ffd39257 | blueswir1 | #define SM501_DC_CRT_CUR_LINE (0x220) |
365 | ffd39257 | blueswir1 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) |
366 | ffd39257 | blueswir1 | |
367 | ffd39257 | blueswir1 | #define SM501_DC_CRT_HWC_BASE (0x230) |
368 | ffd39257 | blueswir1 | #define SM501_DC_CRT_HWC_ADDR (0x230) |
369 | ffd39257 | blueswir1 | #define SM501_DC_CRT_HWC_LOC (0x234) |
370 | ffd39257 | blueswir1 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) |
371 | ffd39257 | blueswir1 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) |
372 | ffd39257 | blueswir1 | |
373 | ffd39257 | blueswir1 | #define SM501_DC_PANEL_PALETTE (0x400) |
374 | ffd39257 | blueswir1 | |
375 | ffd39257 | blueswir1 | #define SM501_DC_VIDEO_PALETTE (0x800) |
376 | ffd39257 | blueswir1 | |
377 | ffd39257 | blueswir1 | #define SM501_DC_CRT_PALETTE (0xC00) |
378 | ffd39257 | blueswir1 | |
379 | ffd39257 | blueswir1 | /* Zoom Video port base */
|
380 | ffd39257 | blueswir1 | #define SM501_ZVPORT (0x090000) |
381 | ffd39257 | blueswir1 | |
382 | ffd39257 | blueswir1 | /* AC97/I2S base */
|
383 | ffd39257 | blueswir1 | #define SM501_AC97 (0x0A0000) |
384 | ffd39257 | blueswir1 | |
385 | ffd39257 | blueswir1 | /* 8051 micro controller base */
|
386 | ffd39257 | blueswir1 | #define SM501_UCONTROLLER (0x0B0000) |
387 | ffd39257 | blueswir1 | |
388 | ffd39257 | blueswir1 | /* 8051 micro controller SRAM base */
|
389 | ffd39257 | blueswir1 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
390 | ffd39257 | blueswir1 | |
391 | ffd39257 | blueswir1 | /* DMA base */
|
392 | ffd39257 | blueswir1 | #define SM501_DMA (0x0D0000) |
393 | ffd39257 | blueswir1 | |
394 | ffd39257 | blueswir1 | /* 2d engine base */
|
395 | ffd39257 | blueswir1 | #define SM501_2D_ENGINE (0x100000) |
396 | ffd39257 | blueswir1 | #define SM501_2D_SOURCE (0x00) |
397 | ffd39257 | blueswir1 | #define SM501_2D_DESTINATION (0x04) |
398 | ffd39257 | blueswir1 | #define SM501_2D_DIMENSION (0x08) |
399 | ffd39257 | blueswir1 | #define SM501_2D_CONTROL (0x0C) |
400 | ffd39257 | blueswir1 | #define SM501_2D_PITCH (0x10) |
401 | ffd39257 | blueswir1 | #define SM501_2D_FOREGROUND (0x14) |
402 | ffd39257 | blueswir1 | #define SM501_2D_BACKGROUND (0x18) |
403 | ffd39257 | blueswir1 | #define SM501_2D_STRETCH (0x1C) |
404 | ffd39257 | blueswir1 | #define SM501_2D_COLOR_COMPARE (0x20) |
405 | ffd39257 | blueswir1 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) |
406 | ffd39257 | blueswir1 | #define SM501_2D_MASK (0x28) |
407 | ffd39257 | blueswir1 | #define SM501_2D_CLIP_TL (0x2C) |
408 | ffd39257 | blueswir1 | #define SM501_2D_CLIP_BR (0x30) |
409 | ffd39257 | blueswir1 | #define SM501_2D_MONO_PATTERN_LOW (0x34) |
410 | ffd39257 | blueswir1 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) |
411 | ffd39257 | blueswir1 | #define SM501_2D_WINDOW_WIDTH (0x3C) |
412 | ffd39257 | blueswir1 | #define SM501_2D_SOURCE_BASE (0x40) |
413 | ffd39257 | blueswir1 | #define SM501_2D_DESTINATION_BASE (0x44) |
414 | ffd39257 | blueswir1 | #define SM501_2D_ALPHA (0x48) |
415 | ffd39257 | blueswir1 | #define SM501_2D_WRAP (0x4C) |
416 | ffd39257 | blueswir1 | #define SM501_2D_STATUS (0x50) |
417 | ffd39257 | blueswir1 | |
418 | ffd39257 | blueswir1 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) |
419 | ffd39257 | blueswir1 | #define SM501_CSC_CONSTANTS (0xCC) |
420 | ffd39257 | blueswir1 | #define SM501_CSC_Y_SOURCE_X (0xD0) |
421 | ffd39257 | blueswir1 | #define SM501_CSC_Y_SOURCE_Y (0xD4) |
422 | ffd39257 | blueswir1 | #define SM501_CSC_U_SOURCE_BASE (0xD8) |
423 | ffd39257 | blueswir1 | #define SM501_CSC_V_SOURCE_BASE (0xDC) |
424 | ffd39257 | blueswir1 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) |
425 | ffd39257 | blueswir1 | #define SM501_CSC_SOURCE_PITCH (0xE4) |
426 | ffd39257 | blueswir1 | #define SM501_CSC_DESTINATION (0xE8) |
427 | ffd39257 | blueswir1 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) |
428 | ffd39257 | blueswir1 | #define SM501_CSC_DESTINATION_PITCH (0xF0) |
429 | ffd39257 | blueswir1 | #define SM501_CSC_SCALE_FACTOR (0xF4) |
430 | ffd39257 | blueswir1 | #define SM501_CSC_DESTINATION_BASE (0xF8) |
431 | ffd39257 | blueswir1 | #define SM501_CSC_CONTROL (0xFC) |
432 | ffd39257 | blueswir1 | |
433 | ffd39257 | blueswir1 | /* 2d engine data port base */
|
434 | ffd39257 | blueswir1 | #define SM501_2D_ENGINE_DATA (0x110000) |
435 | ffd39257 | blueswir1 | |
436 | ffd39257 | blueswir1 | /* end of register definitions */
|
437 | ffd39257 | blueswir1 | |
438 | ffd39257 | blueswir1 | |
439 | ffd39257 | blueswir1 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
|
440 | ffd39257 | blueswir1 | static const uint32_t sm501_mem_local_size[] = { |
441 | ffd39257 | blueswir1 | [0] = 4*1024*1024, |
442 | ffd39257 | blueswir1 | [1] = 8*1024*1024, |
443 | ffd39257 | blueswir1 | [2] = 16*1024*1024, |
444 | ffd39257 | blueswir1 | [3] = 32*1024*1024, |
445 | ffd39257 | blueswir1 | [4] = 64*1024*1024, |
446 | ffd39257 | blueswir1 | [5] = 2*1024*1024, |
447 | ffd39257 | blueswir1 | }; |
448 | ffd39257 | blueswir1 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
|
449 | ffd39257 | blueswir1 | |
450 | ffd39257 | blueswir1 | typedef struct SM501State { |
451 | ffd39257 | blueswir1 | /* graphic console status */
|
452 | ffd39257 | blueswir1 | DisplayState *ds; |
453 | ffd39257 | blueswir1 | QEMUConsole *console; |
454 | ffd39257 | blueswir1 | |
455 | ffd39257 | blueswir1 | /* status & internal resources */
|
456 | ffd39257 | blueswir1 | target_phys_addr_t base; |
457 | ffd39257 | blueswir1 | uint32_t local_mem_size_index; |
458 | ffd39257 | blueswir1 | uint8_t * local_mem; |
459 | ffd39257 | blueswir1 | uint32_t last_width; |
460 | ffd39257 | blueswir1 | uint32_t last_height; |
461 | ffd39257 | blueswir1 | |
462 | ffd39257 | blueswir1 | /* mmio registers */
|
463 | ffd39257 | blueswir1 | uint32_t system_control; |
464 | ffd39257 | blueswir1 | uint32_t misc_control; |
465 | ffd39257 | blueswir1 | uint32_t gpio_31_0_control; |
466 | ffd39257 | blueswir1 | uint32_t gpio_63_32_control; |
467 | ffd39257 | blueswir1 | uint32_t dram_control; |
468 | ffd39257 | blueswir1 | uint32_t irq_mask; |
469 | ffd39257 | blueswir1 | uint32_t misc_timing; |
470 | ffd39257 | blueswir1 | uint32_t power_mode_control; |
471 | ffd39257 | blueswir1 | |
472 | ffd39257 | blueswir1 | uint32_t uart0_ier; |
473 | ffd39257 | blueswir1 | uint32_t uart0_lcr; |
474 | ffd39257 | blueswir1 | uint32_t uart0_mcr; |
475 | ffd39257 | blueswir1 | uint32_t uart0_scr; |
476 | ffd39257 | blueswir1 | |
477 | ffd39257 | blueswir1 | uint8_t dc_palette[0x400 * 3]; |
478 | ffd39257 | blueswir1 | |
479 | ffd39257 | blueswir1 | uint32_t dc_panel_control; |
480 | ffd39257 | blueswir1 | uint32_t dc_panel_panning_control; |
481 | ffd39257 | blueswir1 | uint32_t dc_panel_fb_addr; |
482 | ffd39257 | blueswir1 | uint32_t dc_panel_fb_offset; |
483 | ffd39257 | blueswir1 | uint32_t dc_panel_fb_width; |
484 | ffd39257 | blueswir1 | uint32_t dc_panel_fb_height; |
485 | ffd39257 | blueswir1 | uint32_t dc_panel_tl_location; |
486 | ffd39257 | blueswir1 | uint32_t dc_panel_br_location; |
487 | ffd39257 | blueswir1 | uint32_t dc_panel_h_total; |
488 | ffd39257 | blueswir1 | uint32_t dc_panel_h_sync; |
489 | ffd39257 | blueswir1 | uint32_t dc_panel_v_total; |
490 | ffd39257 | blueswir1 | uint32_t dc_panel_v_sync; |
491 | ffd39257 | blueswir1 | |
492 | ffd39257 | blueswir1 | uint32_t dc_panel_hwc_addr; |
493 | ffd39257 | blueswir1 | uint32_t dc_panel_hwc_location; |
494 | ffd39257 | blueswir1 | uint32_t dc_panel_hwc_color_1_2; |
495 | ffd39257 | blueswir1 | uint32_t dc_panel_hwc_color_3; |
496 | ffd39257 | blueswir1 | |
497 | ffd39257 | blueswir1 | uint32_t dc_crt_control; |
498 | ffd39257 | blueswir1 | uint32_t dc_crt_fb_addr; |
499 | ffd39257 | blueswir1 | uint32_t dc_crt_fb_offset; |
500 | ffd39257 | blueswir1 | uint32_t dc_crt_h_total; |
501 | ffd39257 | blueswir1 | uint32_t dc_crt_h_sync; |
502 | ffd39257 | blueswir1 | uint32_t dc_crt_v_total; |
503 | ffd39257 | blueswir1 | uint32_t dc_crt_v_sync; |
504 | ffd39257 | blueswir1 | |
505 | ffd39257 | blueswir1 | uint32_t dc_crt_hwc_addr; |
506 | ffd39257 | blueswir1 | uint32_t dc_crt_hwc_location; |
507 | ffd39257 | blueswir1 | uint32_t dc_crt_hwc_color_1_2; |
508 | ffd39257 | blueswir1 | uint32_t dc_crt_hwc_color_3; |
509 | ffd39257 | blueswir1 | |
510 | ffd39257 | blueswir1 | } SM501State; |
511 | ffd39257 | blueswir1 | |
512 | ffd39257 | blueswir1 | static uint32_t get_local_mem_size_index(uint32_t size)
|
513 | ffd39257 | blueswir1 | { |
514 | ffd39257 | blueswir1 | uint32_t norm_size = 0;
|
515 | ffd39257 | blueswir1 | int i, index = 0; |
516 | ffd39257 | blueswir1 | |
517 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
518 | ffd39257 | blueswir1 | uint32_t new_size = sm501_mem_local_size[i]; |
519 | ffd39257 | blueswir1 | if (new_size >= size) {
|
520 | ffd39257 | blueswir1 | if (norm_size == 0 || norm_size > new_size) { |
521 | ffd39257 | blueswir1 | norm_size = new_size; |
522 | ffd39257 | blueswir1 | index = i; |
523 | ffd39257 | blueswir1 | } |
524 | ffd39257 | blueswir1 | } |
525 | ffd39257 | blueswir1 | } |
526 | ffd39257 | blueswir1 | |
527 | ffd39257 | blueswir1 | return index;
|
528 | ffd39257 | blueswir1 | } |
529 | ffd39257 | blueswir1 | |
530 | ffd39257 | blueswir1 | static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) |
531 | ffd39257 | blueswir1 | { |
532 | ffd39257 | blueswir1 | SM501State * s = (SM501State *)opaque; |
533 | ffd39257 | blueswir1 | uint32_t ret = 0;
|
534 | 8da3ff18 | pbrook | SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); |
535 | ffd39257 | blueswir1 | |
536 | 8da3ff18 | pbrook | switch(addr) {
|
537 | ffd39257 | blueswir1 | case SM501_SYSTEM_CONTROL:
|
538 | ffd39257 | blueswir1 | ret = s->system_control; |
539 | ffd39257 | blueswir1 | break;
|
540 | ffd39257 | blueswir1 | case SM501_MISC_CONTROL:
|
541 | ffd39257 | blueswir1 | ret = s->misc_control; |
542 | ffd39257 | blueswir1 | break;
|
543 | ffd39257 | blueswir1 | case SM501_GPIO31_0_CONTROL:
|
544 | ffd39257 | blueswir1 | ret = s->gpio_31_0_control; |
545 | ffd39257 | blueswir1 | break;
|
546 | ffd39257 | blueswir1 | case SM501_GPIO63_32_CONTROL:
|
547 | ffd39257 | blueswir1 | ret = s->gpio_63_32_control; |
548 | ffd39257 | blueswir1 | break;
|
549 | ffd39257 | blueswir1 | case SM501_DEVICEID:
|
550 | ffd39257 | blueswir1 | ret = 0x050100A0;
|
551 | ffd39257 | blueswir1 | break;
|
552 | ffd39257 | blueswir1 | case SM501_DRAM_CONTROL:
|
553 | ffd39257 | blueswir1 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
554 | ffd39257 | blueswir1 | break;
|
555 | ffd39257 | blueswir1 | case SM501_IRQ_MASK:
|
556 | ffd39257 | blueswir1 | ret = s->irq_mask; |
557 | ffd39257 | blueswir1 | break;
|
558 | ffd39257 | blueswir1 | case SM501_MISC_TIMING:
|
559 | ffd39257 | blueswir1 | /* TODO : simulate gate control */
|
560 | ffd39257 | blueswir1 | ret = s->misc_timing; |
561 | ffd39257 | blueswir1 | break;
|
562 | ffd39257 | blueswir1 | case SM501_CURRENT_GATE:
|
563 | ffd39257 | blueswir1 | /* TODO : simulate gate control */
|
564 | ffd39257 | blueswir1 | ret = 0x00021807;
|
565 | ffd39257 | blueswir1 | break;
|
566 | ffd39257 | blueswir1 | case SM501_CURRENT_CLOCK:
|
567 | ffd39257 | blueswir1 | ret = 0x2A1A0A09;
|
568 | ffd39257 | blueswir1 | break;
|
569 | ffd39257 | blueswir1 | case SM501_POWER_MODE_CONTROL:
|
570 | ffd39257 | blueswir1 | ret = s->power_mode_control; |
571 | ffd39257 | blueswir1 | break;
|
572 | ffd39257 | blueswir1 | |
573 | ffd39257 | blueswir1 | default:
|
574 | ffd39257 | blueswir1 | printf("sm501 system config : not implemented register read."
|
575 | 8da3ff18 | pbrook | " addr=%x\n", (int)addr); |
576 | ffd39257 | blueswir1 | assert(0);
|
577 | ffd39257 | blueswir1 | } |
578 | ffd39257 | blueswir1 | |
579 | ffd39257 | blueswir1 | return ret;
|
580 | ffd39257 | blueswir1 | } |
581 | ffd39257 | blueswir1 | |
582 | ffd39257 | blueswir1 | static void sm501_system_config_write(void *opaque, |
583 | ffd39257 | blueswir1 | target_phys_addr_t addr, uint32_t value) |
584 | ffd39257 | blueswir1 | { |
585 | ffd39257 | blueswir1 | SM501State * s = (SM501State *)opaque; |
586 | 8da3ff18 | pbrook | SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
|
587 | 8da3ff18 | pbrook | addr, value); |
588 | ffd39257 | blueswir1 | |
589 | 8da3ff18 | pbrook | switch(addr) {
|
590 | ffd39257 | blueswir1 | case SM501_SYSTEM_CONTROL:
|
591 | ffd39257 | blueswir1 | s->system_control = value & 0xE300B8F7;
|
592 | ffd39257 | blueswir1 | break;
|
593 | ffd39257 | blueswir1 | case SM501_MISC_CONTROL:
|
594 | ffd39257 | blueswir1 | s->misc_control = value & 0xFF7FFF20;
|
595 | ffd39257 | blueswir1 | break;
|
596 | ffd39257 | blueswir1 | case SM501_GPIO31_0_CONTROL:
|
597 | ffd39257 | blueswir1 | s->gpio_31_0_control = value; |
598 | ffd39257 | blueswir1 | break;
|
599 | ffd39257 | blueswir1 | case SM501_GPIO63_32_CONTROL:
|
600 | ffd39257 | blueswir1 | s->gpio_63_32_control = value; |
601 | ffd39257 | blueswir1 | break;
|
602 | ffd39257 | blueswir1 | case SM501_DRAM_CONTROL:
|
603 | ffd39257 | blueswir1 | s->local_mem_size_index = (value >> 13) & 0x7; |
604 | ffd39257 | blueswir1 | /* rODO : check validity of size change */
|
605 | ffd39257 | blueswir1 | s->dram_control |= value & 0x7FFFFFC3;
|
606 | ffd39257 | blueswir1 | break;
|
607 | ffd39257 | blueswir1 | case SM501_IRQ_MASK:
|
608 | ffd39257 | blueswir1 | s->irq_mask = value; |
609 | ffd39257 | blueswir1 | break;
|
610 | ffd39257 | blueswir1 | case SM501_MISC_TIMING:
|
611 | ffd39257 | blueswir1 | s->misc_timing = value & 0xF31F1FFF;
|
612 | ffd39257 | blueswir1 | break;
|
613 | ffd39257 | blueswir1 | case SM501_POWER_MODE_0_GATE:
|
614 | ffd39257 | blueswir1 | case SM501_POWER_MODE_1_GATE:
|
615 | ffd39257 | blueswir1 | case SM501_POWER_MODE_0_CLOCK:
|
616 | ffd39257 | blueswir1 | case SM501_POWER_MODE_1_CLOCK:
|
617 | ffd39257 | blueswir1 | /* TODO : simulate gate & clock control */
|
618 | ffd39257 | blueswir1 | break;
|
619 | ffd39257 | blueswir1 | case SM501_POWER_MODE_CONTROL:
|
620 | ffd39257 | blueswir1 | s->power_mode_control = value & 0x00000003;
|
621 | ffd39257 | blueswir1 | break;
|
622 | ffd39257 | blueswir1 | |
623 | ffd39257 | blueswir1 | default:
|
624 | ffd39257 | blueswir1 | printf("sm501 system config : not implemented register write."
|
625 | 8da3ff18 | pbrook | " addr=%x, val=%x\n", (int)addr, value); |
626 | ffd39257 | blueswir1 | assert(0);
|
627 | ffd39257 | blueswir1 | } |
628 | ffd39257 | blueswir1 | } |
629 | ffd39257 | blueswir1 | |
630 | ffd39257 | blueswir1 | static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
|
631 | ffd39257 | blueswir1 | NULL,
|
632 | ffd39257 | blueswir1 | NULL,
|
633 | ffd39257 | blueswir1 | &sm501_system_config_read, |
634 | ffd39257 | blueswir1 | }; |
635 | ffd39257 | blueswir1 | |
636 | ffd39257 | blueswir1 | static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
|
637 | ffd39257 | blueswir1 | NULL,
|
638 | ffd39257 | blueswir1 | NULL,
|
639 | ffd39257 | blueswir1 | &sm501_system_config_write, |
640 | ffd39257 | blueswir1 | }; |
641 | ffd39257 | blueswir1 | |
642 | 486579de | balrog | static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) |
643 | 486579de | balrog | { |
644 | 486579de | balrog | SM501State * s = (SM501State *)opaque; |
645 | 486579de | balrog | SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
646 | 486579de | balrog | |
647 | 486579de | balrog | /* TODO : consider BYTE/WORD access */
|
648 | 486579de | balrog | /* TODO : consider endian */
|
649 | 486579de | balrog | |
650 | 486579de | balrog | assert(0 <= addr && addr < 0x400 * 3); |
651 | 486579de | balrog | return *(uint32_t*)&s->dc_palette[addr];
|
652 | 486579de | balrog | } |
653 | 486579de | balrog | |
654 | 486579de | balrog | static void sm501_palette_write(void *opaque, |
655 | 486579de | balrog | target_phys_addr_t addr, uint32_t value) |
656 | 486579de | balrog | { |
657 | 486579de | balrog | SM501State * s = (SM501State *)opaque; |
658 | 486579de | balrog | SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
|
659 | 486579de | balrog | (int)addr, value);
|
660 | 486579de | balrog | |
661 | 486579de | balrog | /* TODO : consider BYTE/WORD access */
|
662 | 486579de | balrog | /* TODO : consider endian */
|
663 | 486579de | balrog | |
664 | 486579de | balrog | assert(0 <= addr && addr < 0x400 * 3); |
665 | 486579de | balrog | *(uint32_t*)&s->dc_palette[addr] = value; |
666 | 486579de | balrog | } |
667 | 486579de | balrog | |
668 | 8da3ff18 | pbrook | static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) |
669 | ffd39257 | blueswir1 | { |
670 | ffd39257 | blueswir1 | SM501State * s = (SM501State *)opaque; |
671 | ffd39257 | blueswir1 | uint32_t ret = 0;
|
672 | 8da3ff18 | pbrook | SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); |
673 | ffd39257 | blueswir1 | |
674 | 8da3ff18 | pbrook | switch(addr) {
|
675 | ffd39257 | blueswir1 | |
676 | ffd39257 | blueswir1 | case SM501_DC_PANEL_CONTROL:
|
677 | ffd39257 | blueswir1 | ret = s->dc_panel_control; |
678 | ffd39257 | blueswir1 | break;
|
679 | ffd39257 | blueswir1 | case SM501_DC_PANEL_PANNING_CONTROL:
|
680 | ffd39257 | blueswir1 | ret = s->dc_panel_panning_control; |
681 | ffd39257 | blueswir1 | break;
|
682 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_ADDR:
|
683 | ffd39257 | blueswir1 | ret = s->dc_panel_fb_addr; |
684 | ffd39257 | blueswir1 | break;
|
685 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_OFFSET:
|
686 | ffd39257 | blueswir1 | ret = s->dc_panel_fb_offset; |
687 | ffd39257 | blueswir1 | break;
|
688 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_WIDTH:
|
689 | ffd39257 | blueswir1 | ret = s->dc_panel_fb_width; |
690 | ffd39257 | blueswir1 | break;
|
691 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_HEIGHT:
|
692 | ffd39257 | blueswir1 | ret = s->dc_panel_fb_height; |
693 | ffd39257 | blueswir1 | break;
|
694 | ffd39257 | blueswir1 | case SM501_DC_PANEL_TL_LOC:
|
695 | ffd39257 | blueswir1 | ret = s->dc_panel_tl_location; |
696 | ffd39257 | blueswir1 | break;
|
697 | ffd39257 | blueswir1 | case SM501_DC_PANEL_BR_LOC:
|
698 | ffd39257 | blueswir1 | ret = s->dc_panel_br_location; |
699 | ffd39257 | blueswir1 | break;
|
700 | ffd39257 | blueswir1 | |
701 | ffd39257 | blueswir1 | case SM501_DC_PANEL_H_TOT:
|
702 | ffd39257 | blueswir1 | ret = s->dc_panel_h_total; |
703 | ffd39257 | blueswir1 | break;
|
704 | ffd39257 | blueswir1 | case SM501_DC_PANEL_H_SYNC:
|
705 | ffd39257 | blueswir1 | ret = s->dc_panel_h_sync; |
706 | ffd39257 | blueswir1 | break;
|
707 | ffd39257 | blueswir1 | case SM501_DC_PANEL_V_TOT:
|
708 | ffd39257 | blueswir1 | ret = s->dc_panel_v_total; |
709 | ffd39257 | blueswir1 | break;
|
710 | ffd39257 | blueswir1 | case SM501_DC_PANEL_V_SYNC:
|
711 | ffd39257 | blueswir1 | ret = s->dc_panel_v_sync; |
712 | ffd39257 | blueswir1 | break;
|
713 | ffd39257 | blueswir1 | |
714 | ffd39257 | blueswir1 | case SM501_DC_CRT_CONTROL:
|
715 | ffd39257 | blueswir1 | ret = s->dc_crt_control; |
716 | ffd39257 | blueswir1 | break;
|
717 | ffd39257 | blueswir1 | case SM501_DC_CRT_FB_ADDR:
|
718 | ffd39257 | blueswir1 | ret = s->dc_crt_fb_addr; |
719 | ffd39257 | blueswir1 | break;
|
720 | ffd39257 | blueswir1 | case SM501_DC_CRT_FB_OFFSET:
|
721 | ffd39257 | blueswir1 | ret = s->dc_crt_fb_offset; |
722 | ffd39257 | blueswir1 | break;
|
723 | ffd39257 | blueswir1 | case SM501_DC_CRT_H_TOT:
|
724 | ffd39257 | blueswir1 | ret = s->dc_crt_h_total; |
725 | ffd39257 | blueswir1 | break;
|
726 | ffd39257 | blueswir1 | case SM501_DC_CRT_H_SYNC:
|
727 | ffd39257 | blueswir1 | ret = s->dc_crt_h_sync; |
728 | ffd39257 | blueswir1 | break;
|
729 | ffd39257 | blueswir1 | case SM501_DC_CRT_V_TOT:
|
730 | ffd39257 | blueswir1 | ret = s->dc_crt_v_total; |
731 | ffd39257 | blueswir1 | break;
|
732 | ffd39257 | blueswir1 | case SM501_DC_CRT_V_SYNC:
|
733 | ffd39257 | blueswir1 | ret = s->dc_crt_v_sync; |
734 | ffd39257 | blueswir1 | break;
|
735 | ffd39257 | blueswir1 | |
736 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_ADDR:
|
737 | ffd39257 | blueswir1 | ret = s->dc_crt_hwc_addr; |
738 | ffd39257 | blueswir1 | break;
|
739 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_LOC:
|
740 | ffd39257 | blueswir1 | ret = s->dc_crt_hwc_addr; |
741 | ffd39257 | blueswir1 | break;
|
742 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_COLOR_1_2:
|
743 | ffd39257 | blueswir1 | ret = s->dc_crt_hwc_addr; |
744 | ffd39257 | blueswir1 | break;
|
745 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_COLOR_3:
|
746 | ffd39257 | blueswir1 | ret = s->dc_crt_hwc_addr; |
747 | ffd39257 | blueswir1 | break;
|
748 | ffd39257 | blueswir1 | |
749 | 486579de | balrog | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: |
750 | 486579de | balrog | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
751 | 486579de | balrog | break;
|
752 | 486579de | balrog | |
753 | ffd39257 | blueswir1 | default:
|
754 | ffd39257 | blueswir1 | printf("sm501 disp ctrl : not implemented register read."
|
755 | 8da3ff18 | pbrook | " addr=%x\n", (int)addr); |
756 | ffd39257 | blueswir1 | assert(0);
|
757 | ffd39257 | blueswir1 | } |
758 | ffd39257 | blueswir1 | |
759 | ffd39257 | blueswir1 | return ret;
|
760 | ffd39257 | blueswir1 | } |
761 | ffd39257 | blueswir1 | |
762 | ffd39257 | blueswir1 | static void sm501_disp_ctrl_write(void *opaque, |
763 | ffd39257 | blueswir1 | target_phys_addr_t addr, |
764 | ffd39257 | blueswir1 | uint32_t value) |
765 | ffd39257 | blueswir1 | { |
766 | ffd39257 | blueswir1 | SM501State * s = (SM501State *)opaque; |
767 | 8da3ff18 | pbrook | SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
|
768 | 8da3ff18 | pbrook | addr, value); |
769 | ffd39257 | blueswir1 | |
770 | 8da3ff18 | pbrook | switch(addr) {
|
771 | ffd39257 | blueswir1 | case SM501_DC_PANEL_CONTROL:
|
772 | ffd39257 | blueswir1 | s->dc_panel_control = value & 0x0FFF73FF;
|
773 | ffd39257 | blueswir1 | break;
|
774 | ffd39257 | blueswir1 | case SM501_DC_PANEL_PANNING_CONTROL:
|
775 | ffd39257 | blueswir1 | s->dc_panel_panning_control = value & 0xFF3FFF3F;
|
776 | ffd39257 | blueswir1 | break;
|
777 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_ADDR:
|
778 | ffd39257 | blueswir1 | s->dc_panel_fb_addr = value & 0x8FFFFFF0;
|
779 | ffd39257 | blueswir1 | break;
|
780 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_OFFSET:
|
781 | ffd39257 | blueswir1 | s->dc_panel_fb_offset = value & 0x3FF03FF0;
|
782 | ffd39257 | blueswir1 | break;
|
783 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_WIDTH:
|
784 | ffd39257 | blueswir1 | s->dc_panel_fb_width = value & 0x0FFF0FFF;
|
785 | ffd39257 | blueswir1 | break;
|
786 | ffd39257 | blueswir1 | case SM501_DC_PANEL_FB_HEIGHT:
|
787 | ffd39257 | blueswir1 | s->dc_panel_fb_height = value & 0x0FFF0FFF;
|
788 | ffd39257 | blueswir1 | break;
|
789 | ffd39257 | blueswir1 | case SM501_DC_PANEL_TL_LOC:
|
790 | ffd39257 | blueswir1 | s->dc_panel_tl_location = value & 0x07FF07FF;
|
791 | ffd39257 | blueswir1 | break;
|
792 | ffd39257 | blueswir1 | case SM501_DC_PANEL_BR_LOC:
|
793 | ffd39257 | blueswir1 | s->dc_panel_br_location = value & 0x07FF07FF;
|
794 | ffd39257 | blueswir1 | break;
|
795 | ffd39257 | blueswir1 | |
796 | ffd39257 | blueswir1 | case SM501_DC_PANEL_H_TOT:
|
797 | ffd39257 | blueswir1 | s->dc_panel_h_total = value & 0x0FFF0FFF;
|
798 | ffd39257 | blueswir1 | break;
|
799 | ffd39257 | blueswir1 | case SM501_DC_PANEL_H_SYNC:
|
800 | ffd39257 | blueswir1 | s->dc_panel_h_sync = value & 0x00FF0FFF;
|
801 | ffd39257 | blueswir1 | break;
|
802 | ffd39257 | blueswir1 | case SM501_DC_PANEL_V_TOT:
|
803 | ffd39257 | blueswir1 | s->dc_panel_v_total = value & 0x0FFF0FFF;
|
804 | ffd39257 | blueswir1 | break;
|
805 | ffd39257 | blueswir1 | case SM501_DC_PANEL_V_SYNC:
|
806 | ffd39257 | blueswir1 | s->dc_panel_v_sync = value & 0x003F0FFF;
|
807 | ffd39257 | blueswir1 | break;
|
808 | ffd39257 | blueswir1 | |
809 | ffd39257 | blueswir1 | case SM501_DC_PANEL_HWC_ADDR:
|
810 | ffd39257 | blueswir1 | s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
|
811 | ffd39257 | blueswir1 | break;
|
812 | ffd39257 | blueswir1 | case SM501_DC_PANEL_HWC_LOC:
|
813 | ffd39257 | blueswir1 | s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
|
814 | ffd39257 | blueswir1 | break;
|
815 | ffd39257 | blueswir1 | case SM501_DC_PANEL_HWC_COLOR_1_2:
|
816 | ffd39257 | blueswir1 | s->dc_panel_hwc_addr = value; |
817 | ffd39257 | blueswir1 | break;
|
818 | ffd39257 | blueswir1 | case SM501_DC_PANEL_HWC_COLOR_3:
|
819 | ffd39257 | blueswir1 | s->dc_panel_hwc_addr = value & 0x0000FFFF;
|
820 | ffd39257 | blueswir1 | break;
|
821 | ffd39257 | blueswir1 | |
822 | ffd39257 | blueswir1 | case SM501_DC_CRT_CONTROL:
|
823 | ffd39257 | blueswir1 | s->dc_crt_control = value & 0x0003FFFF;
|
824 | ffd39257 | blueswir1 | break;
|
825 | ffd39257 | blueswir1 | case SM501_DC_CRT_FB_ADDR:
|
826 | ffd39257 | blueswir1 | s->dc_crt_fb_addr = value & 0x8FFFFFF0;
|
827 | ffd39257 | blueswir1 | break;
|
828 | ffd39257 | blueswir1 | case SM501_DC_CRT_FB_OFFSET:
|
829 | ffd39257 | blueswir1 | s->dc_crt_fb_offset = value & 0x3FF03FF0;
|
830 | ffd39257 | blueswir1 | break;
|
831 | ffd39257 | blueswir1 | case SM501_DC_CRT_H_TOT:
|
832 | ffd39257 | blueswir1 | s->dc_crt_h_total = value & 0x0FFF0FFF;
|
833 | ffd39257 | blueswir1 | break;
|
834 | ffd39257 | blueswir1 | case SM501_DC_CRT_H_SYNC:
|
835 | ffd39257 | blueswir1 | s->dc_crt_h_sync = value & 0x00FF0FFF;
|
836 | ffd39257 | blueswir1 | break;
|
837 | ffd39257 | blueswir1 | case SM501_DC_CRT_V_TOT:
|
838 | ffd39257 | blueswir1 | s->dc_crt_v_total = value & 0x0FFF0FFF;
|
839 | ffd39257 | blueswir1 | break;
|
840 | ffd39257 | blueswir1 | case SM501_DC_CRT_V_SYNC:
|
841 | ffd39257 | blueswir1 | s->dc_crt_v_sync = value & 0x003F0FFF;
|
842 | ffd39257 | blueswir1 | break;
|
843 | ffd39257 | blueswir1 | |
844 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_ADDR:
|
845 | ffd39257 | blueswir1 | s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
|
846 | ffd39257 | blueswir1 | break;
|
847 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_LOC:
|
848 | ffd39257 | blueswir1 | s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
|
849 | ffd39257 | blueswir1 | break;
|
850 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_COLOR_1_2:
|
851 | ffd39257 | blueswir1 | s->dc_crt_hwc_addr = value; |
852 | ffd39257 | blueswir1 | break;
|
853 | ffd39257 | blueswir1 | case SM501_DC_CRT_HWC_COLOR_3:
|
854 | ffd39257 | blueswir1 | s->dc_crt_hwc_addr = value & 0x0000FFFF;
|
855 | ffd39257 | blueswir1 | break;
|
856 | ffd39257 | blueswir1 | |
857 | 486579de | balrog | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: |
858 | 486579de | balrog | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
859 | 486579de | balrog | break;
|
860 | 486579de | balrog | |
861 | ffd39257 | blueswir1 | default:
|
862 | ffd39257 | blueswir1 | printf("sm501 disp ctrl : not implemented register write."
|
863 | 8da3ff18 | pbrook | " addr=%x, val=%x\n", (int)addr, value); |
864 | ffd39257 | blueswir1 | assert(0);
|
865 | ffd39257 | blueswir1 | } |
866 | ffd39257 | blueswir1 | } |
867 | ffd39257 | blueswir1 | |
868 | ffd39257 | blueswir1 | static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
|
869 | ffd39257 | blueswir1 | NULL,
|
870 | ffd39257 | blueswir1 | NULL,
|
871 | ffd39257 | blueswir1 | &sm501_disp_ctrl_read, |
872 | ffd39257 | blueswir1 | }; |
873 | ffd39257 | blueswir1 | |
874 | ffd39257 | blueswir1 | static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
|
875 | ffd39257 | blueswir1 | NULL,
|
876 | ffd39257 | blueswir1 | NULL,
|
877 | ffd39257 | blueswir1 | &sm501_disp_ctrl_write, |
878 | ffd39257 | blueswir1 | }; |
879 | ffd39257 | blueswir1 | |
880 | ffd39257 | blueswir1 | /* draw line functions for all console modes */
|
881 | ffd39257 | blueswir1 | |
882 | ffd39257 | blueswir1 | #include "pixel_ops.h" |
883 | ffd39257 | blueswir1 | |
884 | ffd39257 | blueswir1 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
885 | ffd39257 | blueswir1 | int width, const uint32_t *pal); |
886 | ffd39257 | blueswir1 | |
887 | ffd39257 | blueswir1 | #define DEPTH 8 |
888 | ffd39257 | blueswir1 | #include "sm501_template.h" |
889 | ffd39257 | blueswir1 | |
890 | ffd39257 | blueswir1 | #define DEPTH 15 |
891 | ffd39257 | blueswir1 | #include "sm501_template.h" |
892 | ffd39257 | blueswir1 | |
893 | ffd39257 | blueswir1 | #define BGR_FORMAT
|
894 | ffd39257 | blueswir1 | #define DEPTH 15 |
895 | ffd39257 | blueswir1 | #include "sm501_template.h" |
896 | ffd39257 | blueswir1 | |
897 | ffd39257 | blueswir1 | #define DEPTH 16 |
898 | ffd39257 | blueswir1 | #include "sm501_template.h" |
899 | ffd39257 | blueswir1 | |
900 | ffd39257 | blueswir1 | #define BGR_FORMAT
|
901 | ffd39257 | blueswir1 | #define DEPTH 16 |
902 | ffd39257 | blueswir1 | #include "sm501_template.h" |
903 | ffd39257 | blueswir1 | |
904 | ffd39257 | blueswir1 | #define DEPTH 32 |
905 | ffd39257 | blueswir1 | #include "sm501_template.h" |
906 | ffd39257 | blueswir1 | |
907 | ffd39257 | blueswir1 | #define BGR_FORMAT
|
908 | ffd39257 | blueswir1 | #define DEPTH 32 |
909 | ffd39257 | blueswir1 | #include "sm501_template.h" |
910 | ffd39257 | blueswir1 | |
911 | ffd39257 | blueswir1 | static draw_line_func * draw_line8_funcs[] = {
|
912 | ffd39257 | blueswir1 | draw_line8_8, |
913 | ffd39257 | blueswir1 | draw_line8_15, |
914 | ffd39257 | blueswir1 | draw_line8_16, |
915 | ffd39257 | blueswir1 | draw_line8_32, |
916 | ffd39257 | blueswir1 | draw_line8_32bgr, |
917 | ffd39257 | blueswir1 | draw_line8_15bgr, |
918 | ffd39257 | blueswir1 | draw_line8_16bgr, |
919 | ffd39257 | blueswir1 | }; |
920 | ffd39257 | blueswir1 | |
921 | ffd39257 | blueswir1 | static draw_line_func * draw_line16_funcs[] = {
|
922 | ffd39257 | blueswir1 | draw_line16_8, |
923 | ffd39257 | blueswir1 | draw_line16_15, |
924 | ffd39257 | blueswir1 | draw_line16_16, |
925 | ffd39257 | blueswir1 | draw_line16_32, |
926 | ffd39257 | blueswir1 | draw_line16_32bgr, |
927 | ffd39257 | blueswir1 | draw_line16_15bgr, |
928 | ffd39257 | blueswir1 | draw_line16_16bgr, |
929 | ffd39257 | blueswir1 | }; |
930 | ffd39257 | blueswir1 | |
931 | ffd39257 | blueswir1 | static draw_line_func * draw_line32_funcs[] = {
|
932 | ffd39257 | blueswir1 | draw_line32_8, |
933 | ffd39257 | blueswir1 | draw_line32_15, |
934 | ffd39257 | blueswir1 | draw_line32_16, |
935 | ffd39257 | blueswir1 | draw_line32_32, |
936 | ffd39257 | blueswir1 | draw_line32_32bgr, |
937 | ffd39257 | blueswir1 | draw_line32_15bgr, |
938 | ffd39257 | blueswir1 | draw_line32_16bgr, |
939 | ffd39257 | blueswir1 | }; |
940 | ffd39257 | blueswir1 | |
941 | ffd39257 | blueswir1 | static inline int get_depth_index(DisplayState *s) |
942 | ffd39257 | blueswir1 | { |
943 | ffd39257 | blueswir1 | switch(s->depth) {
|
944 | ffd39257 | blueswir1 | default:
|
945 | ffd39257 | blueswir1 | case 8: |
946 | ffd39257 | blueswir1 | return 0; |
947 | ffd39257 | blueswir1 | case 15: |
948 | ffd39257 | blueswir1 | if (s->bgr)
|
949 | ffd39257 | blueswir1 | return 5; |
950 | ffd39257 | blueswir1 | else
|
951 | ffd39257 | blueswir1 | return 1; |
952 | ffd39257 | blueswir1 | case 16: |
953 | ffd39257 | blueswir1 | if (s->bgr)
|
954 | ffd39257 | blueswir1 | return 6; |
955 | ffd39257 | blueswir1 | else
|
956 | ffd39257 | blueswir1 | return 2; |
957 | ffd39257 | blueswir1 | case 32: |
958 | ffd39257 | blueswir1 | if (s->bgr)
|
959 | ffd39257 | blueswir1 | return 4; |
960 | ffd39257 | blueswir1 | else
|
961 | ffd39257 | blueswir1 | return 3; |
962 | ffd39257 | blueswir1 | } |
963 | ffd39257 | blueswir1 | } |
964 | ffd39257 | blueswir1 | |
965 | ffd39257 | blueswir1 | static void sm501_draw_crt(SM501State * s) |
966 | ffd39257 | blueswir1 | { |
967 | ffd39257 | blueswir1 | int y;
|
968 | ffd39257 | blueswir1 | int width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
969 | ffd39257 | blueswir1 | int height = (s->dc_crt_v_total & 0x00000FFF) + 1; |
970 | ffd39257 | blueswir1 | |
971 | ffd39257 | blueswir1 | uint8_t * src = s->local_mem; |
972 | ffd39257 | blueswir1 | int src_bpp = 0; |
973 | ffd39257 | blueswir1 | int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0); |
974 | ffd39257 | blueswir1 | uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE |
975 | ffd39257 | blueswir1 | - SM501_DC_PANEL_PALETTE]; |
976 | ffd39257 | blueswir1 | int ds_depth_index = get_depth_index(s->ds);
|
977 | ffd39257 | blueswir1 | draw_line_func * draw_line = NULL;
|
978 | ffd39257 | blueswir1 | int full_update = 0; |
979 | ffd39257 | blueswir1 | int y_start = -1; |
980 | ffd39257 | blueswir1 | int page_min = 0x7fffffff; |
981 | ffd39257 | blueswir1 | int page_max = -1; |
982 | ffd39257 | blueswir1 | |
983 | ffd39257 | blueswir1 | /* choose draw_line function */
|
984 | ffd39257 | blueswir1 | switch (s->dc_crt_control & 3) { |
985 | ffd39257 | blueswir1 | case SM501_DC_CRT_CONTROL_8BPP:
|
986 | ffd39257 | blueswir1 | src_bpp = 1;
|
987 | ffd39257 | blueswir1 | draw_line = draw_line8_funcs[ds_depth_index]; |
988 | ffd39257 | blueswir1 | break;
|
989 | ffd39257 | blueswir1 | case SM501_DC_CRT_CONTROL_16BPP:
|
990 | ffd39257 | blueswir1 | src_bpp = 2;
|
991 | ffd39257 | blueswir1 | draw_line = draw_line16_funcs[ds_depth_index]; |
992 | ffd39257 | blueswir1 | break;
|
993 | ffd39257 | blueswir1 | case SM501_DC_CRT_CONTROL_32BPP:
|
994 | ffd39257 | blueswir1 | src_bpp = 4;
|
995 | ffd39257 | blueswir1 | draw_line = draw_line32_funcs[ds_depth_index]; |
996 | ffd39257 | blueswir1 | break;
|
997 | ffd39257 | blueswir1 | default:
|
998 | ffd39257 | blueswir1 | printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
|
999 | ffd39257 | blueswir1 | s->dc_crt_control); |
1000 | ffd39257 | blueswir1 | assert(0);
|
1001 | ffd39257 | blueswir1 | break;
|
1002 | ffd39257 | blueswir1 | } |
1003 | ffd39257 | blueswir1 | |
1004 | ffd39257 | blueswir1 | /* adjust console size */
|
1005 | ffd39257 | blueswir1 | if (s->last_width != width || s->last_height != height) {
|
1006 | ffd39257 | blueswir1 | qemu_console_resize(s->console, width, height); |
1007 | ffd39257 | blueswir1 | s->last_width = width; |
1008 | ffd39257 | blueswir1 | s->last_height = height; |
1009 | ffd39257 | blueswir1 | full_update = 1;
|
1010 | ffd39257 | blueswir1 | } |
1011 | ffd39257 | blueswir1 | |
1012 | ffd39257 | blueswir1 | /* draw each line according to conditions */
|
1013 | ffd39257 | blueswir1 | for (y = 0; y < height; y++) { |
1014 | ffd39257 | blueswir1 | int update = full_update;
|
1015 | ffd39257 | blueswir1 | uint8_t * line_end = &src[width * src_bpp - 1];
|
1016 | ffd39257 | blueswir1 | int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
|
1017 | ffd39257 | blueswir1 | int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
|
1018 | ffd39257 | blueswir1 | int page;
|
1019 | ffd39257 | blueswir1 | |
1020 | ffd39257 | blueswir1 | /* check dirty flags for each line */
|
1021 | ffd39257 | blueswir1 | for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
|
1022 | ffd39257 | blueswir1 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
|
1023 | ffd39257 | blueswir1 | update = 1;
|
1024 | ffd39257 | blueswir1 | |
1025 | ffd39257 | blueswir1 | /* draw line and change status */
|
1026 | ffd39257 | blueswir1 | if (update) {
|
1027 | ffd39257 | blueswir1 | draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette); |
1028 | ffd39257 | blueswir1 | if (y_start < 0) |
1029 | ffd39257 | blueswir1 | y_start = y; |
1030 | ffd39257 | blueswir1 | if (page0 < page_min)
|
1031 | ffd39257 | blueswir1 | page_min = page0; |
1032 | ffd39257 | blueswir1 | if (page1 > page_max)
|
1033 | ffd39257 | blueswir1 | page_max = page1; |
1034 | ffd39257 | blueswir1 | } else {
|
1035 | ffd39257 | blueswir1 | if (y_start >= 0) { |
1036 | ffd39257 | blueswir1 | /* flush to display */
|
1037 | ffd39257 | blueswir1 | dpy_update(s->ds, 0, y_start, width, y - y_start);
|
1038 | ffd39257 | blueswir1 | y_start = -1;
|
1039 | ffd39257 | blueswir1 | } |
1040 | ffd39257 | blueswir1 | } |
1041 | ffd39257 | blueswir1 | |
1042 | ffd39257 | blueswir1 | src += width * src_bpp; |
1043 | ffd39257 | blueswir1 | } |
1044 | ffd39257 | blueswir1 | |
1045 | ffd39257 | blueswir1 | /* complete flush to display */
|
1046 | ffd39257 | blueswir1 | if (y_start >= 0) |
1047 | ffd39257 | blueswir1 | dpy_update(s->ds, 0, y_start, width, y - y_start);
|
1048 | ffd39257 | blueswir1 | |
1049 | ffd39257 | blueswir1 | /* clear dirty flags */
|
1050 | ffd39257 | blueswir1 | if (page_max != -1) |
1051 | ffd39257 | blueswir1 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
1052 | ffd39257 | blueswir1 | VGA_DIRTY_FLAG); |
1053 | ffd39257 | blueswir1 | } |
1054 | ffd39257 | blueswir1 | |
1055 | ffd39257 | blueswir1 | static void sm501_update_display(void *opaque) |
1056 | ffd39257 | blueswir1 | { |
1057 | ffd39257 | blueswir1 | SM501State * s = (SM501State *)opaque; |
1058 | ffd39257 | blueswir1 | |
1059 | ffd39257 | blueswir1 | if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
|
1060 | ffd39257 | blueswir1 | sm501_draw_crt(s); |
1061 | ffd39257 | blueswir1 | } |
1062 | ffd39257 | blueswir1 | |
1063 | ffd39257 | blueswir1 | void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base, |
1064 | ffd39257 | blueswir1 | uint32_t local_mem_bytes, CharDriverState *chr) |
1065 | ffd39257 | blueswir1 | { |
1066 | ffd39257 | blueswir1 | SM501State * s; |
1067 | ffd39257 | blueswir1 | int sm501_system_config_index;
|
1068 | ffd39257 | blueswir1 | int sm501_disp_ctrl_index;
|
1069 | ffd39257 | blueswir1 | |
1070 | ffd39257 | blueswir1 | /* allocate management data region */
|
1071 | ffd39257 | blueswir1 | s = (SM501State *)qemu_mallocz(sizeof(SM501State));
|
1072 | ffd39257 | blueswir1 | s->base = base; |
1073 | ffd39257 | blueswir1 | s->local_mem_size_index |
1074 | ffd39257 | blueswir1 | = get_local_mem_size_index(local_mem_bytes); |
1075 | ffd39257 | blueswir1 | SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
|
1076 | ffd39257 | blueswir1 | s->local_mem_size_index); |
1077 | ffd39257 | blueswir1 | s->system_control = 0x00100000;
|
1078 | ffd39257 | blueswir1 | s->misc_control = 0x00001000; /* assumes SH, active=low */ |
1079 | ffd39257 | blueswir1 | s->dc_panel_control = 0x00010000;
|
1080 | ffd39257 | blueswir1 | s->dc_crt_control = 0x00010000;
|
1081 | ffd39257 | blueswir1 | s->ds = ds; |
1082 | ffd39257 | blueswir1 | |
1083 | ffd39257 | blueswir1 | /* allocate local memory */
|
1084 | ffd39257 | blueswir1 | s->local_mem = (uint8 *)phys_ram_base + local_mem_base; |
1085 | ffd39257 | blueswir1 | cpu_register_physical_memory(base, local_mem_bytes, local_mem_base); |
1086 | ffd39257 | blueswir1 | |
1087 | ffd39257 | blueswir1 | /* map mmio */
|
1088 | ffd39257 | blueswir1 | sm501_system_config_index |
1089 | ffd39257 | blueswir1 | = cpu_register_io_memory(0, sm501_system_config_readfn,
|
1090 | ffd39257 | blueswir1 | sm501_system_config_writefn, s); |
1091 | ffd39257 | blueswir1 | cpu_register_physical_memory(base + MMIO_BASE_OFFSET, |
1092 | ffd39257 | blueswir1 | 0x6c, sm501_system_config_index);
|
1093 | ffd39257 | blueswir1 | sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
|
1094 | ffd39257 | blueswir1 | sm501_disp_ctrl_writefn, s); |
1095 | ffd39257 | blueswir1 | cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, |
1096 | 486579de | balrog | 0x1000, sm501_disp_ctrl_index);
|
1097 | ffd39257 | blueswir1 | |
1098 | ffd39257 | blueswir1 | /* bridge to serial emulation module */
|
1099 | ffd39257 | blueswir1 | if (chr)
|
1100 | ffd39257 | blueswir1 | serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
|
1101 | ffd39257 | blueswir1 | 0, /* TODO : chain irq to IRL */ |
1102 | ffd39257 | blueswir1 | 115200, chr, 1); |
1103 | ffd39257 | blueswir1 | |
1104 | ffd39257 | blueswir1 | /* create qemu graphic console */
|
1105 | ffd39257 | blueswir1 | s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
|
1106 | ffd39257 | blueswir1 | NULL, NULL, s); |
1107 | ffd39257 | blueswir1 | } |