root / hw / soc_dma.h @ 59d94130
History | View | Annotate | Download (3.6 kB)
1 | afbb5194 | balrog | /*
|
---|---|---|---|
2 | afbb5194 | balrog | * On-chip DMA controller framework.
|
3 | afbb5194 | balrog | *
|
4 | afbb5194 | balrog | * Copyright (C) 2008 Nokia Corporation
|
5 | afbb5194 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
|
6 | afbb5194 | balrog | *
|
7 | afbb5194 | balrog | * This program is free software; you can redistribute it and/or
|
8 | afbb5194 | balrog | * modify it under the terms of the GNU General Public License as
|
9 | afbb5194 | balrog | * published by the Free Software Foundation; either version 2 or
|
10 | afbb5194 | balrog | * (at your option) version 3 of the License.
|
11 | afbb5194 | balrog | *
|
12 | afbb5194 | balrog | * This program is distributed in the hope that it will be useful,
|
13 | afbb5194 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 | afbb5194 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 | afbb5194 | balrog | * GNU General Public License for more details.
|
16 | afbb5194 | balrog | *
|
17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
|
18 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
|
19 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
20 | afbb5194 | balrog | */
|
21 | afbb5194 | balrog | |
22 | afbb5194 | balrog | struct soc_dma_s;
|
23 | afbb5194 | balrog | struct soc_dma_ch_s;
|
24 | afbb5194 | balrog | typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len); |
25 | afbb5194 | balrog | typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch); |
26 | afbb5194 | balrog | |
27 | afbb5194 | balrog | enum soc_dma_port_type {
|
28 | afbb5194 | balrog | soc_dma_port_mem, |
29 | afbb5194 | balrog | soc_dma_port_fifo, |
30 | afbb5194 | balrog | soc_dma_port_other, |
31 | afbb5194 | balrog | }; |
32 | afbb5194 | balrog | |
33 | afbb5194 | balrog | enum soc_dma_access_type {
|
34 | afbb5194 | balrog | soc_dma_access_const, |
35 | afbb5194 | balrog | soc_dma_access_linear, |
36 | afbb5194 | balrog | soc_dma_access_other, |
37 | afbb5194 | balrog | }; |
38 | afbb5194 | balrog | |
39 | afbb5194 | balrog | struct soc_dma_ch_s {
|
40 | afbb5194 | balrog | /* Private */
|
41 | afbb5194 | balrog | struct soc_dma_s *dma;
|
42 | afbb5194 | balrog | int num;
|
43 | afbb5194 | balrog | QEMUTimer *timer; |
44 | afbb5194 | balrog | |
45 | afbb5194 | balrog | /* Set by soc_dma.c */
|
46 | afbb5194 | balrog | int enable;
|
47 | afbb5194 | balrog | int update;
|
48 | afbb5194 | balrog | |
49 | afbb5194 | balrog | /* This should be set by dma->setup_fn(). */
|
50 | afbb5194 | balrog | int bytes;
|
51 | afbb5194 | balrog | /* Initialised by the DMA module, call soc_dma_ch_update after writing. */
|
52 | afbb5194 | balrog | enum soc_dma_access_type type[2]; |
53 | afbb5194 | balrog | target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */ |
54 | afbb5194 | balrog | /* Private */
|
55 | afbb5194 | balrog | void *paddr[2]; |
56 | afbb5194 | balrog | soc_dma_io_t io_fn[2];
|
57 | afbb5194 | balrog | void *io_opaque[2]; |
58 | afbb5194 | balrog | |
59 | afbb5194 | balrog | int running;
|
60 | afbb5194 | balrog | soc_dma_transfer_t transfer_fn; |
61 | afbb5194 | balrog | |
62 | afbb5194 | balrog | /* Set and used by the DMA module. */
|
63 | afbb5194 | balrog | void *opaque;
|
64 | afbb5194 | balrog | }; |
65 | afbb5194 | balrog | |
66 | afbb5194 | balrog | struct soc_dma_s {
|
67 | afbb5194 | balrog | /* Following fields are set by the SoC DMA module and can be used
|
68 | afbb5194 | balrog | * by anybody. */
|
69 | afbb5194 | balrog | uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
|
70 | afbb5194 | balrog | qemu_irq *drq; |
71 | afbb5194 | balrog | void *opaque;
|
72 | afbb5194 | balrog | int64_t freq; |
73 | afbb5194 | balrog | soc_dma_transfer_t transfer_fn; |
74 | afbb5194 | balrog | soc_dma_transfer_t setup_fn; |
75 | afbb5194 | balrog | /* Set by soc_dma_init() for use by the DMA module. */
|
76 | afbb5194 | balrog | struct soc_dma_ch_s *ch;
|
77 | afbb5194 | balrog | }; |
78 | afbb5194 | balrog | |
79 | afbb5194 | balrog | /* Call to activate or stop a DMA channel. */
|
80 | afbb5194 | balrog | void soc_dma_set_request(struct soc_dma_ch_s *ch, int level); |
81 | afbb5194 | balrog | /* Call after every write to one of the following fields and before
|
82 | afbb5194 | balrog | * calling soc_dma_set_request(ch, 1):
|
83 | afbb5194 | balrog | * ch->type[0...1],
|
84 | afbb5194 | balrog | * ch->vaddr[0...1],
|
85 | afbb5194 | balrog | * ch->paddr[0...1],
|
86 | afbb5194 | balrog | * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
|
87 | afbb5194 | balrog | void soc_dma_ch_update(struct soc_dma_ch_s *ch); |
88 | afbb5194 | balrog | |
89 | afbb5194 | balrog | /* The SoC should call this when the DMA module is being reset. */
|
90 | afbb5194 | balrog | void soc_dma_reset(struct soc_dma_s *s); |
91 | afbb5194 | balrog | struct soc_dma_s *soc_dma_init(int n); |
92 | afbb5194 | balrog | |
93 | afbb5194 | balrog | void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base, |
94 | afbb5194 | balrog | soc_dma_io_t fn, void *opaque, int out); |
95 | afbb5194 | balrog | void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base, |
96 | afbb5194 | balrog | target_phys_addr_t virt_base, size_t size); |
97 | afbb5194 | balrog | |
98 | afbb5194 | balrog | static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, |
99 | afbb5194 | balrog | target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
|
100 | afbb5194 | balrog | { |
101 | afbb5194 | balrog | return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); |
102 | afbb5194 | balrog | } |
103 | afbb5194 | balrog | |
104 | afbb5194 | balrog | static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, |
105 | afbb5194 | balrog | target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
|
106 | afbb5194 | balrog | { |
107 | afbb5194 | balrog | return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); |
108 | afbb5194 | balrog | } |
109 | afbb5194 | balrog | |
110 | afbb5194 | balrog | static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma, |
111 | afbb5194 | balrog | ram_addr_t offset, target_phys_addr_t virt_base, size_t size) |
112 | afbb5194 | balrog | { |
113 | afbb5194 | balrog | return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size);
|
114 | afbb5194 | balrog | } |