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1 | 6643d27e | bellard | /* Print mips instructions for GDB, the GNU debugger, or for objdump.
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2 | 6643d27e | bellard | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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3 | 6643d27e | bellard | 2000, 2001, 2002, 2003
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4 | 6643d27e | bellard | Free Software Foundation, Inc.
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5 | 6643d27e | bellard | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
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6 | 6643d27e | bellard | |
7 | 6643d27e | bellard | This file is part of GDB, GAS, and the GNU binutils.
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8 | 6643d27e | bellard | |
9 | 6643d27e | bellard | This program is free software; you can redistribute it and/or modify
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10 | 6643d27e | bellard | it under the terms of the GNU General Public License as published by
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11 | 6643d27e | bellard | the Free Software Foundation; either version 2 of the License, or
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12 | 6643d27e | bellard | (at your option) any later version.
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13 | 6643d27e | bellard | |
14 | 6643d27e | bellard | This program is distributed in the hope that it will be useful,
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15 | 6643d27e | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 6643d27e | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 6643d27e | bellard | GNU General Public License for more details.
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18 | 6643d27e | bellard | |
19 | 6643d27e | bellard | You should have received a copy of the GNU General Public License
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20 | 6643d27e | bellard | along with this program; if not, write to the Free Software
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21 | fad6cb1a | aurel32 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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22 | fad6cb1a | aurel32 | MA 02110-1301, USA. */
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23 | 6643d27e | bellard | |
24 | 6643d27e | bellard | #include "dis-asm.h" |
25 | 6643d27e | bellard | |
26 | 6643d27e | bellard | /* mips.h. Mips opcode list for GDB, the GNU debugger.
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27 | 6643d27e | bellard | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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28 | 6643d27e | bellard | Free Software Foundation, Inc.
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29 | 6643d27e | bellard | Contributed by Ralph Campbell and OSF
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30 | 6643d27e | bellard | Commented and modified by Ian Lance Taylor, Cygnus Support
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31 | 6643d27e | bellard | |
32 | 6643d27e | bellard | This file is part of GDB, GAS, and the GNU binutils.
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33 | 6643d27e | bellard | |
34 | 6643d27e | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
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35 | 6643d27e | bellard | them and/or modify them under the terms of the GNU General Public
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36 | 6643d27e | bellard | License as published by the Free Software Foundation; either version
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37 | 6643d27e | bellard | 1, or (at your option) any later version.
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38 | 6643d27e | bellard | |
39 | 6643d27e | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
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40 | 6643d27e | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
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41 | 6643d27e | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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42 | 6643d27e | bellard | the GNU General Public License for more details.
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43 | 6643d27e | bellard | |
44 | 6643d27e | bellard | You should have received a copy of the GNU General Public License
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45 | 6643d27e | bellard | along with this file; see the file COPYING. If not, write to the Free
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46 | fad6cb1a | aurel32 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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47 | 6643d27e | bellard | |
48 | 6643d27e | bellard | /* These are bit masks and shift counts to use to access the various
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49 | 6643d27e | bellard | fields of an instruction. To retrieve the X field of an
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50 | 6643d27e | bellard | instruction, use the expression
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51 | 6643d27e | bellard | (i >> OP_SH_X) & OP_MASK_X
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52 | 6643d27e | bellard | To set the same field (to j), use
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53 | 6643d27e | bellard | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
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54 | 6643d27e | bellard | |
55 | 6643d27e | bellard | Make sure you use fields that are appropriate for the instruction,
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56 | 6643d27e | bellard | of course.
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57 | 6643d27e | bellard | |
58 | 6643d27e | bellard | The 'i' format uses OP, RS, RT and IMMEDIATE.
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59 | 6643d27e | bellard | |
60 | 6643d27e | bellard | The 'j' format uses OP and TARGET.
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61 | 6643d27e | bellard | |
62 | 6643d27e | bellard | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
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63 | 6643d27e | bellard | |
64 | 6643d27e | bellard | The 'b' format uses OP, RS, RT and DELTA.
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65 | 6643d27e | bellard | |
66 | 6643d27e | bellard | The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
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67 | 6643d27e | bellard | |
68 | 6643d27e | bellard | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
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69 | 6643d27e | bellard | |
70 | 6643d27e | bellard | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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71 | 6643d27e | bellard | breakpoint instruction are not defined; Kane says the breakpoint
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72 | 6643d27e | bellard | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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73 | 6643d27e | bellard | only use ten bits). An optional two-operand form of break/sdbbp
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74 | 6643d27e | bellard | allows the lower ten bits to be set too, and MIPS32 and later
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75 | 6643d27e | bellard | architectures allow 20 bits to be set with a signal operand
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76 | 6643d27e | bellard | (using CODE20).
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77 | 6643d27e | bellard | |
78 | 6643d27e | bellard | The syscall instruction uses CODE20.
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79 | 6643d27e | bellard | |
80 | 6643d27e | bellard | The general coprocessor instructions use COPZ. */
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81 | 6643d27e | bellard | |
82 | 6643d27e | bellard | #define OP_MASK_OP 0x3f |
83 | 6643d27e | bellard | #define OP_SH_OP 26 |
84 | 6643d27e | bellard | #define OP_MASK_RS 0x1f |
85 | 6643d27e | bellard | #define OP_SH_RS 21 |
86 | 6643d27e | bellard | #define OP_MASK_FR 0x1f |
87 | 6643d27e | bellard | #define OP_SH_FR 21 |
88 | 6643d27e | bellard | #define OP_MASK_FMT 0x1f |
89 | 6643d27e | bellard | #define OP_SH_FMT 21 |
90 | 6643d27e | bellard | #define OP_MASK_BCC 0x7 |
91 | 6643d27e | bellard | #define OP_SH_BCC 18 |
92 | 6643d27e | bellard | #define OP_MASK_CODE 0x3ff |
93 | 6643d27e | bellard | #define OP_SH_CODE 16 |
94 | 6643d27e | bellard | #define OP_MASK_CODE2 0x3ff |
95 | 6643d27e | bellard | #define OP_SH_CODE2 6 |
96 | 6643d27e | bellard | #define OP_MASK_RT 0x1f |
97 | 6643d27e | bellard | #define OP_SH_RT 16 |
98 | 6643d27e | bellard | #define OP_MASK_FT 0x1f |
99 | 6643d27e | bellard | #define OP_SH_FT 16 |
100 | 6643d27e | bellard | #define OP_MASK_CACHE 0x1f |
101 | 6643d27e | bellard | #define OP_SH_CACHE 16 |
102 | 6643d27e | bellard | #define OP_MASK_RD 0x1f |
103 | 6643d27e | bellard | #define OP_SH_RD 11 |
104 | 6643d27e | bellard | #define OP_MASK_FS 0x1f |
105 | 6643d27e | bellard | #define OP_SH_FS 11 |
106 | 6643d27e | bellard | #define OP_MASK_PREFX 0x1f |
107 | 6643d27e | bellard | #define OP_SH_PREFX 11 |
108 | 6643d27e | bellard | #define OP_MASK_CCC 0x7 |
109 | 6643d27e | bellard | #define OP_SH_CCC 8 |
110 | 6643d27e | bellard | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
111 | 6643d27e | bellard | #define OP_SH_CODE20 6 |
112 | 6643d27e | bellard | #define OP_MASK_SHAMT 0x1f |
113 | 6643d27e | bellard | #define OP_SH_SHAMT 6 |
114 | 6643d27e | bellard | #define OP_MASK_FD 0x1f |
115 | 6643d27e | bellard | #define OP_SH_FD 6 |
116 | 6643d27e | bellard | #define OP_MASK_TARGET 0x3ffffff |
117 | 6643d27e | bellard | #define OP_SH_TARGET 0 |
118 | 6643d27e | bellard | #define OP_MASK_COPZ 0x1ffffff |
119 | 6643d27e | bellard | #define OP_SH_COPZ 0 |
120 | 6643d27e | bellard | #define OP_MASK_IMMEDIATE 0xffff |
121 | 6643d27e | bellard | #define OP_SH_IMMEDIATE 0 |
122 | 6643d27e | bellard | #define OP_MASK_DELTA 0xffff |
123 | 6643d27e | bellard | #define OP_SH_DELTA 0 |
124 | 6643d27e | bellard | #define OP_MASK_FUNCT 0x3f |
125 | 6643d27e | bellard | #define OP_SH_FUNCT 0 |
126 | 6643d27e | bellard | #define OP_MASK_SPEC 0x3f |
127 | 6643d27e | bellard | #define OP_SH_SPEC 0 |
128 | 6643d27e | bellard | #define OP_SH_LOCC 8 /* FP condition code. */ |
129 | 6643d27e | bellard | #define OP_SH_HICC 18 /* FP condition code. */ |
130 | 6643d27e | bellard | #define OP_MASK_CC 0x7 |
131 | 6643d27e | bellard | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
132 | 6643d27e | bellard | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ |
133 | 6643d27e | bellard | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
134 | 6643d27e | bellard | #define OP_MASK_COP1SPEC 0xf |
135 | 6643d27e | bellard | #define OP_MASK_COP1SCLR 0x4 |
136 | 6643d27e | bellard | #define OP_MASK_COP1CMP 0x3 |
137 | 6643d27e | bellard | #define OP_SH_COP1CMP 4 |
138 | 6643d27e | bellard | #define OP_SH_FORMAT 21 /* FP short format field. */ |
139 | 6643d27e | bellard | #define OP_MASK_FORMAT 0x7 |
140 | 6643d27e | bellard | #define OP_SH_TRUE 16 |
141 | 6643d27e | bellard | #define OP_MASK_TRUE 0x1 |
142 | 6643d27e | bellard | #define OP_SH_GE 17 |
143 | 6643d27e | bellard | #define OP_MASK_GE 0x01 |
144 | 6643d27e | bellard | #define OP_SH_UNSIGNED 16 |
145 | 6643d27e | bellard | #define OP_MASK_UNSIGNED 0x1 |
146 | 6643d27e | bellard | #define OP_SH_HINT 16 |
147 | 6643d27e | bellard | #define OP_MASK_HINT 0x1f |
148 | 6643d27e | bellard | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
149 | 6643d27e | bellard | #define OP_MASK_MMI 0x3f |
150 | 6643d27e | bellard | #define OP_SH_MMISUB 6 |
151 | 6643d27e | bellard | #define OP_MASK_MMISUB 0x1f |
152 | 6643d27e | bellard | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
153 | 6643d27e | bellard | #define OP_SH_PERFREG 1 |
154 | 6643d27e | bellard | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
155 | 6643d27e | bellard | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
156 | 6643d27e | bellard | #define OP_SH_CODE19 6 /* 19 bit wait code. */ |
157 | 6643d27e | bellard | #define OP_MASK_CODE19 0x7ffff |
158 | 6643d27e | bellard | #define OP_SH_ALN 21 |
159 | 6643d27e | bellard | #define OP_MASK_ALN 0x7 |
160 | 6643d27e | bellard | #define OP_SH_VSEL 21 |
161 | 6643d27e | bellard | #define OP_MASK_VSEL 0x1f |
162 | 6643d27e | bellard | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
163 | 6643d27e | bellard | but 0x8-0xf don't select bytes. */
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164 | 6643d27e | bellard | #define OP_SH_VECBYTE 22 |
165 | 6643d27e | bellard | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
166 | 6643d27e | bellard | #define OP_SH_VECALIGN 21 |
167 | 6643d27e | bellard | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
168 | 6643d27e | bellard | #define OP_SH_INSMSB 11 |
169 | 6643d27e | bellard | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
170 | 6643d27e | bellard | #define OP_SH_EXTMSBD 11 |
171 | 6643d27e | bellard | |
172 | 6643d27e | bellard | #define OP_OP_COP0 0x10 |
173 | 6643d27e | bellard | #define OP_OP_COP1 0x11 |
174 | 6643d27e | bellard | #define OP_OP_COP2 0x12 |
175 | 6643d27e | bellard | #define OP_OP_COP3 0x13 |
176 | 6643d27e | bellard | #define OP_OP_LWC1 0x31 |
177 | 6643d27e | bellard | #define OP_OP_LWC2 0x32 |
178 | 6643d27e | bellard | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
179 | 6643d27e | bellard | #define OP_OP_LDC1 0x35 |
180 | 6643d27e | bellard | #define OP_OP_LDC2 0x36 |
181 | 6643d27e | bellard | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
182 | 6643d27e | bellard | #define OP_OP_SWC1 0x39 |
183 | 6643d27e | bellard | #define OP_OP_SWC2 0x3a |
184 | 6643d27e | bellard | #define OP_OP_SWC3 0x3b |
185 | 6643d27e | bellard | #define OP_OP_SDC1 0x3d |
186 | 6643d27e | bellard | #define OP_OP_SDC2 0x3e |
187 | 6643d27e | bellard | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
188 | 6643d27e | bellard | |
189 | 29490584 | ths | /* MIPS DSP ASE */
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190 | 29490584 | ths | #define OP_SH_DSPACC 11 |
191 | 29490584 | ths | #define OP_MASK_DSPACC 0x3 |
192 | 29490584 | ths | #define OP_SH_DSPACC_S 21 |
193 | 29490584 | ths | #define OP_MASK_DSPACC_S 0x3 |
194 | 29490584 | ths | #define OP_SH_DSPSFT 20 |
195 | 29490584 | ths | #define OP_MASK_DSPSFT 0x3f |
196 | 29490584 | ths | #define OP_SH_DSPSFT_7 19 |
197 | 29490584 | ths | #define OP_MASK_DSPSFT_7 0x7f |
198 | 29490584 | ths | #define OP_SH_SA3 21 |
199 | 29490584 | ths | #define OP_MASK_SA3 0x7 |
200 | 29490584 | ths | #define OP_SH_SA4 21 |
201 | 29490584 | ths | #define OP_MASK_SA4 0xf |
202 | 29490584 | ths | #define OP_SH_IMM8 16 |
203 | 29490584 | ths | #define OP_MASK_IMM8 0xff |
204 | 29490584 | ths | #define OP_SH_IMM10 16 |
205 | 29490584 | ths | #define OP_MASK_IMM10 0x3ff |
206 | 29490584 | ths | #define OP_SH_WRDSP 11 |
207 | 29490584 | ths | #define OP_MASK_WRDSP 0x3f |
208 | 29490584 | ths | #define OP_SH_RDDSP 16 |
209 | 29490584 | ths | #define OP_MASK_RDDSP 0x3f |
210 | 29490584 | ths | #define OP_SH_BP 11 |
211 | 29490584 | ths | #define OP_MASK_BP 0x3 |
212 | 29490584 | ths | |
213 | 29490584 | ths | /* MIPS MT ASE */
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214 | 29490584 | ths | #define OP_SH_MT_U 5 |
215 | 29490584 | ths | #define OP_MASK_MT_U 0x1 |
216 | 29490584 | ths | #define OP_SH_MT_H 4 |
217 | 29490584 | ths | #define OP_MASK_MT_H 0x1 |
218 | 29490584 | ths | #define OP_SH_MTACC_T 18 |
219 | 29490584 | ths | #define OP_MASK_MTACC_T 0x3 |
220 | 29490584 | ths | #define OP_SH_MTACC_D 13 |
221 | 29490584 | ths | #define OP_MASK_MTACC_D 0x3 |
222 | 29490584 | ths | |
223 | 29490584 | ths | #define OP_OP_COP0 0x10 |
224 | 29490584 | ths | #define OP_OP_COP1 0x11 |
225 | 29490584 | ths | #define OP_OP_COP2 0x12 |
226 | 29490584 | ths | #define OP_OP_COP3 0x13 |
227 | 29490584 | ths | #define OP_OP_LWC1 0x31 |
228 | 29490584 | ths | #define OP_OP_LWC2 0x32 |
229 | 29490584 | ths | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
230 | 29490584 | ths | #define OP_OP_LDC1 0x35 |
231 | 29490584 | ths | #define OP_OP_LDC2 0x36 |
232 | 29490584 | ths | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
233 | 29490584 | ths | #define OP_OP_SWC1 0x39 |
234 | 29490584 | ths | #define OP_OP_SWC2 0x3a |
235 | 29490584 | ths | #define OP_OP_SWC3 0x3b |
236 | 29490584 | ths | #define OP_OP_SDC1 0x3d |
237 | 29490584 | ths | #define OP_OP_SDC2 0x3e |
238 | 29490584 | ths | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
239 | 29490584 | ths | |
240 | 6643d27e | bellard | /* Values in the 'VSEL' field. */
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241 | 6643d27e | bellard | #define MDMX_FMTSEL_IMM_QH 0x1d |
242 | 6643d27e | bellard | #define MDMX_FMTSEL_IMM_OB 0x1e |
243 | 6643d27e | bellard | #define MDMX_FMTSEL_VEC_QH 0x15 |
244 | 6643d27e | bellard | #define MDMX_FMTSEL_VEC_OB 0x16 |
245 | 6643d27e | bellard | |
246 | 29490584 | ths | /* UDI */
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247 | 29490584 | ths | #define OP_SH_UDI1 6 |
248 | 29490584 | ths | #define OP_MASK_UDI1 0x1f |
249 | 29490584 | ths | #define OP_SH_UDI2 6 |
250 | 29490584 | ths | #define OP_MASK_UDI2 0x3ff |
251 | 29490584 | ths | #define OP_SH_UDI3 6 |
252 | 29490584 | ths | #define OP_MASK_UDI3 0x7fff |
253 | 29490584 | ths | #define OP_SH_UDI4 6 |
254 | 29490584 | ths | #define OP_MASK_UDI4 0xfffff |
255 | 6643d27e | bellard | /* This structure holds information for a particular instruction. */
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256 | 6643d27e | bellard | |
257 | 6643d27e | bellard | struct mips_opcode
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258 | 6643d27e | bellard | { |
259 | 6643d27e | bellard | /* The name of the instruction. */
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260 | 6643d27e | bellard | const char *name; |
261 | 6643d27e | bellard | /* A string describing the arguments for this instruction. */
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262 | 6643d27e | bellard | const char *args; |
263 | 6643d27e | bellard | /* The basic opcode for the instruction. When assembling, this
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264 | 6643d27e | bellard | opcode is modified by the arguments to produce the actual opcode
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265 | 6643d27e | bellard | that is used. If pinfo is INSN_MACRO, then this is 0. */
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266 | 6643d27e | bellard | unsigned long match; |
267 | 6643d27e | bellard | /* If pinfo is not INSN_MACRO, then this is a bit mask for the
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268 | 6643d27e | bellard | relevant portions of the opcode when disassembling. If the
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269 | 6643d27e | bellard | actual opcode anded with the match field equals the opcode field,
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270 | 6643d27e | bellard | then we have found the correct instruction. If pinfo is
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271 | 6643d27e | bellard | INSN_MACRO, then this field is the macro identifier. */
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272 | 6643d27e | bellard | unsigned long mask; |
273 | 6643d27e | bellard | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
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274 | 6643d27e | bellard | of bits describing the instruction, notably any relevant hazard
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275 | 6643d27e | bellard | information. */
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276 | 6643d27e | bellard | unsigned long pinfo; |
277 | 29490584 | ths | /* A collection of additional bits describing the instruction. */
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278 | 29490584 | ths | unsigned long pinfo2; |
279 | 6643d27e | bellard | /* A collection of bits describing the instruction sets of which this
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280 | 6643d27e | bellard | instruction or macro is a member. */
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281 | 6643d27e | bellard | unsigned long membership; |
282 | 6643d27e | bellard | }; |
283 | 6643d27e | bellard | |
284 | 6643d27e | bellard | /* These are the characters which may appear in the args field of an
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285 | 6643d27e | bellard | instruction. They appear in the order in which the fields appear
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286 | 6643d27e | bellard | when the instruction is used. Commas and parentheses in the args
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287 | 6643d27e | bellard | string are ignored when assembling, and written into the output
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288 | 6643d27e | bellard | when disassembling.
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289 | 6643d27e | bellard | |
290 | 6643d27e | bellard | Each of these characters corresponds to a mask field defined above.
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291 | 6643d27e | bellard | |
292 | 6643d27e | bellard | "<" 5 bit shift amount (OP_*_SHAMT)
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293 | 6643d27e | bellard | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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294 | 6643d27e | bellard | "a" 26 bit target address (OP_*_TARGET)
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295 | 6643d27e | bellard | "b" 5 bit base register (OP_*_RS)
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296 | 6643d27e | bellard | "c" 10 bit breakpoint code (OP_*_CODE)
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297 | 6643d27e | bellard | "d" 5 bit destination register specifier (OP_*_RD)
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298 | 6643d27e | bellard | "h" 5 bit prefx hint (OP_*_PREFX)
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299 | 6643d27e | bellard | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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300 | 6643d27e | bellard | "j" 16 bit signed immediate (OP_*_DELTA)
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301 | 6643d27e | bellard | "k" 5 bit cache opcode in target register position (OP_*_CACHE)
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302 | 6643d27e | bellard | Also used for immediate operands in vr5400 vector insns.
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303 | 6643d27e | bellard | "o" 16 bit signed offset (OP_*_DELTA)
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304 | 6643d27e | bellard | "p" 16 bit PC relative branch target address (OP_*_DELTA)
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305 | 6643d27e | bellard | "q" 10 bit extra breakpoint code (OP_*_CODE2)
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306 | 6643d27e | bellard | "r" 5 bit same register used as both source and target (OP_*_RS)
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307 | 6643d27e | bellard | "s" 5 bit source register specifier (OP_*_RS)
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308 | 6643d27e | bellard | "t" 5 bit target register (OP_*_RT)
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309 | 6643d27e | bellard | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
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310 | 6643d27e | bellard | "v" 5 bit same register used as both source and destination (OP_*_RS)
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311 | 6643d27e | bellard | "w" 5 bit same register used as both target and destination (OP_*_RT)
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312 | 6643d27e | bellard | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
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313 | 6643d27e | bellard | (used by clo and clz)
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314 | 6643d27e | bellard | "C" 25 bit coprocessor function code (OP_*_COPZ)
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315 | 6643d27e | bellard | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
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316 | 6643d27e | bellard | "J" 19 bit wait function code (OP_*_CODE19)
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317 | 6643d27e | bellard | "x" accept and ignore register name
|
318 | 6643d27e | bellard | "z" must be zero register
|
319 | 6643d27e | bellard | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
|
320 | 29490584 | ths | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
|
321 | 29490584 | ths | LSB (OP_*_SHAMT).
|
322 | 6643d27e | bellard | Enforces: 0 <= pos < 32.
|
323 | 29490584 | ths | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
|
324 | 6643d27e | bellard | Requires that "+A" or "+E" occur first to set position.
|
325 | 6643d27e | bellard | Enforces: 0 < (pos+size) <= 32.
|
326 | 29490584 | ths | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
|
327 | 6643d27e | bellard | Requires that "+A" or "+E" occur first to set position.
|
328 | 6643d27e | bellard | Enforces: 0 < (pos+size) <= 32.
|
329 | 6643d27e | bellard | (Also used by "dext" w/ different limits, but limits for
|
330 | 6643d27e | bellard | that are checked by the M_DEXT macro.)
|
331 | 29490584 | ths | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
|
332 | 6643d27e | bellard | Enforces: 32 <= pos < 64.
|
333 | 29490584 | ths | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
|
334 | 6643d27e | bellard | Requires that "+A" or "+E" occur first to set position.
|
335 | 6643d27e | bellard | Enforces: 32 < (pos+size) <= 64.
|
336 | 6643d27e | bellard | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
|
337 | 6643d27e | bellard | Requires that "+A" or "+E" occur first to set position.
|
338 | 6643d27e | bellard | Enforces: 32 < (pos+size) <= 64.
|
339 | 6643d27e | bellard | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
|
340 | 6643d27e | bellard | Requires that "+A" or "+E" occur first to set position.
|
341 | 6643d27e | bellard | Enforces: 32 < (pos+size) <= 64.
|
342 | 6643d27e | bellard | |
343 | 6643d27e | bellard | Floating point instructions:
|
344 | 6643d27e | bellard | "D" 5 bit destination register (OP_*_FD)
|
345 | 6643d27e | bellard | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
|
346 | 6643d27e | bellard | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
|
347 | 6643d27e | bellard | "S" 5 bit fs source 1 register (OP_*_FS)
|
348 | 6643d27e | bellard | "T" 5 bit ft source 2 register (OP_*_FT)
|
349 | 6643d27e | bellard | "R" 5 bit fr source 3 register (OP_*_FR)
|
350 | 6643d27e | bellard | "V" 5 bit same register used as floating source and destination (OP_*_FS)
|
351 | 6643d27e | bellard | "W" 5 bit same register used as floating target and destination (OP_*_FT)
|
352 | 6643d27e | bellard | |
353 | 6643d27e | bellard | Coprocessor instructions:
|
354 | 6643d27e | bellard | "E" 5 bit target register (OP_*_RT)
|
355 | 6643d27e | bellard | "G" 5 bit destination register (OP_*_RD)
|
356 | 6643d27e | bellard | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
|
357 | 6643d27e | bellard | "P" 5 bit performance-monitor register (OP_*_PERFREG)
|
358 | 6643d27e | bellard | "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
|
359 | 6643d27e | bellard | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
|
360 | 6643d27e | bellard | see also "k" above
|
361 | 6643d27e | bellard | "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
|
362 | 6643d27e | bellard | for pretty-printing in disassembly only.
|
363 | 6643d27e | bellard | |
364 | 6643d27e | bellard | Macro instructions:
|
365 | 6643d27e | bellard | "A" General 32 bit expression
|
366 | 6643d27e | bellard | "I" 32 bit immediate (value placed in imm_expr).
|
367 | 6643d27e | bellard | "+I" 32 bit immediate (value placed in imm2_expr).
|
368 | 6643d27e | bellard | "F" 64 bit floating point constant in .rdata
|
369 | 6643d27e | bellard | "L" 64 bit floating point constant in .lit8
|
370 | 6643d27e | bellard | "f" 32 bit floating point constant
|
371 | 6643d27e | bellard | "l" 32 bit floating point constant in .lit4
|
372 | 6643d27e | bellard | |
373 | 6643d27e | bellard | MDMX instruction operands (note that while these use the FP register
|
374 | 3b46e624 | ths | fields, they accept both $fN and $vN names for the registers):
|
375 | 6643d27e | bellard | "O" MDMX alignment offset (OP_*_ALN)
|
376 | 6643d27e | bellard | "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
|
377 | 5fafdf24 | ths | "X" MDMX destination register (OP_*_FD)
|
378 | 6643d27e | bellard | "Y" MDMX source register (OP_*_FS)
|
379 | 6643d27e | bellard | "Z" MDMX source register (OP_*_FT)
|
380 | 6643d27e | bellard | |
381 | 29490584 | ths | DSP ASE usage:
|
382 | 29490584 | ths | "2" 2 bit unsigned immediate for byte align (OP_*_BP)
|
383 | 29490584 | ths | "3" 3 bit unsigned immediate (OP_*_SA3)
|
384 | 29490584 | ths | "4" 4 bit unsigned immediate (OP_*_SA4)
|
385 | 29490584 | ths | "5" 8 bit unsigned immediate (OP_*_IMM8)
|
386 | 29490584 | ths | "6" 5 bit unsigned immediate (OP_*_RS)
|
387 | 29490584 | ths | "7" 2 bit dsp accumulator register (OP_*_DSPACC)
|
388 | 29490584 | ths | "8" 6 bit unsigned immediate (OP_*_WRDSP)
|
389 | 29490584 | ths | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
|
390 | 29490584 | ths | "0" 6 bit signed immediate (OP_*_DSPSFT)
|
391 | 29490584 | ths | ":" 7 bit signed immediate (OP_*_DSPSFT_7)
|
392 | 29490584 | ths | "'" 6 bit unsigned immediate (OP_*_RDDSP)
|
393 | 29490584 | ths | "@" 10 bit signed immediate (OP_*_IMM10)
|
394 | 29490584 | ths | |
395 | 29490584 | ths | MT ASE usage:
|
396 | 29490584 | ths | "!" 1 bit usermode flag (OP_*_MT_U)
|
397 | 29490584 | ths | "$" 1 bit load high flag (OP_*_MT_H)
|
398 | 29490584 | ths | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
|
399 | 29490584 | ths | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
|
400 | 29490584 | ths | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
|
401 | 29490584 | ths | "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
|
402 | 29490584 | ths | "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
|
403 | 29490584 | ths | |
404 | 29490584 | ths | UDI immediates:
|
405 | 29490584 | ths | "+1" UDI immediate bits 6-10
|
406 | 29490584 | ths | "+2" UDI immediate bits 6-15
|
407 | 29490584 | ths | "+3" UDI immediate bits 6-20
|
408 | 29490584 | ths | "+4" UDI immediate bits 6-25
|
409 | 29490584 | ths | |
410 | 6643d27e | bellard | Other:
|
411 | 6643d27e | bellard | "()" parens surrounding optional value
|
412 | 6643d27e | bellard | "," separates operands
|
413 | 6643d27e | bellard | "[]" brackets around index for vector-op scalar operand specifier (vr5400)
|
414 | 6643d27e | bellard | "+" Start of extension sequence.
|
415 | 6643d27e | bellard | |
416 | 6643d27e | bellard | Characters used so far, for quick reference when adding more:
|
417 | 29490584 | ths | "234567890"
|
418 | 29490584 | ths | "%[]<>(),+:'@!$*&"
|
419 | 6643d27e | bellard | "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
420 | 29490584 | ths | "abcdefghijklopqrstuvwxz"
|
421 | 6643d27e | bellard | |
422 | 6643d27e | bellard | Extension character sequences used so far ("+" followed by the
|
423 | 6643d27e | bellard | following), for quick reference when adding more:
|
424 | 29490584 | ths | "1234"
|
425 | 29490584 | ths | "ABCDEFGHIT"
|
426 | 29490584 | ths | "t"
|
427 | 6643d27e | bellard | */
|
428 | 6643d27e | bellard | |
429 | 6643d27e | bellard | /* These are the bits which may be set in the pinfo field of an
|
430 | 6643d27e | bellard | instructions, if it is not equal to INSN_MACRO. */
|
431 | 6643d27e | bellard | |
432 | 6643d27e | bellard | /* Modifies the general purpose register in OP_*_RD. */
|
433 | 6643d27e | bellard | #define INSN_WRITE_GPR_D 0x00000001 |
434 | 6643d27e | bellard | /* Modifies the general purpose register in OP_*_RT. */
|
435 | 6643d27e | bellard | #define INSN_WRITE_GPR_T 0x00000002 |
436 | 6643d27e | bellard | /* Modifies general purpose register 31. */
|
437 | 6643d27e | bellard | #define INSN_WRITE_GPR_31 0x00000004 |
438 | 6643d27e | bellard | /* Modifies the floating point register in OP_*_FD. */
|
439 | 6643d27e | bellard | #define INSN_WRITE_FPR_D 0x00000008 |
440 | 6643d27e | bellard | /* Modifies the floating point register in OP_*_FS. */
|
441 | 6643d27e | bellard | #define INSN_WRITE_FPR_S 0x00000010 |
442 | 6643d27e | bellard | /* Modifies the floating point register in OP_*_FT. */
|
443 | 6643d27e | bellard | #define INSN_WRITE_FPR_T 0x00000020 |
444 | 6643d27e | bellard | /* Reads the general purpose register in OP_*_RS. */
|
445 | 6643d27e | bellard | #define INSN_READ_GPR_S 0x00000040 |
446 | 6643d27e | bellard | /* Reads the general purpose register in OP_*_RT. */
|
447 | 6643d27e | bellard | #define INSN_READ_GPR_T 0x00000080 |
448 | 6643d27e | bellard | /* Reads the floating point register in OP_*_FS. */
|
449 | 6643d27e | bellard | #define INSN_READ_FPR_S 0x00000100 |
450 | 6643d27e | bellard | /* Reads the floating point register in OP_*_FT. */
|
451 | 6643d27e | bellard | #define INSN_READ_FPR_T 0x00000200 |
452 | 6643d27e | bellard | /* Reads the floating point register in OP_*_FR. */
|
453 | 6643d27e | bellard | #define INSN_READ_FPR_R 0x00000400 |
454 | 6643d27e | bellard | /* Modifies coprocessor condition code. */
|
455 | 6643d27e | bellard | #define INSN_WRITE_COND_CODE 0x00000800 |
456 | 6643d27e | bellard | /* Reads coprocessor condition code. */
|
457 | 6643d27e | bellard | #define INSN_READ_COND_CODE 0x00001000 |
458 | 6643d27e | bellard | /* TLB operation. */
|
459 | 6643d27e | bellard | #define INSN_TLB 0x00002000 |
460 | 6643d27e | bellard | /* Reads coprocessor register other than floating point register. */
|
461 | 6643d27e | bellard | #define INSN_COP 0x00004000 |
462 | 6643d27e | bellard | /* Instruction loads value from memory, requiring delay. */
|
463 | 6643d27e | bellard | #define INSN_LOAD_MEMORY_DELAY 0x00008000 |
464 | 6643d27e | bellard | /* Instruction loads value from coprocessor, requiring delay. */
|
465 | 6643d27e | bellard | #define INSN_LOAD_COPROC_DELAY 0x00010000 |
466 | 6643d27e | bellard | /* Instruction has unconditional branch delay slot. */
|
467 | 6643d27e | bellard | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 |
468 | 6643d27e | bellard | /* Instruction has conditional branch delay slot. */
|
469 | 6643d27e | bellard | #define INSN_COND_BRANCH_DELAY 0x00040000 |
470 | 6643d27e | bellard | /* Conditional branch likely: if branch not taken, insn nullified. */
|
471 | 6643d27e | bellard | #define INSN_COND_BRANCH_LIKELY 0x00080000 |
472 | 6643d27e | bellard | /* Moves to coprocessor register, requiring delay. */
|
473 | 6643d27e | bellard | #define INSN_COPROC_MOVE_DELAY 0x00100000 |
474 | 6643d27e | bellard | /* Loads coprocessor register from memory, requiring delay. */
|
475 | 6643d27e | bellard | #define INSN_COPROC_MEMORY_DELAY 0x00200000 |
476 | 6643d27e | bellard | /* Reads the HI register. */
|
477 | 6643d27e | bellard | #define INSN_READ_HI 0x00400000 |
478 | 6643d27e | bellard | /* Reads the LO register. */
|
479 | 6643d27e | bellard | #define INSN_READ_LO 0x00800000 |
480 | 6643d27e | bellard | /* Modifies the HI register. */
|
481 | 6643d27e | bellard | #define INSN_WRITE_HI 0x01000000 |
482 | 6643d27e | bellard | /* Modifies the LO register. */
|
483 | 6643d27e | bellard | #define INSN_WRITE_LO 0x02000000 |
484 | 6643d27e | bellard | /* Takes a trap (easier to keep out of delay slot). */
|
485 | 6643d27e | bellard | #define INSN_TRAP 0x04000000 |
486 | 6643d27e | bellard | /* Instruction stores value into memory. */
|
487 | 6643d27e | bellard | #define INSN_STORE_MEMORY 0x08000000 |
488 | 6643d27e | bellard | /* Instruction uses single precision floating point. */
|
489 | 6643d27e | bellard | #define FP_S 0x10000000 |
490 | 6643d27e | bellard | /* Instruction uses double precision floating point. */
|
491 | 6643d27e | bellard | #define FP_D 0x20000000 |
492 | 6643d27e | bellard | /* Instruction is part of the tx39's integer multiply family. */
|
493 | 6643d27e | bellard | #define INSN_MULT 0x40000000 |
494 | 6643d27e | bellard | /* Instruction synchronize shared memory. */
|
495 | 6643d27e | bellard | #define INSN_SYNC 0x80000000 |
496 | 29490584 | ths | |
497 | 29490584 | ths | /* These are the bits which may be set in the pinfo2 field of an
|
498 | 29490584 | ths | instruction. */
|
499 | 29490584 | ths | |
500 | 29490584 | ths | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
|
501 | 29490584 | ths | #define INSN2_ALIAS 0x00000001 |
502 | 29490584 | ths | /* Instruction reads MDMX accumulator. */
|
503 | 29490584 | ths | #define INSN2_READ_MDMX_ACC 0x00000002 |
504 | 29490584 | ths | /* Instruction writes MDMX accumulator. */
|
505 | 29490584 | ths | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
506 | 6643d27e | bellard | |
507 | 6643d27e | bellard | /* Instruction is actually a macro. It should be ignored by the
|
508 | 6643d27e | bellard | disassembler, and requires special treatment by the assembler. */
|
509 | 6643d27e | bellard | #define INSN_MACRO 0xffffffff |
510 | 6643d27e | bellard | |
511 | 6643d27e | bellard | /* Masks used to mark instructions to indicate which MIPS ISA level
|
512 | 6643d27e | bellard | they were introduced in. ISAs, as defined below, are logical
|
513 | 6643d27e | bellard | ORs of these bits, indicating that they support the instructions
|
514 | 6643d27e | bellard | defined at the given level. */
|
515 | 6643d27e | bellard | |
516 | 6643d27e | bellard | #define INSN_ISA_MASK 0x00000fff |
517 | 6643d27e | bellard | #define INSN_ISA1 0x00000001 |
518 | 6643d27e | bellard | #define INSN_ISA2 0x00000002 |
519 | 6643d27e | bellard | #define INSN_ISA3 0x00000004 |
520 | 6643d27e | bellard | #define INSN_ISA4 0x00000008 |
521 | 6643d27e | bellard | #define INSN_ISA5 0x00000010 |
522 | 6643d27e | bellard | #define INSN_ISA32 0x00000020 |
523 | 6643d27e | bellard | #define INSN_ISA64 0x00000040 |
524 | 6643d27e | bellard | #define INSN_ISA32R2 0x00000080 |
525 | 6643d27e | bellard | #define INSN_ISA64R2 0x00000100 |
526 | 6643d27e | bellard | |
527 | 6643d27e | bellard | /* Masks used for MIPS-defined ASEs. */
|
528 | 6643d27e | bellard | #define INSN_ASE_MASK 0x0000f000 |
529 | 6643d27e | bellard | |
530 | 29490584 | ths | /* DSP ASE */
|
531 | 29490584 | ths | #define INSN_DSP 0x00001000 |
532 | 29490584 | ths | #define INSN_DSP64 0x00002000 |
533 | 6643d27e | bellard | /* MIPS 16 ASE */
|
534 | 29490584 | ths | #define INSN_MIPS16 0x00004000 |
535 | 6643d27e | bellard | /* MIPS-3D ASE */
|
536 | 29490584 | ths | #define INSN_MIPS3D 0x00008000 |
537 | 6643d27e | bellard | |
538 | 6643d27e | bellard | /* Chip specific instructions. These are bitmasks. */
|
539 | 6643d27e | bellard | |
540 | 6643d27e | bellard | /* MIPS R4650 instruction. */
|
541 | 6643d27e | bellard | #define INSN_4650 0x00010000 |
542 | 6643d27e | bellard | /* LSI R4010 instruction. */
|
543 | 6643d27e | bellard | #define INSN_4010 0x00020000 |
544 | 6643d27e | bellard | /* NEC VR4100 instruction. */
|
545 | 6643d27e | bellard | #define INSN_4100 0x00040000 |
546 | 6643d27e | bellard | /* Toshiba R3900 instruction. */
|
547 | 6643d27e | bellard | #define INSN_3900 0x00080000 |
548 | 6643d27e | bellard | /* MIPS R10000 instruction. */
|
549 | 6643d27e | bellard | #define INSN_10000 0x00100000 |
550 | 6643d27e | bellard | /* Broadcom SB-1 instruction. */
|
551 | 6643d27e | bellard | #define INSN_SB1 0x00200000 |
552 | 6643d27e | bellard | /* NEC VR4111/VR4181 instruction. */
|
553 | 6643d27e | bellard | #define INSN_4111 0x00400000 |
554 | 6643d27e | bellard | /* NEC VR4120 instruction. */
|
555 | 6643d27e | bellard | #define INSN_4120 0x00800000 |
556 | 6643d27e | bellard | /* NEC VR5400 instruction. */
|
557 | 6643d27e | bellard | #define INSN_5400 0x01000000 |
558 | 6643d27e | bellard | /* NEC VR5500 instruction. */
|
559 | 6643d27e | bellard | #define INSN_5500 0x02000000 |
560 | 6643d27e | bellard | |
561 | 29490584 | ths | /* MDMX ASE */
|
562 | 29490584 | ths | #define INSN_MDMX 0x04000000 |
563 | 29490584 | ths | /* MT ASE */
|
564 | 29490584 | ths | #define INSN_MT 0x08000000 |
565 | 29490584 | ths | /* SmartMIPS ASE */
|
566 | 29490584 | ths | #define INSN_SMARTMIPS 0x10000000 |
567 | 29490584 | ths | /* DSP R2 ASE */
|
568 | 29490584 | ths | #define INSN_DSPR2 0x20000000 |
569 | 29490584 | ths | |
570 | 6643d27e | bellard | /* MIPS ISA defines, use instead of hardcoding ISA level. */
|
571 | 6643d27e | bellard | |
572 | 6643d27e | bellard | #define ISA_UNKNOWN 0 /* Gas internal use. */ |
573 | 6643d27e | bellard | #define ISA_MIPS1 (INSN_ISA1)
|
574 | 6643d27e | bellard | #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
|
575 | 6643d27e | bellard | #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
|
576 | 6643d27e | bellard | #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
|
577 | 6643d27e | bellard | #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
|
578 | 6643d27e | bellard | |
579 | 6643d27e | bellard | #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
|
580 | 6643d27e | bellard | #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
|
581 | 6643d27e | bellard | |
582 | 6643d27e | bellard | #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
|
583 | 6643d27e | bellard | #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
|
584 | 6643d27e | bellard | |
585 | 6643d27e | bellard | |
586 | 6643d27e | bellard | /* CPU defines, use instead of hardcoding processor number. Keep this
|
587 | 6643d27e | bellard | in sync with bfd/archures.c in order for machine selection to work. */
|
588 | 6643d27e | bellard | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
589 | 6643d27e | bellard | #define CPU_R3000 3000 |
590 | 6643d27e | bellard | #define CPU_R3900 3900 |
591 | 6643d27e | bellard | #define CPU_R4000 4000 |
592 | 6643d27e | bellard | #define CPU_R4010 4010 |
593 | 6643d27e | bellard | #define CPU_VR4100 4100 |
594 | 6643d27e | bellard | #define CPU_R4111 4111 |
595 | 6643d27e | bellard | #define CPU_VR4120 4120 |
596 | 6643d27e | bellard | #define CPU_R4300 4300 |
597 | 6643d27e | bellard | #define CPU_R4400 4400 |
598 | 6643d27e | bellard | #define CPU_R4600 4600 |
599 | 6643d27e | bellard | #define CPU_R4650 4650 |
600 | 6643d27e | bellard | #define CPU_R5000 5000 |
601 | 6643d27e | bellard | #define CPU_VR5400 5400 |
602 | 6643d27e | bellard | #define CPU_VR5500 5500 |
603 | 6643d27e | bellard | #define CPU_R6000 6000 |
604 | 6643d27e | bellard | #define CPU_RM7000 7000 |
605 | 6643d27e | bellard | #define CPU_R8000 8000 |
606 | 6643d27e | bellard | #define CPU_R10000 10000 |
607 | 6643d27e | bellard | #define CPU_R12000 12000 |
608 | 6643d27e | bellard | #define CPU_MIPS16 16 |
609 | 6643d27e | bellard | #define CPU_MIPS32 32 |
610 | 6643d27e | bellard | #define CPU_MIPS32R2 33 |
611 | 6643d27e | bellard | #define CPU_MIPS5 5 |
612 | 6643d27e | bellard | #define CPU_MIPS64 64 |
613 | 6643d27e | bellard | #define CPU_MIPS64R2 65 |
614 | 6643d27e | bellard | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
615 | 6643d27e | bellard | |
616 | 6643d27e | bellard | /* Test for membership in an ISA including chip specific ISAs. INSN
|
617 | 6643d27e | bellard | is pointer to an element of the opcode table; ISA is the specified
|
618 | 6643d27e | bellard | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
619 | 6643d27e | bellard | test, or zero if no CPU specific ISA test is desired. */
|
620 | 6643d27e | bellard | |
621 | 42fe4044 | bellard | #if 0
|
622 | 6643d27e | bellard | #define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
623 | 6643d27e | bellard | (((insn)->membership & isa) != 0 \
|
624 | 6643d27e | bellard | || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
625 | 6643d27e | bellard | || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
|
626 | 29490584 | ths | || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|
627 | 6643d27e | bellard | || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
628 | 6643d27e | bellard | || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|
629 | 6643d27e | bellard | || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|
630 | 6643d27e | bellard | || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
|
631 | 6643d27e | bellard | && ((insn)->membership & INSN_10000) != 0) \
|
632 | 6643d27e | bellard | || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|
633 | 6643d27e | bellard | || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|
634 | 6643d27e | bellard | || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|
635 | 6643d27e | bellard | || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|
636 | 6643d27e | bellard | || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|
637 | 6643d27e | bellard | || 0) /* Please keep this term for easier source merging. */
|
638 | 42fe4044 | bellard | #else
|
639 | 42fe4044 | bellard | #define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
640 | 42fe4044 | bellard | (1 != 0) |
641 | 42fe4044 | bellard | #endif
|
642 | 6643d27e | bellard | |
643 | 6643d27e | bellard | /* This is a list of macro expanded instructions.
|
644 | 6643d27e | bellard | |
645 | 6643d27e | bellard | _I appended means immediate
|
646 | 6643d27e | bellard | _A appended means address
|
647 | 6643d27e | bellard | _AB appended means address with base register
|
648 | 6643d27e | bellard | _D appended means 64 bit floating point constant
|
649 | 6643d27e | bellard | _S appended means 32 bit floating point constant. */
|
650 | 6643d27e | bellard | |
651 | 6643d27e | bellard | enum
|
652 | 6643d27e | bellard | { |
653 | 6643d27e | bellard | M_ABS, |
654 | 6643d27e | bellard | M_ADD_I, |
655 | 6643d27e | bellard | M_ADDU_I, |
656 | 6643d27e | bellard | M_AND_I, |
657 | 29490584 | ths | M_BALIGN, |
658 | 6643d27e | bellard | M_BEQ, |
659 | 6643d27e | bellard | M_BEQ_I, |
660 | 6643d27e | bellard | M_BEQL_I, |
661 | 6643d27e | bellard | M_BGE, |
662 | 6643d27e | bellard | M_BGEL, |
663 | 6643d27e | bellard | M_BGE_I, |
664 | 6643d27e | bellard | M_BGEL_I, |
665 | 6643d27e | bellard | M_BGEU, |
666 | 6643d27e | bellard | M_BGEUL, |
667 | 6643d27e | bellard | M_BGEU_I, |
668 | 6643d27e | bellard | M_BGEUL_I, |
669 | 6643d27e | bellard | M_BGT, |
670 | 6643d27e | bellard | M_BGTL, |
671 | 6643d27e | bellard | M_BGT_I, |
672 | 6643d27e | bellard | M_BGTL_I, |
673 | 6643d27e | bellard | M_BGTU, |
674 | 6643d27e | bellard | M_BGTUL, |
675 | 6643d27e | bellard | M_BGTU_I, |
676 | 6643d27e | bellard | M_BGTUL_I, |
677 | 6643d27e | bellard | M_BLE, |
678 | 6643d27e | bellard | M_BLEL, |
679 | 6643d27e | bellard | M_BLE_I, |
680 | 6643d27e | bellard | M_BLEL_I, |
681 | 6643d27e | bellard | M_BLEU, |
682 | 6643d27e | bellard | M_BLEUL, |
683 | 6643d27e | bellard | M_BLEU_I, |
684 | 6643d27e | bellard | M_BLEUL_I, |
685 | 6643d27e | bellard | M_BLT, |
686 | 6643d27e | bellard | M_BLTL, |
687 | 6643d27e | bellard | M_BLT_I, |
688 | 6643d27e | bellard | M_BLTL_I, |
689 | 6643d27e | bellard | M_BLTU, |
690 | 6643d27e | bellard | M_BLTUL, |
691 | 6643d27e | bellard | M_BLTU_I, |
692 | 6643d27e | bellard | M_BLTUL_I, |
693 | 6643d27e | bellard | M_BNE, |
694 | 6643d27e | bellard | M_BNE_I, |
695 | 6643d27e | bellard | M_BNEL_I, |
696 | 29490584 | ths | M_CACHE_AB, |
697 | 6643d27e | bellard | M_DABS, |
698 | 6643d27e | bellard | M_DADD_I, |
699 | 6643d27e | bellard | M_DADDU_I, |
700 | 6643d27e | bellard | M_DDIV_3, |
701 | 6643d27e | bellard | M_DDIV_3I, |
702 | 6643d27e | bellard | M_DDIVU_3, |
703 | 6643d27e | bellard | M_DDIVU_3I, |
704 | 6643d27e | bellard | M_DEXT, |
705 | 6643d27e | bellard | M_DINS, |
706 | 6643d27e | bellard | M_DIV_3, |
707 | 6643d27e | bellard | M_DIV_3I, |
708 | 6643d27e | bellard | M_DIVU_3, |
709 | 6643d27e | bellard | M_DIVU_3I, |
710 | 6643d27e | bellard | M_DLA_AB, |
711 | 6643d27e | bellard | M_DLCA_AB, |
712 | 6643d27e | bellard | M_DLI, |
713 | 6643d27e | bellard | M_DMUL, |
714 | 6643d27e | bellard | M_DMUL_I, |
715 | 6643d27e | bellard | M_DMULO, |
716 | 6643d27e | bellard | M_DMULO_I, |
717 | 6643d27e | bellard | M_DMULOU, |
718 | 6643d27e | bellard | M_DMULOU_I, |
719 | 6643d27e | bellard | M_DREM_3, |
720 | 6643d27e | bellard | M_DREM_3I, |
721 | 6643d27e | bellard | M_DREMU_3, |
722 | 6643d27e | bellard | M_DREMU_3I, |
723 | 6643d27e | bellard | M_DSUB_I, |
724 | 6643d27e | bellard | M_DSUBU_I, |
725 | 6643d27e | bellard | M_DSUBU_I_2, |
726 | 6643d27e | bellard | M_J_A, |
727 | 6643d27e | bellard | M_JAL_1, |
728 | 6643d27e | bellard | M_JAL_2, |
729 | 6643d27e | bellard | M_JAL_A, |
730 | 6643d27e | bellard | M_L_DOB, |
731 | 6643d27e | bellard | M_L_DAB, |
732 | 6643d27e | bellard | M_LA_AB, |
733 | 6643d27e | bellard | M_LB_A, |
734 | 6643d27e | bellard | M_LB_AB, |
735 | 6643d27e | bellard | M_LBU_A, |
736 | 6643d27e | bellard | M_LBU_AB, |
737 | 6643d27e | bellard | M_LCA_AB, |
738 | 6643d27e | bellard | M_LD_A, |
739 | 6643d27e | bellard | M_LD_OB, |
740 | 6643d27e | bellard | M_LD_AB, |
741 | 6643d27e | bellard | M_LDC1_AB, |
742 | 6643d27e | bellard | M_LDC2_AB, |
743 | 6643d27e | bellard | M_LDC3_AB, |
744 | 6643d27e | bellard | M_LDL_AB, |
745 | 6643d27e | bellard | M_LDR_AB, |
746 | 6643d27e | bellard | M_LH_A, |
747 | 6643d27e | bellard | M_LH_AB, |
748 | 6643d27e | bellard | M_LHU_A, |
749 | 6643d27e | bellard | M_LHU_AB, |
750 | 6643d27e | bellard | M_LI, |
751 | 6643d27e | bellard | M_LI_D, |
752 | 6643d27e | bellard | M_LI_DD, |
753 | 6643d27e | bellard | M_LI_S, |
754 | 6643d27e | bellard | M_LI_SS, |
755 | 6643d27e | bellard | M_LL_AB, |
756 | 6643d27e | bellard | M_LLD_AB, |
757 | 6643d27e | bellard | M_LS_A, |
758 | 6643d27e | bellard | M_LW_A, |
759 | 6643d27e | bellard | M_LW_AB, |
760 | 6643d27e | bellard | M_LWC0_A, |
761 | 6643d27e | bellard | M_LWC0_AB, |
762 | 6643d27e | bellard | M_LWC1_A, |
763 | 6643d27e | bellard | M_LWC1_AB, |
764 | 6643d27e | bellard | M_LWC2_A, |
765 | 6643d27e | bellard | M_LWC2_AB, |
766 | 6643d27e | bellard | M_LWC3_A, |
767 | 6643d27e | bellard | M_LWC3_AB, |
768 | 6643d27e | bellard | M_LWL_A, |
769 | 6643d27e | bellard | M_LWL_AB, |
770 | 6643d27e | bellard | M_LWR_A, |
771 | 6643d27e | bellard | M_LWR_AB, |
772 | 6643d27e | bellard | M_LWU_AB, |
773 | 6643d27e | bellard | M_MOVE, |
774 | 6643d27e | bellard | M_MUL, |
775 | 6643d27e | bellard | M_MUL_I, |
776 | 6643d27e | bellard | M_MULO, |
777 | 6643d27e | bellard | M_MULO_I, |
778 | 6643d27e | bellard | M_MULOU, |
779 | 6643d27e | bellard | M_MULOU_I, |
780 | 6643d27e | bellard | M_NOR_I, |
781 | 6643d27e | bellard | M_OR_I, |
782 | 6643d27e | bellard | M_REM_3, |
783 | 6643d27e | bellard | M_REM_3I, |
784 | 6643d27e | bellard | M_REMU_3, |
785 | 6643d27e | bellard | M_REMU_3I, |
786 | 6643d27e | bellard | M_DROL, |
787 | 6643d27e | bellard | M_ROL, |
788 | 6643d27e | bellard | M_DROL_I, |
789 | 6643d27e | bellard | M_ROL_I, |
790 | 6643d27e | bellard | M_DROR, |
791 | 6643d27e | bellard | M_ROR, |
792 | 6643d27e | bellard | M_DROR_I, |
793 | 6643d27e | bellard | M_ROR_I, |
794 | 6643d27e | bellard | M_S_DA, |
795 | 6643d27e | bellard | M_S_DOB, |
796 | 6643d27e | bellard | M_S_DAB, |
797 | 6643d27e | bellard | M_S_S, |
798 | 6643d27e | bellard | M_SC_AB, |
799 | 6643d27e | bellard | M_SCD_AB, |
800 | 6643d27e | bellard | M_SD_A, |
801 | 6643d27e | bellard | M_SD_OB, |
802 | 6643d27e | bellard | M_SD_AB, |
803 | 6643d27e | bellard | M_SDC1_AB, |
804 | 6643d27e | bellard | M_SDC2_AB, |
805 | 6643d27e | bellard | M_SDC3_AB, |
806 | 6643d27e | bellard | M_SDL_AB, |
807 | 6643d27e | bellard | M_SDR_AB, |
808 | 6643d27e | bellard | M_SEQ, |
809 | 6643d27e | bellard | M_SEQ_I, |
810 | 6643d27e | bellard | M_SGE, |
811 | 6643d27e | bellard | M_SGE_I, |
812 | 6643d27e | bellard | M_SGEU, |
813 | 6643d27e | bellard | M_SGEU_I, |
814 | 6643d27e | bellard | M_SGT, |
815 | 6643d27e | bellard | M_SGT_I, |
816 | 6643d27e | bellard | M_SGTU, |
817 | 6643d27e | bellard | M_SGTU_I, |
818 | 6643d27e | bellard | M_SLE, |
819 | 6643d27e | bellard | M_SLE_I, |
820 | 6643d27e | bellard | M_SLEU, |
821 | 6643d27e | bellard | M_SLEU_I, |
822 | 6643d27e | bellard | M_SLT_I, |
823 | 6643d27e | bellard | M_SLTU_I, |
824 | 6643d27e | bellard | M_SNE, |
825 | 6643d27e | bellard | M_SNE_I, |
826 | 6643d27e | bellard | M_SB_A, |
827 | 6643d27e | bellard | M_SB_AB, |
828 | 6643d27e | bellard | M_SH_A, |
829 | 6643d27e | bellard | M_SH_AB, |
830 | 6643d27e | bellard | M_SW_A, |
831 | 6643d27e | bellard | M_SW_AB, |
832 | 6643d27e | bellard | M_SWC0_A, |
833 | 6643d27e | bellard | M_SWC0_AB, |
834 | 6643d27e | bellard | M_SWC1_A, |
835 | 6643d27e | bellard | M_SWC1_AB, |
836 | 6643d27e | bellard | M_SWC2_A, |
837 | 6643d27e | bellard | M_SWC2_AB, |
838 | 6643d27e | bellard | M_SWC3_A, |
839 | 6643d27e | bellard | M_SWC3_AB, |
840 | 6643d27e | bellard | M_SWL_A, |
841 | 6643d27e | bellard | M_SWL_AB, |
842 | 6643d27e | bellard | M_SWR_A, |
843 | 6643d27e | bellard | M_SWR_AB, |
844 | 6643d27e | bellard | M_SUB_I, |
845 | 6643d27e | bellard | M_SUBU_I, |
846 | 6643d27e | bellard | M_SUBU_I_2, |
847 | 6643d27e | bellard | M_TEQ_I, |
848 | 6643d27e | bellard | M_TGE_I, |
849 | 6643d27e | bellard | M_TGEU_I, |
850 | 6643d27e | bellard | M_TLT_I, |
851 | 6643d27e | bellard | M_TLTU_I, |
852 | 6643d27e | bellard | M_TNE_I, |
853 | 6643d27e | bellard | M_TRUNCWD, |
854 | 6643d27e | bellard | M_TRUNCWS, |
855 | 6643d27e | bellard | M_ULD, |
856 | 6643d27e | bellard | M_ULD_A, |
857 | 6643d27e | bellard | M_ULH, |
858 | 6643d27e | bellard | M_ULH_A, |
859 | 6643d27e | bellard | M_ULHU, |
860 | 6643d27e | bellard | M_ULHU_A, |
861 | 6643d27e | bellard | M_ULW, |
862 | 6643d27e | bellard | M_ULW_A, |
863 | 6643d27e | bellard | M_USH, |
864 | 6643d27e | bellard | M_USH_A, |
865 | 6643d27e | bellard | M_USW, |
866 | 6643d27e | bellard | M_USW_A, |
867 | 6643d27e | bellard | M_USD, |
868 | 6643d27e | bellard | M_USD_A, |
869 | 6643d27e | bellard | M_XOR_I, |
870 | 6643d27e | bellard | M_COP0, |
871 | 6643d27e | bellard | M_COP1, |
872 | 6643d27e | bellard | M_COP2, |
873 | 6643d27e | bellard | M_COP3, |
874 | 6643d27e | bellard | M_NUM_MACROS |
875 | 6643d27e | bellard | }; |
876 | 6643d27e | bellard | |
877 | 6643d27e | bellard | |
878 | 6643d27e | bellard | /* The order of overloaded instructions matters. Label arguments and
|
879 | 6643d27e | bellard | register arguments look the same. Instructions that can have either
|
880 | 6643d27e | bellard | for arguments must apear in the correct order in this table for the
|
881 | 6643d27e | bellard | assembler to pick the right one. In other words, entries with
|
882 | 6643d27e | bellard | immediate operands must apear after the same instruction with
|
883 | 6643d27e | bellard | registers.
|
884 | 6643d27e | bellard | |
885 | 6643d27e | bellard | Many instructions are short hand for other instructions (i.e., The
|
886 | 6643d27e | bellard | jal <register> instruction is short for jalr <register>). */
|
887 | 6643d27e | bellard | |
888 | 6643d27e | bellard | extern const struct mips_opcode mips_builtin_opcodes[]; |
889 | 6643d27e | bellard | extern const int bfd_mips_num_builtin_opcodes; |
890 | 6643d27e | bellard | extern struct mips_opcode *mips_opcodes; |
891 | 6643d27e | bellard | extern int bfd_mips_num_opcodes; |
892 | 6643d27e | bellard | #define NUMOPCODES bfd_mips_num_opcodes
|
893 | 6643d27e | bellard | |
894 | 6643d27e | bellard | |
895 | 6643d27e | bellard | /* The rest of this file adds definitions for the mips16 TinyRISC
|
896 | 6643d27e | bellard | processor. */
|
897 | 6643d27e | bellard | |
898 | 6643d27e | bellard | /* These are the bitmasks and shift counts used for the different
|
899 | 6643d27e | bellard | fields in the instruction formats. Other than OP, no masks are
|
900 | 6643d27e | bellard | provided for the fixed portions of an instruction, since they are
|
901 | 6643d27e | bellard | not needed.
|
902 | 6643d27e | bellard | |
903 | 6643d27e | bellard | The I format uses IMM11.
|
904 | 6643d27e | bellard | |
905 | 6643d27e | bellard | The RI format uses RX and IMM8.
|
906 | 6643d27e | bellard | |
907 | 6643d27e | bellard | The RR format uses RX, and RY.
|
908 | 6643d27e | bellard | |
909 | 6643d27e | bellard | The RRI format uses RX, RY, and IMM5.
|
910 | 6643d27e | bellard | |
911 | 6643d27e | bellard | The RRR format uses RX, RY, and RZ.
|
912 | 6643d27e | bellard | |
913 | 6643d27e | bellard | The RRI_A format uses RX, RY, and IMM4.
|
914 | 6643d27e | bellard | |
915 | 6643d27e | bellard | The SHIFT format uses RX, RY, and SHAMT.
|
916 | 6643d27e | bellard | |
917 | 6643d27e | bellard | The I8 format uses IMM8.
|
918 | 6643d27e | bellard | |
919 | 6643d27e | bellard | The I8_MOVR32 format uses RY and REGR32.
|
920 | 6643d27e | bellard | |
921 | 6643d27e | bellard | The IR_MOV32R format uses REG32R and MOV32Z.
|
922 | 6643d27e | bellard | |
923 | 6643d27e | bellard | The I64 format uses IMM8.
|
924 | 6643d27e | bellard | |
925 | 6643d27e | bellard | The RI64 format uses RY and IMM5.
|
926 | 6643d27e | bellard | */
|
927 | 6643d27e | bellard | |
928 | 6643d27e | bellard | #define MIPS16OP_MASK_OP 0x1f |
929 | 6643d27e | bellard | #define MIPS16OP_SH_OP 11 |
930 | 6643d27e | bellard | #define MIPS16OP_MASK_IMM11 0x7ff |
931 | 6643d27e | bellard | #define MIPS16OP_SH_IMM11 0 |
932 | 6643d27e | bellard | #define MIPS16OP_MASK_RX 0x7 |
933 | 6643d27e | bellard | #define MIPS16OP_SH_RX 8 |
934 | 6643d27e | bellard | #define MIPS16OP_MASK_IMM8 0xff |
935 | 6643d27e | bellard | #define MIPS16OP_SH_IMM8 0 |
936 | 6643d27e | bellard | #define MIPS16OP_MASK_RY 0x7 |
937 | 6643d27e | bellard | #define MIPS16OP_SH_RY 5 |
938 | 6643d27e | bellard | #define MIPS16OP_MASK_IMM5 0x1f |
939 | 6643d27e | bellard | #define MIPS16OP_SH_IMM5 0 |
940 | 6643d27e | bellard | #define MIPS16OP_MASK_RZ 0x7 |
941 | 6643d27e | bellard | #define MIPS16OP_SH_RZ 2 |
942 | 6643d27e | bellard | #define MIPS16OP_MASK_IMM4 0xf |
943 | 6643d27e | bellard | #define MIPS16OP_SH_IMM4 0 |
944 | 6643d27e | bellard | #define MIPS16OP_MASK_REGR32 0x1f |
945 | 6643d27e | bellard | #define MIPS16OP_SH_REGR32 0 |
946 | 6643d27e | bellard | #define MIPS16OP_MASK_REG32R 0x1f |
947 | 6643d27e | bellard | #define MIPS16OP_SH_REG32R 3 |
948 | 6643d27e | bellard | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
949 | 6643d27e | bellard | #define MIPS16OP_MASK_MOVE32Z 0x7 |
950 | 6643d27e | bellard | #define MIPS16OP_SH_MOVE32Z 0 |
951 | 6643d27e | bellard | #define MIPS16OP_MASK_IMM6 0x3f |
952 | 6643d27e | bellard | #define MIPS16OP_SH_IMM6 5 |
953 | 6643d27e | bellard | |
954 | 6643d27e | bellard | /* These are the characters which may appears in the args field of an
|
955 | 6643d27e | bellard | instruction. They appear in the order in which the fields appear
|
956 | 6643d27e | bellard | when the instruction is used. Commas and parentheses in the args
|
957 | 6643d27e | bellard | string are ignored when assembling, and written into the output
|
958 | 6643d27e | bellard | when disassembling.
|
959 | 6643d27e | bellard | |
960 | 6643d27e | bellard | "y" 3 bit register (MIPS16OP_*_RY)
|
961 | 6643d27e | bellard | "x" 3 bit register (MIPS16OP_*_RX)
|
962 | 6643d27e | bellard | "z" 3 bit register (MIPS16OP_*_RZ)
|
963 | 6643d27e | bellard | "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
964 | 6643d27e | bellard | "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
965 | 6643d27e | bellard | "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
966 | 6643d27e | bellard | "0" zero register ($0)
|
967 | 6643d27e | bellard | "S" stack pointer ($sp or $29)
|
968 | 6643d27e | bellard | "P" program counter
|
969 | 6643d27e | bellard | "R" return address register ($ra or $31)
|
970 | 6643d27e | bellard | "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
971 | 6643d27e | bellard | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
972 | 6643d27e | bellard | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
973 | 6643d27e | bellard | "a" 26 bit jump address
|
974 | 6643d27e | bellard | "e" 11 bit extension value
|
975 | 6643d27e | bellard | "l" register list for entry instruction
|
976 | 6643d27e | bellard | "L" register list for exit instruction
|
977 | 6643d27e | bellard | |
978 | 6643d27e | bellard | The remaining codes may be extended. Except as otherwise noted,
|
979 | 6643d27e | bellard | the full extended operand is a 16 bit signed value.
|
980 | 6643d27e | bellard | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
981 | 6643d27e | bellard | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
982 | 6643d27e | bellard | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
983 | 6643d27e | bellard | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
984 | 6643d27e | bellard | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
985 | 6643d27e | bellard | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
986 | 6643d27e | bellard | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
987 | 6643d27e | bellard | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
988 | 6643d27e | bellard | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
989 | 6643d27e | bellard | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
990 | 6643d27e | bellard | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
991 | 6643d27e | bellard | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
992 | 6643d27e | bellard | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
993 | 6643d27e | bellard | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
994 | 6643d27e | bellard | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
995 | 6643d27e | bellard | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
996 | 6643d27e | bellard | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
997 | 6643d27e | bellard | "q" 11 bit branch address (MIPS16OP_*_IMM11)
|
998 | 6643d27e | bellard | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
999 | 6643d27e | bellard | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
1000 | 6643d27e | bellard | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
1001 | 6643d27e | bellard | */
|
1002 | 6643d27e | bellard | |
1003 | 29490584 | ths | /* Save/restore encoding for the args field when all 4 registers are
|
1004 | 29490584 | ths | either saved as arguments or saved/restored as statics. */
|
1005 | 29490584 | ths | #define MIPS16_ALL_ARGS 0xe |
1006 | 29490584 | ths | #define MIPS16_ALL_STATICS 0xb |
1007 | 29490584 | ths | |
1008 | 6643d27e | bellard | /* For the mips16, we use the same opcode table format and a few of
|
1009 | 6643d27e | bellard | the same flags. However, most of the flags are different. */
|
1010 | 6643d27e | bellard | |
1011 | 6643d27e | bellard | /* Modifies the register in MIPS16OP_*_RX. */
|
1012 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_X 0x00000001 |
1013 | 6643d27e | bellard | /* Modifies the register in MIPS16OP_*_RY. */
|
1014 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_Y 0x00000002 |
1015 | 6643d27e | bellard | /* Modifies the register in MIPS16OP_*_RZ. */
|
1016 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_Z 0x00000004 |
1017 | 6643d27e | bellard | /* Modifies the T ($24) register. */
|
1018 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_T 0x00000008 |
1019 | 6643d27e | bellard | /* Modifies the SP ($29) register. */
|
1020 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_SP 0x00000010 |
1021 | 6643d27e | bellard | /* Modifies the RA ($31) register. */
|
1022 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_31 0x00000020 |
1023 | 6643d27e | bellard | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
1024 | 6643d27e | bellard | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
1025 | 6643d27e | bellard | /* Reads the register in MIPS16OP_*_RX. */
|
1026 | 6643d27e | bellard | #define MIPS16_INSN_READ_X 0x00000080 |
1027 | 6643d27e | bellard | /* Reads the register in MIPS16OP_*_RY. */
|
1028 | 6643d27e | bellard | #define MIPS16_INSN_READ_Y 0x00000100 |
1029 | 6643d27e | bellard | /* Reads the register in MIPS16OP_*_MOVE32Z. */
|
1030 | 6643d27e | bellard | #define MIPS16_INSN_READ_Z 0x00000200 |
1031 | 6643d27e | bellard | /* Reads the T ($24) register. */
|
1032 | 6643d27e | bellard | #define MIPS16_INSN_READ_T 0x00000400 |
1033 | 6643d27e | bellard | /* Reads the SP ($29) register. */
|
1034 | 6643d27e | bellard | #define MIPS16_INSN_READ_SP 0x00000800 |
1035 | 6643d27e | bellard | /* Reads the RA ($31) register. */
|
1036 | 6643d27e | bellard | #define MIPS16_INSN_READ_31 0x00001000 |
1037 | 6643d27e | bellard | /* Reads the program counter. */
|
1038 | 6643d27e | bellard | #define MIPS16_INSN_READ_PC 0x00002000 |
1039 | 6643d27e | bellard | /* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
1040 | 6643d27e | bellard | #define MIPS16_INSN_READ_GPR_X 0x00004000 |
1041 | 6643d27e | bellard | /* Is a branch insn. */
|
1042 | 6643d27e | bellard | #define MIPS16_INSN_BRANCH 0x00010000 |
1043 | 6643d27e | bellard | |
1044 | 6643d27e | bellard | /* The following flags have the same value for the mips16 opcode
|
1045 | 6643d27e | bellard | table:
|
1046 | 6643d27e | bellard | INSN_UNCOND_BRANCH_DELAY
|
1047 | 6643d27e | bellard | INSN_COND_BRANCH_DELAY
|
1048 | 6643d27e | bellard | INSN_COND_BRANCH_LIKELY (never used)
|
1049 | 6643d27e | bellard | INSN_READ_HI
|
1050 | 6643d27e | bellard | INSN_READ_LO
|
1051 | 6643d27e | bellard | INSN_WRITE_HI
|
1052 | 6643d27e | bellard | INSN_WRITE_LO
|
1053 | 6643d27e | bellard | INSN_TRAP
|
1054 | 6643d27e | bellard | INSN_ISA3
|
1055 | 6643d27e | bellard | */
|
1056 | 6643d27e | bellard | |
1057 | 6643d27e | bellard | extern const struct mips_opcode mips16_opcodes[]; |
1058 | 6643d27e | bellard | extern const int bfd_mips16_num_opcodes; |
1059 | 6643d27e | bellard | |
1060 | 6643d27e | bellard | /* Short hand so the lines aren't too long. */
|
1061 | 6643d27e | bellard | |
1062 | 6643d27e | bellard | #define LDD INSN_LOAD_MEMORY_DELAY
|
1063 | 6643d27e | bellard | #define LCD INSN_LOAD_COPROC_DELAY
|
1064 | 6643d27e | bellard | #define UBD INSN_UNCOND_BRANCH_DELAY
|
1065 | 6643d27e | bellard | #define CBD INSN_COND_BRANCH_DELAY
|
1066 | 6643d27e | bellard | #define COD INSN_COPROC_MOVE_DELAY
|
1067 | 6643d27e | bellard | #define CLD INSN_COPROC_MEMORY_DELAY
|
1068 | 6643d27e | bellard | #define CBL INSN_COND_BRANCH_LIKELY
|
1069 | 6643d27e | bellard | #define TRAP INSN_TRAP
|
1070 | 6643d27e | bellard | #define SM INSN_STORE_MEMORY
|
1071 | 6643d27e | bellard | |
1072 | 6643d27e | bellard | #define WR_d INSN_WRITE_GPR_D
|
1073 | 6643d27e | bellard | #define WR_t INSN_WRITE_GPR_T
|
1074 | 6643d27e | bellard | #define WR_31 INSN_WRITE_GPR_31
|
1075 | 6643d27e | bellard | #define WR_D INSN_WRITE_FPR_D
|
1076 | 6643d27e | bellard | #define WR_T INSN_WRITE_FPR_T
|
1077 | 6643d27e | bellard | #define WR_S INSN_WRITE_FPR_S
|
1078 | 6643d27e | bellard | #define RD_s INSN_READ_GPR_S
|
1079 | 6643d27e | bellard | #define RD_b INSN_READ_GPR_S
|
1080 | 6643d27e | bellard | #define RD_t INSN_READ_GPR_T
|
1081 | 6643d27e | bellard | #define RD_S INSN_READ_FPR_S
|
1082 | 6643d27e | bellard | #define RD_T INSN_READ_FPR_T
|
1083 | 6643d27e | bellard | #define RD_R INSN_READ_FPR_R
|
1084 | 6643d27e | bellard | #define WR_CC INSN_WRITE_COND_CODE
|
1085 | 6643d27e | bellard | #define RD_CC INSN_READ_COND_CODE
|
1086 | 6643d27e | bellard | #define RD_C0 INSN_COP
|
1087 | 6643d27e | bellard | #define RD_C1 INSN_COP
|
1088 | 6643d27e | bellard | #define RD_C2 INSN_COP
|
1089 | 6643d27e | bellard | #define RD_C3 INSN_COP
|
1090 | 6643d27e | bellard | #define WR_C0 INSN_COP
|
1091 | 6643d27e | bellard | #define WR_C1 INSN_COP
|
1092 | 6643d27e | bellard | #define WR_C2 INSN_COP
|
1093 | 6643d27e | bellard | #define WR_C3 INSN_COP
|
1094 | 6643d27e | bellard | |
1095 | 6643d27e | bellard | #define WR_HI INSN_WRITE_HI
|
1096 | 6643d27e | bellard | #define RD_HI INSN_READ_HI
|
1097 | 6643d27e | bellard | #define MOD_HI WR_HI|RD_HI
|
1098 | 6643d27e | bellard | |
1099 | 6643d27e | bellard | #define WR_LO INSN_WRITE_LO
|
1100 | 6643d27e | bellard | #define RD_LO INSN_READ_LO
|
1101 | 6643d27e | bellard | #define MOD_LO WR_LO|RD_LO
|
1102 | 6643d27e | bellard | |
1103 | 6643d27e | bellard | #define WR_HILO WR_HI|WR_LO
|
1104 | 6643d27e | bellard | #define RD_HILO RD_HI|RD_LO
|
1105 | 6643d27e | bellard | #define MOD_HILO WR_HILO|RD_HILO
|
1106 | 6643d27e | bellard | |
1107 | 6643d27e | bellard | #define IS_M INSN_MULT
|
1108 | 6643d27e | bellard | |
1109 | 29490584 | ths | #define WR_MACC INSN2_WRITE_MDMX_ACC
|
1110 | 29490584 | ths | #define RD_MACC INSN2_READ_MDMX_ACC
|
1111 | 6643d27e | bellard | |
1112 | 6643d27e | bellard | #define I1 INSN_ISA1
|
1113 | 6643d27e | bellard | #define I2 INSN_ISA2
|
1114 | 6643d27e | bellard | #define I3 INSN_ISA3
|
1115 | 6643d27e | bellard | #define I4 INSN_ISA4
|
1116 | 6643d27e | bellard | #define I5 INSN_ISA5
|
1117 | 6643d27e | bellard | #define I32 INSN_ISA32
|
1118 | 6643d27e | bellard | #define I64 INSN_ISA64
|
1119 | 6643d27e | bellard | #define I33 INSN_ISA32R2
|
1120 | 6643d27e | bellard | #define I65 INSN_ISA64R2
|
1121 | 6643d27e | bellard | |
1122 | 6643d27e | bellard | /* MIPS64 MIPS-3D ASE support. */
|
1123 | 6643d27e | bellard | #define I16 INSN_MIPS16
|
1124 | 6643d27e | bellard | |
1125 | 29490584 | ths | /* MIPS32 SmartMIPS ASE support. */
|
1126 | 29490584 | ths | #define SMT INSN_SMARTMIPS
|
1127 | 29490584 | ths | |
1128 | 6643d27e | bellard | /* MIPS64 MIPS-3D ASE support. */
|
1129 | 6643d27e | bellard | #define M3D INSN_MIPS3D
|
1130 | 6643d27e | bellard | |
1131 | 6643d27e | bellard | /* MIPS64 MDMX ASE support. */
|
1132 | 6643d27e | bellard | #define MX INSN_MDMX
|
1133 | 6643d27e | bellard | |
1134 | 6643d27e | bellard | #define P3 INSN_4650
|
1135 | 6643d27e | bellard | #define L1 INSN_4010
|
1136 | 6643d27e | bellard | #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
|
1137 | 6643d27e | bellard | #define T3 INSN_3900
|
1138 | 6643d27e | bellard | #define M1 INSN_10000
|
1139 | 6643d27e | bellard | #define SB1 INSN_SB1
|
1140 | 6643d27e | bellard | #define N411 INSN_4111
|
1141 | 6643d27e | bellard | #define N412 INSN_4120
|
1142 | 6643d27e | bellard | #define N5 (INSN_5400 | INSN_5500)
|
1143 | 6643d27e | bellard | #define N54 INSN_5400
|
1144 | 6643d27e | bellard | #define N55 INSN_5500
|
1145 | 6643d27e | bellard | |
1146 | 6643d27e | bellard | #define G1 (T3 \
|
1147 | 6643d27e | bellard | ) |
1148 | 6643d27e | bellard | |
1149 | 6643d27e | bellard | #define G2 (T3 \
|
1150 | 6643d27e | bellard | ) |
1151 | 6643d27e | bellard | |
1152 | 6643d27e | bellard | #define G3 (I4 \
|
1153 | 6643d27e | bellard | ) |
1154 | 6643d27e | bellard | |
1155 | 29490584 | ths | /* MIPS DSP ASE support.
|
1156 | 29490584 | ths | NOTE:
|
1157 | 29490584 | ths | 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
|
1158 | 29490584 | ths | of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
|
1159 | 29490584 | ths | the same structure as $ac0 (HI + LO). For DSP instructions that write or
|
1160 | 29490584 | ths | read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
|
1161 | 29490584 | ths | (RD_HILO) attributes, such that HILO dependencies are maintained
|
1162 | 29490584 | ths | conservatively.
|
1163 | 29490584 | ths | |
1164 | 29490584 | ths | 2. For some mul. instructions that use integer registers as destinations
|
1165 | 29490584 | ths | but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
|
1166 | 29490584 | ths | |
1167 | 29490584 | ths | 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
|
1168 | 29490584 | ths | (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
|
1169 | 29490584 | ths | certain fields of the DSP control register. For simplicity, we decide not
|
1170 | 29490584 | ths | to track dependencies of these fields.
|
1171 | 29490584 | ths | However, "bposge32" is a branch instruction that depends on the "pos"
|
1172 | 29490584 | ths | field. In order to make sure that GAS does not reorder DSP instructions
|
1173 | 29490584 | ths | that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
|
1174 | 29490584 | ths | attribute to those instructions that write the "pos" field. */
|
1175 | 29490584 | ths | |
1176 | 29490584 | ths | #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ |
1177 | 29490584 | ths | #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ |
1178 | 29490584 | ths | #define MOD_a WR_a|RD_a
|
1179 | 29490584 | ths | #define DSP_VOLA INSN_TRAP
|
1180 | 29490584 | ths | #define D32 INSN_DSP
|
1181 | 29490584 | ths | #define D33 INSN_DSPR2
|
1182 | 29490584 | ths | #define D64 INSN_DSP64
|
1183 | 29490584 | ths | |
1184 | 29490584 | ths | /* MIPS MT ASE support. */
|
1185 | 29490584 | ths | #define MT32 INSN_MT
|
1186 | 29490584 | ths | |
1187 | 6643d27e | bellard | /* The order of overloaded instructions matters. Label arguments and
|
1188 | 6643d27e | bellard | register arguments look the same. Instructions that can have either
|
1189 | 6643d27e | bellard | for arguments must apear in the correct order in this table for the
|
1190 | 6643d27e | bellard | assembler to pick the right one. In other words, entries with
|
1191 | 6643d27e | bellard | immediate operands must apear after the same instruction with
|
1192 | 6643d27e | bellard | registers.
|
1193 | 6643d27e | bellard | |
1194 | 6643d27e | bellard | Because of the lookup algorithm used, entries with the same opcode
|
1195 | 6643d27e | bellard | name must be contiguous.
|
1196 | 5fafdf24 | ths | |
1197 | 6643d27e | bellard | Many instructions are short hand for other instructions (i.e., The
|
1198 | 6643d27e | bellard | jal <register> instruction is short for jalr <register>). */
|
1199 | 6643d27e | bellard | |
1200 | 6643d27e | bellard | const struct mips_opcode mips_builtin_opcodes[] = |
1201 | 6643d27e | bellard | { |
1202 | 6643d27e | bellard | /* These instructions appear first so that the disassembler will find
|
1203 | 6643d27e | bellard | them first. The assemblers uses a hash table based on the
|
1204 | 6643d27e | bellard | instruction name anyhow. */
|
1205 | 6643d27e | bellard | /* name, args, match, mask, pinfo, membership */
|
1206 | 29490584 | ths | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, |
1207 | 29490584 | ths | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, |
1208 | 29490584 | ths | {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ |
1209 | 29490584 | ths | {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ |
1210 | 29490584 | ths | {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ |
1211 | 29490584 | ths | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ |
1212 | 29490584 | ths | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ |
1213 | 29490584 | ths | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, |
1214 | 29490584 | ths | {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, |
1215 | 29490584 | ths | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ |
1216 | 29490584 | ths | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ |
1217 | 29490584 | ths | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ |
1218 | 29490584 | ths | {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ |
1219 | 29490584 | ths | {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ |
1220 | 29490584 | ths | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ |
1221 | 29490584 | ths | |
1222 | 29490584 | ths | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, |
1223 | 29490584 | ths | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
1224 | 29490584 | ths | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, |
1225 | 29490584 | ths | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, |
1226 | 29490584 | ths | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
1227 | 29490584 | ths | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, |
1228 | 29490584 | ths | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
1229 | 29490584 | ths | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, |
1230 | 29490584 | ths | {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1231 | 29490584 | ths | {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1232 | 29490584 | ths | {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
1233 | 29490584 | ths | {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1234 | 29490584 | ths | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
1235 | 29490584 | ths | {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1236 | 29490584 | ths | {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1237 | 29490584 | ths | {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1238 | 29490584 | ths | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
1239 | 29490584 | ths | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
1240 | 29490584 | ths | {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1241 | 29490584 | ths | {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1242 | 29490584 | ths | {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
1243 | 29490584 | ths | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
1244 | 29490584 | ths | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, |
1245 | 29490584 | ths | {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1246 | 29490584 | ths | {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, |
1247 | 29490584 | ths | {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1248 | 29490584 | ths | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
1249 | 29490584 | ths | {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, |
1250 | 29490584 | ths | {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, |
1251 | 29490584 | ths | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
1252 | 29490584 | ths | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, |
1253 | 29490584 | ths | {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1254 | 29490584 | ths | {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1255 | 29490584 | ths | {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
1256 | 29490584 | ths | {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1257 | 29490584 | ths | {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1258 | 29490584 | ths | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
1259 | 6643d27e | bellard | /* b is at the top of the table. */
|
1260 | 6643d27e | bellard | /* bal is at the top of the table. */
|
1261 | 29490584 | ths | /* bc0[tf]l? are at the bottom of the table. */
|
1262 | 29490584 | ths | {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
1263 | 29490584 | ths | {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
1264 | 29490584 | ths | {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
1265 | 29490584 | ths | {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
1266 | 29490584 | ths | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, |
1267 | 29490584 | ths | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, |
1268 | 29490584 | ths | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, |
1269 | 29490584 | ths | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, |
1270 | 29490584 | ths | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, |
1271 | 29490584 | ths | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, |
1272 | 29490584 | ths | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, |
1273 | 29490584 | ths | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, |
1274 | 6643d27e | bellard | /* bc2* are at the bottom of the table. */
|
1275 | 29490584 | ths | /* bc3* are at the bottom of the table. */
|
1276 | 29490584 | ths | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1277 | 29490584 | ths | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1278 | 29490584 | ths | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, |
1279 | 29490584 | ths | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, |
1280 | 29490584 | ths | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, |
1281 | 29490584 | ths | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, |
1282 | 29490584 | ths | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, |
1283 | 29490584 | ths | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, |
1284 | 29490584 | ths | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, |
1285 | 29490584 | ths | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, |
1286 | 29490584 | ths | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, |
1287 | 29490584 | ths | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, |
1288 | 29490584 | ths | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, |
1289 | 29490584 | ths | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, |
1290 | 29490584 | ths | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1291 | 29490584 | ths | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1292 | 29490584 | ths | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, |
1293 | 29490584 | ths | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, |
1294 | 29490584 | ths | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, |
1295 | 29490584 | ths | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, |
1296 | 29490584 | ths | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, |
1297 | 29490584 | ths | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, |
1298 | 29490584 | ths | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, |
1299 | 29490584 | ths | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, |
1300 | 29490584 | ths | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, |
1301 | 29490584 | ths | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, |
1302 | 29490584 | ths | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1303 | 29490584 | ths | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1304 | 29490584 | ths | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, |
1305 | 29490584 | ths | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, |
1306 | 29490584 | ths | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, |
1307 | 29490584 | ths | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, |
1308 | 29490584 | ths | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, |
1309 | 29490584 | ths | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, |
1310 | 29490584 | ths | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, |
1311 | 29490584 | ths | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, |
1312 | 29490584 | ths | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1313 | 29490584 | ths | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1314 | 29490584 | ths | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, |
1315 | 29490584 | ths | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, |
1316 | 29490584 | ths | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, |
1317 | 29490584 | ths | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, |
1318 | 29490584 | ths | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, |
1319 | 29490584 | ths | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, |
1320 | 29490584 | ths | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, |
1321 | 29490584 | ths | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, |
1322 | 29490584 | ths | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1323 | 29490584 | ths | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1324 | 29490584 | ths | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, |
1325 | 29490584 | ths | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, |
1326 | 29490584 | ths | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
1327 | 29490584 | ths | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
1328 | 29490584 | ths | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, |
1329 | 29490584 | ths | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, |
1330 | 29490584 | ths | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, |
1331 | 29490584 | ths | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, |
1332 | 29490584 | ths | {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, |
1333 | 29490584 | ths | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, |
1334 | 29490584 | ths | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, |
1335 | 29490584 | ths | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1336 | 29490584 | ths | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1337 | 29490584 | ths | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1338 | 29490584 | ths | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1339 | 29490584 | ths | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1340 | 29490584 | ths | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1341 | 29490584 | ths | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1342 | 29490584 | ths | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1343 | 29490584 | ths | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1344 | 29490584 | ths | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1345 | 29490584 | ths | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1346 | 29490584 | ths | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1347 | 29490584 | ths | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1348 | 29490584 | ths | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1349 | 29490584 | ths | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1350 | 29490584 | ths | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1351 | 29490584 | ths | {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1352 | 29490584 | ths | {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1353 | 29490584 | ths | {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1354 | 29490584 | ths | {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1355 | 29490584 | ths | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1356 | 29490584 | ths | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1357 | 29490584 | ths | {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
1358 | 29490584 | ths | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1359 | 29490584 | ths | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1360 | 29490584 | ths | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1361 | 29490584 | ths | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1362 | 29490584 | ths | {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1363 | 29490584 | ths | {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1364 | 29490584 | ths | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1365 | 29490584 | ths | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1366 | 29490584 | ths | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1367 | 29490584 | ths | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1368 | 29490584 | ths | {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1369 | 29490584 | ths | {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1370 | 29490584 | ths | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1371 | 29490584 | ths | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1372 | 29490584 | ths | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1373 | 29490584 | ths | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1374 | 29490584 | ths | {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1375 | 29490584 | ths | {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1376 | 29490584 | ths | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1377 | 29490584 | ths | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1378 | 29490584 | ths | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1379 | 29490584 | ths | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1380 | 29490584 | ths | {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1381 | 29490584 | ths | {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1382 | 29490584 | ths | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1383 | 29490584 | ths | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1384 | 29490584 | ths | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1385 | 29490584 | ths | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1386 | 29490584 | ths | {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1387 | 29490584 | ths | {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1388 | 29490584 | ths | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1389 | 29490584 | ths | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1390 | 29490584 | ths | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1391 | 29490584 | ths | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1392 | 29490584 | ths | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1393 | 29490584 | ths | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1394 | 29490584 | ths | {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1395 | 29490584 | ths | {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1396 | 29490584 | ths | {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1397 | 29490584 | ths | {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1398 | 29490584 | ths | {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1399 | 29490584 | ths | {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1400 | 29490584 | ths | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1401 | 29490584 | ths | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1402 | 29490584 | ths | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1403 | 29490584 | ths | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1404 | 29490584 | ths | {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1405 | 29490584 | ths | {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1406 | 29490584 | ths | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1407 | 29490584 | ths | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1408 | 29490584 | ths | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1409 | 29490584 | ths | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1410 | 29490584 | ths | {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1411 | 29490584 | ths | {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1412 | 29490584 | ths | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1413 | 29490584 | ths | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1414 | 29490584 | ths | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1415 | 29490584 | ths | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1416 | 29490584 | ths | {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1417 | 29490584 | ths | {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1418 | 29490584 | ths | {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1419 | 29490584 | ths | {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1420 | 29490584 | ths | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1421 | 29490584 | ths | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1422 | 29490584 | ths | {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
1423 | 29490584 | ths | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1424 | 29490584 | ths | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1425 | 29490584 | ths | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1426 | 29490584 | ths | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1427 | 29490584 | ths | {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1428 | 29490584 | ths | {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1429 | 29490584 | ths | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1430 | 29490584 | ths | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1431 | 29490584 | ths | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1432 | 29490584 | ths | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1433 | 29490584 | ths | {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1434 | 29490584 | ths | {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1435 | 29490584 | ths | {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1436 | 29490584 | ths | {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1437 | 29490584 | ths | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1438 | 29490584 | ths | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1439 | 29490584 | ths | {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
1440 | 29490584 | ths | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, |
1441 | 29490584 | ths | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, |
1442 | 29490584 | ths | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
1443 | 29490584 | ths | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, |
1444 | 29490584 | ths | {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1445 | 29490584 | ths | {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, |
1446 | 29490584 | ths | {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1447 | 29490584 | ths | {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1448 | 29490584 | ths | {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1449 | 29490584 | ths | {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1450 | 29490584 | ths | {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1451 | 29490584 | ths | {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1452 | 29490584 | ths | {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1453 | 29490584 | ths | {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1454 | 29490584 | ths | {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1455 | 29490584 | ths | {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1456 | 29490584 | ths | {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1457 | 29490584 | ths | {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1458 | 29490584 | ths | {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1459 | 29490584 | ths | {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1460 | 29490584 | ths | {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1461 | 29490584 | ths | {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1462 | 29490584 | ths | {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1463 | 29490584 | ths | {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1464 | 29490584 | ths | {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1465 | 29490584 | ths | {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1466 | 29490584 | ths | {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1467 | 29490584 | ths | {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1468 | 29490584 | ths | {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1469 | 29490584 | ths | {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1470 | 29490584 | ths | {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1471 | 29490584 | ths | {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1472 | 29490584 | ths | {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1473 | 29490584 | ths | {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1474 | 29490584 | ths | {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1475 | 29490584 | ths | {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1476 | 29490584 | ths | {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1477 | 29490584 | ths | {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1478 | 29490584 | ths | {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1479 | 29490584 | ths | {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1480 | 29490584 | ths | {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1481 | 29490584 | ths | {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1482 | 29490584 | ths | {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1483 | 29490584 | ths | {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1484 | 29490584 | ths | {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1485 | 29490584 | ths | {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1486 | 29490584 | ths | {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1487 | 29490584 | ths | {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1488 | 29490584 | ths | {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1489 | 29490584 | ths | {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1490 | 29490584 | ths | {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1491 | 29490584 | ths | {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1492 | 29490584 | ths | {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
1493 | 29490584 | ths | {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
1494 | 29490584 | ths | /* CW4010 instructions which are aliases for the cache instruction. */
|
1495 | 29490584 | ths | {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, |
1496 | 29490584 | ths | {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, |
1497 | 29490584 | ths | {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, |
1498 | 29490584 | ths | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, |
1499 | 29490584 | ths | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, |
1500 | 29490584 | ths | {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, |
1501 | 29490584 | ths | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
1502 | 29490584 | ths | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
1503 | 29490584 | ths | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, |
1504 | 29490584 | ths | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
1505 | 29490584 | ths | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, |
1506 | 29490584 | ths | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, |
1507 | 29490584 | ths | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, |
1508 | 6643d27e | bellard | /* cfc2 is at the bottom of the table. */
|
1509 | 29490584 | ths | /* cfc3 is at the bottom of the table. */
|
1510 | 29490584 | ths | {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, |
1511 | 29490584 | ths | {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, |
1512 | 29490584 | ths | {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, |
1513 | 29490584 | ths | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, |
1514 | 29490584 | ths | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, |
1515 | 29490584 | ths | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, |
1516 | 29490584 | ths | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, |
1517 | 29490584 | ths | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, |
1518 | 6643d27e | bellard | /* ctc2 is at the bottom of the table. */
|
1519 | 29490584 | ths | /* ctc3 is at the bottom of the table. */
|
1520 | 29490584 | ths | {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, |
1521 | 29490584 | ths | {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, |
1522 | 29490584 | ths | {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, |
1523 | 29490584 | ths | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
1524 | 29490584 | ths | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, |
1525 | 29490584 | ths | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, |
1526 | 29490584 | ths | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
1527 | 29490584 | ths | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
1528 | 29490584 | ths | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
1529 | 29490584 | ths | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, |
1530 | 29490584 | ths | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
1531 | 29490584 | ths | {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, |
1532 | 29490584 | ths | {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, |
1533 | 29490584 | ths | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, |
1534 | 29490584 | ths | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
1535 | 29490584 | ths | {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, |
1536 | 29490584 | ths | {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, |
1537 | 29490584 | ths | {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, |
1538 | 29490584 | ths | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, |
1539 | 29490584 | ths | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
1540 | 29490584 | ths | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, |
1541 | 29490584 | ths | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, |
1542 | 29490584 | ths | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, |
1543 | 29490584 | ths | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
1544 | 29490584 | ths | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, |
1545 | 29490584 | ths | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, |
1546 | 29490584 | ths | {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, |
1547 | 29490584 | ths | {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, |
1548 | 6643d27e | bellard | /* dctr and dctw are used on the r5000. */
|
1549 | 29490584 | ths | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, |
1550 | 29490584 | ths | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, |
1551 | 29490584 | ths | {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, |
1552 | 29490584 | ths | {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, |
1553 | 29490584 | ths | {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1554 | 29490584 | ths | {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1555 | 29490584 | ths | {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1556 | 6643d27e | bellard | /* For ddiv, see the comments about div. */
|
1557 | 29490584 | ths | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1558 | 29490584 | ths | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, |
1559 | 29490584 | ths | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, |
1560 | 6643d27e | bellard | /* For ddivu, see the comments about div. */
|
1561 | 29490584 | ths | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1562 | 29490584 | ths | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, |
1563 | 29490584 | ths | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, |
1564 | 29490584 | ths | {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, |
1565 | 29490584 | ths | {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, |
1566 | 29490584 | ths | {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, |
1567 | 29490584 | ths | {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1568 | 29490584 | ths | {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1569 | 29490584 | ths | {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
1570 | 6643d27e | bellard | /* The MIPS assembler treats the div opcode with two operands as
|
1571 | 6643d27e | bellard | though the first operand appeared twice (the first operand is both
|
1572 | 6643d27e | bellard | a source and a destination). To get the div machine instruction,
|
1573 | 6643d27e | bellard | you must use an explicit destination of $0. */
|
1574 | 29490584 | ths | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1575 | 29490584 | ths | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1576 | 29490584 | ths | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, |
1577 | 29490584 | ths | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, |
1578 | 29490584 | ths | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, |
1579 | 29490584 | ths | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
1580 | 29490584 | ths | {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
1581 | 6643d27e | bellard | /* For divu, see the comments about div. */
|
1582 | 29490584 | ths | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1583 | 29490584 | ths | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1584 | 29490584 | ths | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, |
1585 | 29490584 | ths | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, |
1586 | 29490584 | ths | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, |
1587 | 29490584 | ths | {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, |
1588 | 29490584 | ths | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ |
1589 | 29490584 | ths | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ |
1590 | 29490584 | ths | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, |
1591 | 29490584 | ths | {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1592 | 29490584 | ths | {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1593 | 29490584 | ths | {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1594 | 29490584 | ths | {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1595 | 29490584 | ths | {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1596 | 29490584 | ths | {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1597 | 29490584 | ths | {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1598 | 29490584 | ths | {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
1599 | 29490584 | ths | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, |
1600 | 29490584 | ths | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, |
1601 | 29490584 | ths | {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, |
1602 | 29490584 | ths | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, |
1603 | 29490584 | ths | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, |
1604 | 29490584 | ths | {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
1605 | 29490584 | ths | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, |
1606 | 29490584 | ths | {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, |
1607 | 29490584 | ths | {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, |
1608 | 29490584 | ths | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, |
1609 | 29490584 | ths | {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, |
1610 | 29490584 | ths | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, |
1611 | 29490584 | ths | {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, |
1612 | 6643d27e | bellard | /* dmfc2 is at the bottom of the table. */
|
1613 | 6643d27e | bellard | /* dmtc2 is at the bottom of the table. */
|
1614 | 29490584 | ths | /* dmfc3 is at the bottom of the table. */
|
1615 | 29490584 | ths | /* dmtc3 is at the bottom of the table. */
|
1616 | 29490584 | ths | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, |
1617 | 29490584 | ths | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, |
1618 | 29490584 | ths | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, |
1619 | 29490584 | ths | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, |
1620 | 29490584 | ths | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, |
1621 | 29490584 | ths | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, |
1622 | 29490584 | ths | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1623 | 29490584 | ths | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1624 | 29490584 | ths | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ |
1625 | 29490584 | ths | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ |
1626 | 29490584 | ths | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1627 | 29490584 | ths | {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, |
1628 | 29490584 | ths | {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, |
1629 | 29490584 | ths | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1630 | 29490584 | ths | {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, |
1631 | 29490584 | ths | {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, |
1632 | 29490584 | ths | {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, |
1633 | 29490584 | ths | {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, |
1634 | 29490584 | ths | {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, |
1635 | 29490584 | ths | {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, |
1636 | 29490584 | ths | {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, |
1637 | 29490584 | ths | {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, |
1638 | 29490584 | ths | {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, |
1639 | 29490584 | ths | {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, |
1640 | 29490584 | ths | {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, |
1641 | 29490584 | ths | {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, |
1642 | 29490584 | ths | {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, |
1643 | 29490584 | ths | {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, |
1644 | 29490584 | ths | {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, |
1645 | 29490584 | ths | {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, |
1646 | 29490584 | ths | {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, |
1647 | 29490584 | ths | {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, |
1648 | 29490584 | ths | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
1649 | 29490584 | ths | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1650 | 29490584 | ths | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ |
1651 | 29490584 | ths | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ |
1652 | 29490584 | ths | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1653 | 29490584 | ths | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
1654 | 29490584 | ths | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1655 | 29490584 | ths | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ |
1656 | 29490584 | ths | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ |
1657 | 29490584 | ths | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1658 | 29490584 | ths | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
1659 | 29490584 | ths | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1660 | 29490584 | ths | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ |
1661 | 29490584 | ths | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ |
1662 | 29490584 | ths | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
1663 | 29490584 | ths | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
1664 | 29490584 | ths | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, |
1665 | 29490584 | ths | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
1666 | 29490584 | ths | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, |
1667 | 29490584 | ths | {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, |
1668 | 29490584 | ths | {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
1669 | 29490584 | ths | {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, |
1670 | 29490584 | ths | {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, |
1671 | 29490584 | ths | {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, |
1672 | 29490584 | ths | {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
1673 | 29490584 | ths | {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, |
1674 | 29490584 | ths | {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, |
1675 | 29490584 | ths | {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
1676 | 29490584 | ths | {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, |
1677 | 29490584 | ths | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
1678 | 29490584 | ths | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
1679 | 29490584 | ths | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, |
1680 | 29490584 | ths | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
1681 | 29490584 | ths | {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, |
1682 | 29490584 | ths | {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, |
1683 | 29490584 | ths | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, |
1684 | 29490584 | ths | /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
|
1685 | 29490584 | ths | the same hazard barrier effect. */
|
1686 | 29490584 | ths | {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, |
1687 | 29490584 | ths | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ |
1688 | 6643d27e | bellard | /* SVR4 PIC code requires special handling for j, so it must be a
|
1689 | 6643d27e | bellard | macro. */
|
1690 | 29490584 | ths | {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, |
1691 | 6643d27e | bellard | /* This form of j is used by the disassembler and internally by the
|
1692 | 6643d27e | bellard | assembler, but will never match user input (because the line above
|
1693 | 6643d27e | bellard | will match first). */
|
1694 | 29490584 | ths | {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, |
1695 | 29490584 | ths | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, |
1696 | 29490584 | ths | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, |
1697 | 29490584 | ths | /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
|
1698 | 29490584 | ths | with the same hazard barrier effect. */
|
1699 | 29490584 | ths | {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, |
1700 | 29490584 | ths | {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, |
1701 | 6643d27e | bellard | /* SVR4 PIC code requires special handling for jal, so it must be a
|
1702 | 6643d27e | bellard | macro. */
|
1703 | 29490584 | ths | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, |
1704 | 29490584 | ths | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, |
1705 | 29490584 | ths | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, |
1706 | 6643d27e | bellard | /* This form of jal is used by the disassembler and internally by the
|
1707 | 6643d27e | bellard | assembler, but will never match user input (because the line above
|
1708 | 6643d27e | bellard | will match first). */
|
1709 | 29490584 | ths | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, |
1710 | 29490584 | ths | {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, |
1711 | 29490584 | ths | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, |
1712 | 29490584 | ths | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1713 | 29490584 | ths | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, |
1714 | 29490584 | ths | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1715 | 29490584 | ths | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, |
1716 | 29490584 | ths | {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, |
1717 | 29490584 | ths | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, |
1718 | 29490584 | ths | {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, |
1719 | 29490584 | ths | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, |
1720 | 29490584 | ths | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, |
1721 | 29490584 | ths | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, |
1722 | 29490584 | ths | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, |
1723 | 29490584 | ths | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, |
1724 | 29490584 | ths | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ |
1725 | 29490584 | ths | {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, |
1726 | 29490584 | ths | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, |
1727 | 29490584 | ths | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, |
1728 | 29490584 | ths | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, |
1729 | 29490584 | ths | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, |
1730 | 29490584 | ths | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, |
1731 | 29490584 | ths | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, |
1732 | 29490584 | ths | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, |
1733 | 29490584 | ths | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, |
1734 | 29490584 | ths | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, |
1735 | 29490584 | ths | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, |
1736 | 29490584 | ths | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1737 | 29490584 | ths | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, |
1738 | 29490584 | ths | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1739 | 29490584 | ths | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, |
1740 | 6643d27e | bellard | /* li is at the start of the table. */
|
1741 | 29490584 | ths | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, |
1742 | 29490584 | ths | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, |
1743 | 29490584 | ths | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, |
1744 | 29490584 | ths | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, |
1745 | 29490584 | ths | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, |
1746 | 29490584 | ths | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, |
1747 | 29490584 | ths | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, |
1748 | 29490584 | ths | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, |
1749 | 29490584 | ths | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, |
1750 | 29490584 | ths | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, |
1751 | 29490584 | ths | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1752 | 29490584 | ths | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, |
1753 | 29490584 | ths | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, |
1754 | 29490584 | ths | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, |
1755 | 29490584 | ths | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, |
1756 | 29490584 | ths | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, |
1757 | 29490584 | ths | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, |
1758 | 29490584 | ths | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, |
1759 | 29490584 | ths | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ |
1760 | 29490584 | ths | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, |
1761 | 29490584 | ths | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, |
1762 | 29490584 | ths | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, |
1763 | 29490584 | ths | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, |
1764 | 29490584 | ths | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, |
1765 | 29490584 | ths | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1766 | 29490584 | ths | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, |
1767 | 29490584 | ths | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ |
1768 | 29490584 | ths | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ |
1769 | 29490584 | ths | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
1770 | 29490584 | ths | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, |
1771 | 29490584 | ths | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ |
1772 | 29490584 | ths | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ |
1773 | 29490584 | ths | {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, |
1774 | 29490584 | ths | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, |
1775 | 29490584 | ths | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, |
1776 | 29490584 | ths | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, |
1777 | 29490584 | ths | {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, |
1778 | 29490584 | ths | {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1779 | 29490584 | ths | {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1780 | 29490584 | ths | {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1781 | 29490584 | ths | {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1782 | 29490584 | ths | {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1783 | 29490584 | ths | {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1784 | 29490584 | ths | {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1785 | 29490584 | ths | {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1786 | 29490584 | ths | {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1787 | 29490584 | ths | {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1788 | 29490584 | ths | {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1789 | 29490584 | ths | {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
1790 | 29490584 | ths | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, |
1791 | 29490584 | ths | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, |
1792 | 29490584 | ths | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, |
1793 | 29490584 | ths | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, |
1794 | 29490584 | ths | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, |
1795 | 29490584 | ths | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
1796 | 29490584 | ths | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
1797 | 29490584 | ths | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, |
1798 | 29490584 | ths | {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
1799 | 29490584 | ths | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
1800 | 29490584 | ths | {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, |
1801 | 29490584 | ths | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
1802 | 29490584 | ths | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
1803 | 29490584 | ths | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, |
1804 | 29490584 | ths | {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
1805 | 29490584 | ths | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
1806 | 29490584 | ths | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, |
1807 | 29490584 | ths | {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1808 | 29490584 | ths | {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1809 | 29490584 | ths | {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
1810 | 29490584 | ths | {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1811 | 29490584 | ths | {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1812 | 29490584 | ths | {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, |
1813 | 29490584 | ths | {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, |
1814 | 29490584 | ths | {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1815 | 29490584 | ths | {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1816 | 29490584 | ths | {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
1817 | 29490584 | ths | {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
1818 | 29490584 | ths | {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
1819 | 29490584 | ths | {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, |
1820 | 29490584 | ths | {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, |
1821 | 29490584 | ths | {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, |
1822 | 29490584 | ths | {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, |
1823 | 29490584 | ths | {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, |
1824 | 29490584 | ths | {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, |
1825 | 29490584 | ths | {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, |
1826 | 29490584 | ths | {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, |
1827 | 29490584 | ths | {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1828 | 29490584 | ths | {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1829 | 29490584 | ths | {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1830 | 29490584 | ths | {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
1831 | 29490584 | ths | {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, |
1832 | 29490584 | ths | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, |
1833 | 29490584 | ths | {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, |
1834 | 29490584 | ths | {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, |
1835 | 29490584 | ths | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, |
1836 | 29490584 | ths | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, |
1837 | 29490584 | ths | {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, |
1838 | 29490584 | ths | {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, |
1839 | 6643d27e | bellard | /* mfc2 is at the bottom of the table. */
|
1840 | 6643d27e | bellard | /* mfhc2 is at the bottom of the table. */
|
1841 | 29490584 | ths | /* mfc3 is at the bottom of the table. */
|
1842 | 29490584 | ths | {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, |
1843 | 29490584 | ths | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, |
1844 | 29490584 | ths | {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, |
1845 | 29490584 | ths | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, |
1846 | 29490584 | ths | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, |
1847 | 29490584 | ths | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, |
1848 | 29490584 | ths | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1849 | 29490584 | ths | {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1850 | 29490584 | ths | {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
1851 | 29490584 | ths | {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1852 | 29490584 | ths | {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1853 | 29490584 | ths | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, |
1854 | 29490584 | ths | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
1855 | 29490584 | ths | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, |
1856 | 29490584 | ths | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, |
1857 | 29490584 | ths | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, |
1858 | 29490584 | ths | {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
1859 | 29490584 | ths | {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
1860 | 29490584 | ths | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, |
1861 | 29490584 | ths | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, |
1862 | 29490584 | ths | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, |
1863 | 29490584 | ths | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, |
1864 | 29490584 | ths | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, |
1865 | 29490584 | ths | {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
1866 | 29490584 | ths | {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
1867 | 29490584 | ths | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, |
1868 | 29490584 | ths | {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, |
1869 | 29490584 | ths | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, |
1870 | 29490584 | ths | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, |
1871 | 29490584 | ths | {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
1872 | 29490584 | ths | {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
1873 | 29490584 | ths | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, |
1874 | 29490584 | ths | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, |
1875 | 29490584 | ths | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, |
1876 | 29490584 | ths | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, |
1877 | 29490584 | ths | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, |
1878 | 29490584 | ths | {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
1879 | 29490584 | ths | {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
1880 | 29490584 | ths | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, |
1881 | 29490584 | ths | {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, |
1882 | 29490584 | ths | {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1883 | 29490584 | ths | {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1884 | 29490584 | ths | {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1885 | 29490584 | ths | {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1886 | 6643d27e | bellard | /* move is at the top of the table. */
|
1887 | 29490584 | ths | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1888 | 29490584 | ths | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, |
1889 | 29490584 | ths | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, |
1890 | 29490584 | ths | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, |
1891 | 29490584 | ths | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
1892 | 29490584 | ths | {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
1893 | 29490584 | ths | {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
1894 | 29490584 | ths | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
1895 | 29490584 | ths | {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
1896 | 29490584 | ths | {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
1897 | 29490584 | ths | {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, |
1898 | 29490584 | ths | {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, |
1899 | 29490584 | ths | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, |
1900 | 29490584 | ths | {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, |
1901 | 29490584 | ths | {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, |
1902 | 29490584 | ths | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, |
1903 | 29490584 | ths | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, |
1904 | 29490584 | ths | {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, |
1905 | 29490584 | ths | {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, |
1906 | 6643d27e | bellard | /* mtc2 is at the bottom of the table. */
|
1907 | 6643d27e | bellard | /* mthc2 is at the bottom of the table. */
|
1908 | 29490584 | ths | /* mtc3 is at the bottom of the table. */
|
1909 | 29490584 | ths | {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, |
1910 | 29490584 | ths | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, |
1911 | 29490584 | ths | {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, |
1912 | 29490584 | ths | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, |
1913 | 29490584 | ths | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, |
1914 | 29490584 | ths | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, |
1915 | 29490584 | ths | {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
1916 | 29490584 | ths | {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
1917 | 29490584 | ths | {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
1918 | 29490584 | ths | {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, |
1919 | 29490584 | ths | {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, |
1920 | 29490584 | ths | {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, |
1921 | 29490584 | ths | {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
1922 | 29490584 | ths | {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
1923 | 29490584 | ths | {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, |
1924 | 29490584 | ths | {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, |
1925 | 29490584 | ths | {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, |
1926 | 29490584 | ths | {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, |
1927 | 29490584 | ths | {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, |
1928 | 29490584 | ths | {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
1929 | 29490584 | ths | {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
1930 | 29490584 | ths | {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
1931 | 29490584 | ths | {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
1932 | 29490584 | ths | {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, |
1933 | 29490584 | ths | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, |
1934 | 29490584 | ths | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
1935 | 29490584 | ths | {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1936 | 29490584 | ths | {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1937 | 29490584 | ths | {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
1938 | 29490584 | ths | {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
1939 | 29490584 | ths | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
1940 | 29490584 | ths | {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1941 | 29490584 | ths | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, |
1942 | 29490584 | ths | {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, |
1943 | 29490584 | ths | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, |
1944 | 29490584 | ths | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, |
1945 | 29490584 | ths | {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1946 | 29490584 | ths | {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1947 | 29490584 | ths | {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1948 | 29490584 | ths | {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1949 | 29490584 | ths | {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1950 | 29490584 | ths | {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1951 | 29490584 | ths | {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1952 | 29490584 | ths | {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1953 | 29490584 | ths | {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1954 | 29490584 | ths | {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1955 | 29490584 | ths | {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1956 | 29490584 | ths | {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1957 | 29490584 | ths | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, |
1958 | 29490584 | ths | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, |
1959 | 29490584 | ths | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, |
1960 | 29490584 | ths | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, |
1961 | 29490584 | ths | {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
1962 | 29490584 | ths | {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1963 | 29490584 | ths | {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1964 | 29490584 | ths | {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1965 | 29490584 | ths | {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1966 | 29490584 | ths | {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1967 | 29490584 | ths | {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1968 | 29490584 | ths | {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1969 | 29490584 | ths | {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1970 | 29490584 | ths | {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1971 | 29490584 | ths | {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
1972 | 29490584 | ths | {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1973 | 29490584 | ths | {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1974 | 29490584 | ths | {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
1975 | 29490584 | ths | {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
1976 | 29490584 | ths | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, |
1977 | 29490584 | ths | {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, |
1978 | 29490584 | ths | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
1979 | 29490584 | ths | {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, |
1980 | 29490584 | ths | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, |
1981 | 29490584 | ths | {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, |
1982 | 29490584 | ths | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
1983 | 29490584 | ths | {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
1984 | 29490584 | ths | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ |
1985 | 29490584 | ths | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ |
1986 | 29490584 | ths | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, |
1987 | 29490584 | ths | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
1988 | 29490584 | ths | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, |
1989 | 29490584 | ths | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, |
1990 | 29490584 | ths | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, |
1991 | 29490584 | ths | {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, |
1992 | 29490584 | ths | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, |
1993 | 29490584 | ths | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, |
1994 | 29490584 | ths | {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, |
1995 | 6643d27e | bellard | /* nop is at the start of the table. */
|
1996 | 29490584 | ths | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
1997 | 29490584 | ths | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, |
1998 | 29490584 | ths | {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
1999 | 29490584 | ths | {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2000 | 29490584 | ths | {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2001 | 29490584 | ths | {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2002 | 29490584 | ths | {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2003 | 29490584 | ths | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ |
2004 | 29490584 | ths | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2005 | 29490584 | ths | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, |
2006 | 29490584 | ths | {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2007 | 29490584 | ths | {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2008 | 29490584 | ths | {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2009 | 29490584 | ths | {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2010 | 29490584 | ths | {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2011 | 29490584 | ths | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
2012 | 29490584 | ths | {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
2013 | 29490584 | ths | {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, |
2014 | 29490584 | ths | {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
2015 | 29490584 | ths | {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2016 | 29490584 | ths | {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2017 | 29490584 | ths | {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2018 | 29490584 | ths | {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2019 | 29490584 | ths | {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2020 | 29490584 | ths | {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2021 | 29490584 | ths | {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2022 | 29490584 | ths | {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2023 | 29490584 | ths | {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2024 | 29490584 | ths | {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2025 | 29490584 | ths | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2026 | 29490584 | ths | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2027 | 6643d27e | bellard | /* pref and prefx are at the start of the table. */
|
2028 | 29490584 | ths | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2029 | 29490584 | ths | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2030 | 29490584 | ths | {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, |
2031 | 29490584 | ths | {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
2032 | 29490584 | ths | {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, |
2033 | 29490584 | ths | {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
2034 | 29490584 | ths | {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
2035 | 29490584 | ths | {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, |
2036 | 29490584 | ths | {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
2037 | 29490584 | ths | {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
2038 | 29490584 | ths | {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, |
2039 | 29490584 | ths | {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
2040 | 29490584 | ths | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, |
2041 | 29490584 | ths | {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
2042 | 29490584 | ths | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, |
2043 | 29490584 | ths | {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, |
2044 | 29490584 | ths | {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
2045 | 29490584 | ths | {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
2046 | 29490584 | ths | {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
2047 | 29490584 | ths | {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
2048 | 29490584 | ths | {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
2049 | 29490584 | ths | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
2050 | 29490584 | ths | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, |
2051 | 29490584 | ths | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, |
2052 | 29490584 | ths | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
2053 | 29490584 | ths | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, |
2054 | 29490584 | ths | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, |
2055 | 29490584 | ths | {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, |
2056 | 29490584 | ths | {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, |
2057 | 29490584 | ths | {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, |
2058 | 29490584 | ths | {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2059 | 29490584 | ths | {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
2060 | 29490584 | ths | {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2061 | 29490584 | ths | {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2062 | 29490584 | ths | {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
2063 | 29490584 | ths | {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2064 | 29490584 | ths | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, |
2065 | 29490584 | ths | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, |
2066 | 29490584 | ths | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, |
2067 | 29490584 | ths | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, |
2068 | 29490584 | ths | {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, |
2069 | 29490584 | ths | {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, |
2070 | 29490584 | ths | {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, |
2071 | 29490584 | ths | {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, |
2072 | 29490584 | ths | {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, |
2073 | 29490584 | ths | {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, |
2074 | 29490584 | ths | {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, |
2075 | 29490584 | ths | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
2076 | 29490584 | ths | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
2077 | 29490584 | ths | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, |
2078 | 29490584 | ths | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
2079 | 29490584 | ths | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, |
2080 | 29490584 | ths | {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
2081 | 29490584 | ths | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, |
2082 | 29490584 | ths | {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, |
2083 | 29490584 | ths | {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
2084 | 29490584 | ths | {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
2085 | 29490584 | ths | {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
2086 | 29490584 | ths | {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
2087 | 29490584 | ths | {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
2088 | 29490584 | ths | {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2089 | 29490584 | ths | {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
2090 | 29490584 | ths | {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, |
2091 | 29490584 | ths | {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
2092 | 29490584 | ths | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
2093 | 29490584 | ths | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, |
2094 | 29490584 | ths | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, |
2095 | 29490584 | ths | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, |
2096 | 29490584 | ths | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, |
2097 | 29490584 | ths | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, |
2098 | 29490584 | ths | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
2099 | 29490584 | ths | {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, |
2100 | 29490584 | ths | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, |
2101 | 29490584 | ths | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, |
2102 | 29490584 | ths | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, |
2103 | 29490584 | ths | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, |
2104 | 29490584 | ths | {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, |
2105 | 29490584 | ths | {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, |
2106 | 29490584 | ths | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, |
2107 | 29490584 | ths | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, |
2108 | 29490584 | ths | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, |
2109 | 29490584 | ths | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, |
2110 | 29490584 | ths | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, |
2111 | 29490584 | ths | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, |
2112 | 29490584 | ths | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, |
2113 | 29490584 | ths | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, |
2114 | 29490584 | ths | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, |
2115 | 29490584 | ths | {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, |
2116 | 29490584 | ths | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, |
2117 | 29490584 | ths | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
2118 | 29490584 | ths | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, |
2119 | 29490584 | ths | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
2120 | 29490584 | ths | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, |
2121 | 29490584 | ths | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, |
2122 | 29490584 | ths | {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
2123 | 29490584 | ths | {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
2124 | 29490584 | ths | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, |
2125 | 29490584 | ths | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, |
2126 | 29490584 | ths | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, |
2127 | 29490584 | ths | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, |
2128 | 29490584 | ths | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, |
2129 | 29490584 | ths | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, |
2130 | 29490584 | ths | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, |
2131 | 29490584 | ths | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, |
2132 | 29490584 | ths | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, |
2133 | 29490584 | ths | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, |
2134 | 29490584 | ths | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, |
2135 | 29490584 | ths | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, |
2136 | 29490584 | ths | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
2137 | 29490584 | ths | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, |
2138 | 29490584 | ths | {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2139 | 29490584 | ths | {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2140 | 29490584 | ths | {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2141 | 29490584 | ths | {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2142 | 29490584 | ths | {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2143 | 29490584 | ths | {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2144 | 29490584 | ths | {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2145 | 29490584 | ths | {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2146 | 29490584 | ths | {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2147 | 29490584 | ths | {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2148 | 29490584 | ths | {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2149 | 29490584 | ths | {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2150 | 29490584 | ths | {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2151 | 29490584 | ths | {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2152 | 29490584 | ths | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, |
2153 | 29490584 | ths | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, |
2154 | 29490584 | ths | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, |
2155 | 29490584 | ths | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, |
2156 | 29490584 | ths | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
2157 | 29490584 | ths | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ |
2158 | 29490584 | ths | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
2159 | 29490584 | ths | {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2160 | 29490584 | ths | {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2161 | 29490584 | ths | {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2162 | 29490584 | ths | {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2163 | 29490584 | ths | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2164 | 29490584 | ths | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, |
2165 | 29490584 | ths | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
2166 | 29490584 | ths | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
2167 | 29490584 | ths | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2168 | 29490584 | ths | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, |
2169 | 29490584 | ths | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, |
2170 | 29490584 | ths | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, |
2171 | 29490584 | ths | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, |
2172 | 29490584 | ths | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
2173 | 29490584 | ths | {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
2174 | 29490584 | ths | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
2175 | 29490584 | ths | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ |
2176 | 29490584 | ths | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
2177 | 29490584 | ths | {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2178 | 29490584 | ths | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
2179 | 29490584 | ths | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ |
2180 | 29490584 | ths | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
2181 | 29490584 | ths | {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2182 | 29490584 | ths | {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2183 | 29490584 | ths | {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2184 | 29490584 | ths | {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2185 | 6643d27e | bellard | /* ssnop is at the start of the table. */
|
2186 | 29490584 | ths | {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, |
2187 | 29490584 | ths | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2188 | 29490584 | ths | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, |
2189 | 29490584 | ths | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, |
2190 | 29490584 | ths | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
2191 | 29490584 | ths | {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2192 | 29490584 | ths | {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2193 | 29490584 | ths | {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2194 | 29490584 | ths | {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2195 | 29490584 | ths | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2196 | 29490584 | ths | {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2197 | 29490584 | ths | {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
2198 | 29490584 | ths | {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
2199 | 29490584 | ths | {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
2200 | 29490584 | ths | {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
2201 | 29490584 | ths | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2202 | 29490584 | ths | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, |
2203 | 29490584 | ths | {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, |
2204 | 29490584 | ths | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, |
2205 | 29490584 | ths | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
2206 | 29490584 | ths | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, |
2207 | 29490584 | ths | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, |
2208 | 29490584 | ths | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, |
2209 | 29490584 | ths | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, |
2210 | 29490584 | ths | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, |
2211 | 29490584 | ths | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, |
2212 | 29490584 | ths | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, |
2213 | 29490584 | ths | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ |
2214 | 29490584 | ths | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, |
2215 | 29490584 | ths | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, |
2216 | 29490584 | ths | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, |
2217 | 29490584 | ths | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, |
2218 | 29490584 | ths | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, |
2219 | 29490584 | ths | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
2220 | 29490584 | ths | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, |
2221 | 29490584 | ths | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ |
2222 | 29490584 | ths | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ |
2223 | 29490584 | ths | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
2224 | 29490584 | ths | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, |
2225 | 29490584 | ths | {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ |
2226 | 29490584 | ths | {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ |
2227 | 29490584 | ths | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, |
2228 | 29490584 | ths | {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, |
2229 | 29490584 | ths | {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, |
2230 | 29490584 | ths | {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, |
2231 | 29490584 | ths | {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, |
2232 | 29490584 | ths | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, |
2233 | 29490584 | ths | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, |
2234 | 29490584 | ths | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2235 | 29490584 | ths | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2236 | 29490584 | ths | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2237 | 29490584 | ths | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ |
2238 | 29490584 | ths | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, |
2239 | 29490584 | ths | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2240 | 29490584 | ths | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2241 | 29490584 | ths | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2242 | 29490584 | ths | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ |
2243 | 29490584 | ths | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, |
2244 | 29490584 | ths | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2245 | 29490584 | ths | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2246 | 29490584 | ths | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2247 | 29490584 | ths | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ |
2248 | 29490584 | ths | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, |
2249 | 29490584 | ths | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, |
2250 | 29490584 | ths | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, |
2251 | 29490584 | ths | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, |
2252 | 29490584 | ths | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, |
2253 | 29490584 | ths | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2254 | 29490584 | ths | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2255 | 29490584 | ths | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2256 | 29490584 | ths | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ |
2257 | 29490584 | ths | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, |
2258 | 29490584 | ths | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2259 | 29490584 | ths | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2260 | 29490584 | ths | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2261 | 29490584 | ths | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ |
2262 | 29490584 | ths | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, |
2263 | 29490584 | ths | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
2264 | 29490584 | ths | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
2265 | 29490584 | ths | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
2266 | 29490584 | ths | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ |
2267 | 29490584 | ths | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, |
2268 | 29490584 | ths | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, |
2269 | 29490584 | ths | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, |
2270 | 29490584 | ths | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, |
2271 | 29490584 | ths | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, |
2272 | 29490584 | ths | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, |
2273 | 29490584 | ths | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
2274 | 29490584 | ths | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
2275 | 29490584 | ths | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, |
2276 | 29490584 | ths | {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, |
2277 | 29490584 | ths | {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, |
2278 | 29490584 | ths | {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, |
2279 | 29490584 | ths | {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, |
2280 | 29490584 | ths | {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, |
2281 | 29490584 | ths | {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, |
2282 | 29490584 | ths | {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, |
2283 | 29490584 | ths | {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, |
2284 | 29490584 | ths | {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, |
2285 | 29490584 | ths | {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, |
2286 | 29490584 | ths | {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, |
2287 | 29490584 | ths | {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, |
2288 | 29490584 | ths | {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, |
2289 | 29490584 | ths | {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, |
2290 | 29490584 | ths | {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, |
2291 | 29490584 | ths | {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, |
2292 | 29490584 | ths | {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, |
2293 | 29490584 | ths | {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
2294 | 29490584 | ths | {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, |
2295 | 29490584 | ths | {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
2296 | 29490584 | ths | {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, |
2297 | 29490584 | ths | {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, |
2298 | 29490584 | ths | {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, |
2299 | 29490584 | ths | {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, |
2300 | 29490584 | ths | {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
2301 | 29490584 | ths | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2302 | 29490584 | ths | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, |
2303 | 29490584 | ths | {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
2304 | 29490584 | ths | {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2305 | 29490584 | ths | {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
2306 | 29490584 | ths | {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
2307 | 29490584 | ths | {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
2308 | 29490584 | ths | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
2309 | 29490584 | ths | {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, |
2310 | 29490584 | ths | {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, |
2311 | 29490584 | ths | |
2312 | 29490584 | ths | /* User Defined Instruction. */
|
2313 | 29490584 | ths | {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2314 | 29490584 | ths | {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2315 | 29490584 | ths | {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2316 | 29490584 | ths | {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2317 | 29490584 | ths | {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2318 | 29490584 | ths | {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2319 | 29490584 | ths | {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2320 | 29490584 | ths | {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2321 | 29490584 | ths | {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2322 | 29490584 | ths | {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2323 | 29490584 | ths | {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2324 | 29490584 | ths | {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2325 | 29490584 | ths | {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2326 | 29490584 | ths | {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2327 | 29490584 | ths | {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2328 | 29490584 | ths | {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2329 | 29490584 | ths | {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2330 | 29490584 | ths | {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2331 | 29490584 | ths | {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2332 | 29490584 | ths | {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2333 | 29490584 | ths | {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2334 | 29490584 | ths | {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2335 | 29490584 | ths | {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2336 | 29490584 | ths | {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2337 | 29490584 | ths | {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2338 | 29490584 | ths | {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2339 | 29490584 | ths | {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2340 | 29490584 | ths | {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2341 | 29490584 | ths | {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2342 | 29490584 | ths | {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2343 | 29490584 | ths | {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2344 | 29490584 | ths | {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2345 | 29490584 | ths | {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2346 | 29490584 | ths | {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2347 | 29490584 | ths | {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2348 | 29490584 | ths | {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2349 | 29490584 | ths | {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2350 | 29490584 | ths | {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2351 | 29490584 | ths | {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2352 | 29490584 | ths | {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2353 | 29490584 | ths | {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2354 | 29490584 | ths | {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2355 | 29490584 | ths | {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2356 | 29490584 | ths | {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2357 | 29490584 | ths | {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2358 | 29490584 | ths | {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2359 | 29490584 | ths | {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2360 | 29490584 | ths | {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2361 | 29490584 | ths | {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2362 | 29490584 | ths | {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2363 | 29490584 | ths | {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2364 | 29490584 | ths | {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2365 | 29490584 | ths | {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2366 | 29490584 | ths | {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2367 | 29490584 | ths | {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2368 | 29490584 | ths | {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2369 | 29490584 | ths | {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2370 | 29490584 | ths | {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2371 | 29490584 | ths | {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2372 | 29490584 | ths | {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2373 | 29490584 | ths | {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2374 | 29490584 | ths | {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2375 | 29490584 | ths | {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2376 | 29490584 | ths | {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
2377 | 6643d27e | bellard | |
2378 | 6643d27e | bellard | /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
|
2379 | 6643d27e | bellard | instructions so they are here for the latters to take precedence. */
|
2380 | 29490584 | ths | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2381 | 29490584 | ths | {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, |
2382 | 29490584 | ths | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2383 | 29490584 | ths | {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, |
2384 | 29490584 | ths | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2385 | 29490584 | ths | {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, |
2386 | 29490584 | ths | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2387 | 29490584 | ths | {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, |
2388 | 29490584 | ths | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, |
2389 | 29490584 | ths | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, |
2390 | 29490584 | ths | {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, |
2391 | 29490584 | ths | {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, |
2392 | 29490584 | ths | {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, |
2393 | 29490584 | ths | {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, |
2394 | 29490584 | ths | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, |
2395 | 29490584 | ths | {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, |
2396 | 29490584 | ths | {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, |
2397 | 29490584 | ths | {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, |
2398 | 29490584 | ths | {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, |
2399 | 29490584 | ths | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, |
2400 | 29490584 | ths | {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, |
2401 | 29490584 | ths | {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, |
2402 | 29490584 | ths | {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, |
2403 | 29490584 | ths | {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, |
2404 | 29490584 | ths | |
2405 | 29490584 | ths | /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
|
2406 | 29490584 | ths | instructions, so they are here for the latters to take precedence. */
|
2407 | 29490584 | ths | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2408 | 29490584 | ths | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2409 | 29490584 | ths | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2410 | 29490584 | ths | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2411 | 29490584 | ths | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, |
2412 | 29490584 | ths | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, |
2413 | 29490584 | ths | {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, |
2414 | 29490584 | ths | {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, |
2415 | 29490584 | ths | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, |
2416 | 29490584 | ths | {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, |
2417 | 29490584 | ths | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, |
2418 | 29490584 | ths | {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, |
2419 | 6643d27e | bellard | |
2420 | 6643d27e | bellard | /* No hazard protection on coprocessor instructions--they shouldn't
|
2421 | 6643d27e | bellard | change the state of the processor and if they do it's up to the
|
2422 | 6643d27e | bellard | user to put in nops as necessary. These are at the end so that the
|
2423 | 6643d27e | bellard | disassembler recognizes more specific versions first. */
|
2424 | 29490584 | ths | {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, |
2425 | 29490584 | ths | {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, |
2426 | 29490584 | ths | {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, |
2427 | 29490584 | ths | {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, |
2428 | 29490584 | ths | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, |
2429 | 29490584 | ths | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, |
2430 | 29490584 | ths | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, |
2431 | 29490584 | ths | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, |
2432 | 6643d27e | bellard | /* Conflicts with the 4650's "mul" instruction. Nobody's using the
|
2433 | 6643d27e | bellard | 4010 any more, so move this insn out of the way. If the object
|
2434 | 6643d27e | bellard | format gave us more info, we could do this right. */
|
2435 | 29490584 | ths | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, |
2436 | 29490584 | ths | /* MIPS DSP ASE */
|
2437 | 29490584 | ths | {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2438 | 29490584 | ths | {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2439 | 29490584 | ths | {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2440 | 29490584 | ths | {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2441 | 29490584 | ths | {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2442 | 29490584 | ths | {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2443 | 29490584 | ths | {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2444 | 29490584 | ths | {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2445 | 29490584 | ths | {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2446 | 29490584 | ths | {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2447 | 29490584 | ths | {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2448 | 29490584 | ths | {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2449 | 29490584 | ths | {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2450 | 29490584 | ths | {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2451 | 29490584 | ths | {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2452 | 29490584 | ths | {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2453 | 29490584 | ths | {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2454 | 29490584 | ths | {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2455 | 29490584 | ths | {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, |
2456 | 29490584 | ths | {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, |
2457 | 29490584 | ths | {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2458 | 29490584 | ths | {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2459 | 29490584 | ths | {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2460 | 29490584 | ths | {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2461 | 29490584 | ths | {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2462 | 29490584 | ths | {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2463 | 29490584 | ths | {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2464 | 29490584 | ths | {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2465 | 29490584 | ths | {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2466 | 29490584 | ths | {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2467 | 29490584 | ths | {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2468 | 29490584 | ths | {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2469 | 29490584 | ths | {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2470 | 29490584 | ths | {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2471 | 29490584 | ths | {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2472 | 29490584 | ths | {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2473 | 29490584 | ths | {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2474 | 29490584 | ths | {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2475 | 29490584 | ths | {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2476 | 29490584 | ths | {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
2477 | 29490584 | ths | {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
2478 | 29490584 | ths | {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, |
2479 | 29490584 | ths | {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, |
2480 | 29490584 | ths | {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2481 | 29490584 | ths | {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2482 | 29490584 | ths | {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2483 | 29490584 | ths | {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2484 | 29490584 | ths | {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2485 | 29490584 | ths | {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2486 | 29490584 | ths | {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2487 | 29490584 | ths | {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2488 | 29490584 | ths | {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2489 | 29490584 | ths | {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2490 | 29490584 | ths | {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2491 | 29490584 | ths | {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2492 | 29490584 | ths | {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2493 | 29490584 | ths | {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2494 | 29490584 | ths | {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
2495 | 29490584 | ths | {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
2496 | 29490584 | ths | {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, |
2497 | 29490584 | ths | {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2498 | 29490584 | ths | {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2499 | 29490584 | ths | {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2500 | 29490584 | ths | {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2501 | 29490584 | ths | {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, |
2502 | 29490584 | ths | {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2503 | 29490584 | ths | {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2504 | 29490584 | ths | {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2505 | 29490584 | ths | {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2506 | 29490584 | ths | {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2507 | 29490584 | ths | {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2508 | 29490584 | ths | {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2509 | 29490584 | ths | {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2510 | 29490584 | ths | {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2511 | 29490584 | ths | {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2512 | 29490584 | ths | {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2513 | 29490584 | ths | {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2514 | 29490584 | ths | {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2515 | 29490584 | ths | {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2516 | 29490584 | ths | {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2517 | 29490584 | ths | {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2518 | 29490584 | ths | {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, |
2519 | 29490584 | ths | {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, |
2520 | 29490584 | ths | {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, |
2521 | 29490584 | ths | {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, |
2522 | 29490584 | ths | {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
2523 | 29490584 | ths | {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
2524 | 29490584 | ths | {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
2525 | 29490584 | ths | {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
2526 | 29490584 | ths | {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
2527 | 29490584 | ths | {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
2528 | 29490584 | ths | {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
2529 | 29490584 | ths | {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
2530 | 29490584 | ths | {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
2531 | 29490584 | ths | {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
2532 | 29490584 | ths | {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, |
2533 | 29490584 | ths | {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, |
2534 | 29490584 | ths | {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, |
2535 | 29490584 | ths | {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, |
2536 | 29490584 | ths | {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, |
2537 | 29490584 | ths | {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2538 | 29490584 | ths | {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2539 | 29490584 | ths | {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2540 | 29490584 | ths | {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2541 | 29490584 | ths | {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2542 | 29490584 | ths | {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2543 | 29490584 | ths | {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2544 | 29490584 | ths | {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2545 | 29490584 | ths | {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2546 | 29490584 | ths | {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2547 | 29490584 | ths | {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2548 | 29490584 | ths | {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2549 | 29490584 | ths | {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2550 | 29490584 | ths | {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2551 | 29490584 | ths | {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2552 | 29490584 | ths | {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, |
2553 | 29490584 | ths | {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
2554 | 29490584 | ths | {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
2555 | 29490584 | ths | {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
2556 | 29490584 | ths | {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
2557 | 29490584 | ths | {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
2558 | 29490584 | ths | {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
2559 | 29490584 | ths | {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
2560 | 29490584 | ths | {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
2561 | 29490584 | ths | {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
2562 | 29490584 | ths | {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
2563 | 29490584 | ths | {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2564 | 29490584 | ths | {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
2565 | 29490584 | ths | {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
2566 | 29490584 | ths | {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2567 | 29490584 | ths | {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2568 | 29490584 | ths | {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2569 | 29490584 | ths | {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2570 | 29490584 | ths | {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2571 | 29490584 | ths | {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2572 | 29490584 | ths | {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2573 | 29490584 | ths | {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2574 | 29490584 | ths | {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2575 | 29490584 | ths | {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2576 | 29490584 | ths | {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2577 | 29490584 | ths | {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2578 | 29490584 | ths | {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2579 | 29490584 | ths | {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2580 | 29490584 | ths | {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2581 | 29490584 | ths | {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2582 | 29490584 | ths | {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2583 | 29490584 | ths | {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2584 | 29490584 | ths | {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2585 | 29490584 | ths | {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2586 | 29490584 | ths | {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2587 | 29490584 | ths | {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2588 | 29490584 | ths | {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2589 | 29490584 | ths | {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2590 | 29490584 | ths | {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2591 | 29490584 | ths | {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2592 | 29490584 | ths | {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2593 | 29490584 | ths | {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2594 | 29490584 | ths | {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2595 | 29490584 | ths | {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2596 | 29490584 | ths | {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2597 | 29490584 | ths | {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2598 | 29490584 | ths | {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2599 | 29490584 | ths | {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2600 | 29490584 | ths | {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2601 | 29490584 | ths | {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2602 | 29490584 | ths | {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2603 | 29490584 | ths | {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2604 | 29490584 | ths | {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2605 | 29490584 | ths | {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2606 | 29490584 | ths | {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, |
2607 | 29490584 | ths | {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, |
2608 | 29490584 | ths | {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, |
2609 | 29490584 | ths | {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, |
2610 | 29490584 | ths | {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, |
2611 | 29490584 | ths | {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, |
2612 | 29490584 | ths | {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, |
2613 | 29490584 | ths | {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, |
2614 | 29490584 | ths | {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, |
2615 | 29490584 | ths | {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2616 | 29490584 | ths | {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2617 | 29490584 | ths | {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2618 | 29490584 | ths | {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
2619 | 29490584 | ths | {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
2620 | 29490584 | ths | {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, |
2621 | 29490584 | ths | {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, |
2622 | 29490584 | ths | {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, |
2623 | 29490584 | ths | {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
2624 | 29490584 | ths | {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
2625 | 29490584 | ths | {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, |
2626 | 29490584 | ths | {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
2627 | 29490584 | ths | {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
2628 | 29490584 | ths | {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
2629 | 29490584 | ths | {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
2630 | 29490584 | ths | {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, |
2631 | 29490584 | ths | {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2632 | 29490584 | ths | {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2633 | 29490584 | ths | {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2634 | 29490584 | ths | {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2635 | 29490584 | ths | {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2636 | 29490584 | ths | {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2637 | 29490584 | ths | {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2638 | 29490584 | ths | {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2639 | 29490584 | ths | {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2640 | 29490584 | ths | {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
2641 | 29490584 | ths | {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
2642 | 29490584 | ths | {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
2643 | 29490584 | ths | {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
2644 | 29490584 | ths | {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
2645 | 29490584 | ths | {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
2646 | 29490584 | ths | {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, |
2647 | 29490584 | ths | {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2648 | 29490584 | ths | {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2649 | 29490584 | ths | {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2650 | 29490584 | ths | {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2651 | 29490584 | ths | {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2652 | 29490584 | ths | {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2653 | 29490584 | ths | {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2654 | 29490584 | ths | {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, |
2655 | 29490584 | ths | {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, |
2656 | 29490584 | ths | {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2657 | 29490584 | ths | {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2658 | 29490584 | ths | {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2659 | 29490584 | ths | {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2660 | 29490584 | ths | {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2661 | 29490584 | ths | {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2662 | 29490584 | ths | {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2663 | 29490584 | ths | {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2664 | 29490584 | ths | {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2665 | 29490584 | ths | {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2666 | 29490584 | ths | {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2667 | 29490584 | ths | {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
2668 | 29490584 | ths | {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
2669 | 29490584 | ths | {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, |
2670 | 29490584 | ths | {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, |
2671 | 29490584 | ths | /* MIPS DSP ASE Rev2 */
|
2672 | 29490584 | ths | {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, |
2673 | 29490584 | ths | {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2674 | 29490584 | ths | {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2675 | 29490584 | ths | {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2676 | 29490584 | ths | {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2677 | 29490584 | ths | {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
2678 | 29490584 | ths | {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, |
2679 | 29490584 | ths | {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, |
2680 | 29490584 | ths | {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2681 | 29490584 | ths | {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2682 | 29490584 | ths | {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2683 | 29490584 | ths | {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2684 | 29490584 | ths | {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2685 | 29490584 | ths | {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
2686 | 29490584 | ths | {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
2687 | 29490584 | ths | {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
2688 | 29490584 | ths | {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
2689 | 29490584 | ths | {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
2690 | 29490584 | ths | {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2691 | 29490584 | ths | {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2692 | 29490584 | ths | {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
2693 | 29490584 | ths | {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
2694 | 29490584 | ths | {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
2695 | 29490584 | ths | {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, |
2696 | 29490584 | ths | {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, |
2697 | 29490584 | ths | {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2698 | 29490584 | ths | {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2699 | 29490584 | ths | {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, |
2700 | 29490584 | ths | {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2701 | 29490584 | ths | {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2702 | 29490584 | ths | {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2703 | 29490584 | ths | {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2704 | 29490584 | ths | {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2705 | 29490584 | ths | {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2706 | 29490584 | ths | {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2707 | 29490584 | ths | {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2708 | 29490584 | ths | {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2709 | 29490584 | ths | {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2710 | 29490584 | ths | {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2711 | 29490584 | ths | {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2712 | 29490584 | ths | {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
2713 | 29490584 | ths | {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2714 | 29490584 | ths | {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2715 | 29490584 | ths | {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2716 | 29490584 | ths | {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2717 | 29490584 | ths | {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2718 | 29490584 | ths | {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
2719 | 29490584 | ths | /* Move bc0* after mftr and mttr to avoid opcode collision. */
|
2720 | 29490584 | ths | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2721 | 29490584 | ths | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2722 | 29490584 | ths | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2723 | 29490584 | ths | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, |
2724 | 6643d27e | bellard | }; |
2725 | 6643d27e | bellard | |
2726 | 6643d27e | bellard | #define MIPS_NUM_OPCODES \
|
2727 | 6643d27e | bellard | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) |
2728 | 6643d27e | bellard | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; |
2729 | 6643d27e | bellard | |
2730 | 6643d27e | bellard | /* const removed from the following to allow for dynamic extensions to the
|
2731 | 6643d27e | bellard | * built-in instruction set. */
|
2732 | 6643d27e | bellard | struct mips_opcode *mips_opcodes =
|
2733 | 6643d27e | bellard | (struct mips_opcode *) mips_builtin_opcodes;
|
2734 | 6643d27e | bellard | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
|
2735 | 6643d27e | bellard | #undef MIPS_NUM_OPCODES
|
2736 | 6643d27e | bellard | |
2737 | 6643d27e | bellard | /* Mips instructions are at maximum this many bytes long. */
|
2738 | 6643d27e | bellard | #define INSNLEN 4 |
2739 | 6643d27e | bellard | |
2740 | 6643d27e | bellard | |
2741 | 6643d27e | bellard | /* FIXME: These should be shared with gdb somehow. */
|
2742 | 6643d27e | bellard | |
2743 | 52da07d1 | ths | struct mips_cp0sel_name
|
2744 | 52da07d1 | ths | { |
2745 | 52da07d1 | ths | unsigned int cp0reg; |
2746 | 52da07d1 | ths | unsigned int sel; |
2747 | 52da07d1 | ths | const char * const name; |
2748 | 6643d27e | bellard | }; |
2749 | 6643d27e | bellard | |
2750 | 52da07d1 | ths | /* The mips16 registers. */
|
2751 | 52da07d1 | ths | static const unsigned int mips16_to_32_reg_map[] = |
2752 | 52da07d1 | ths | { |
2753 | 52da07d1 | ths | 16, 17, 2, 3, 4, 5, 6, 7 |
2754 | 6643d27e | bellard | }; |
2755 | 6643d27e | bellard | |
2756 | 52da07d1 | ths | #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
|
2757 | 52da07d1 | ths | |
2758 | 52da07d1 | ths | |
2759 | 52da07d1 | ths | static const char * const mips_gpr_names_numeric[32] = |
2760 | 52da07d1 | ths | { |
2761 | 6643d27e | bellard | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
2762 | 6643d27e | bellard | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
2763 | 6643d27e | bellard | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
2764 | 6643d27e | bellard | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
2765 | 6643d27e | bellard | }; |
2766 | 6643d27e | bellard | |
2767 | 52da07d1 | ths | static const char * const mips_gpr_names_oldabi[32] = |
2768 | 52da07d1 | ths | { |
2769 | 6643d27e | bellard | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
2770 | 6643d27e | bellard | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
2771 | 6643d27e | bellard | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
2772 | 6643d27e | bellard | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
2773 | 6643d27e | bellard | }; |
2774 | 6643d27e | bellard | |
2775 | 52da07d1 | ths | static const char * const mips_gpr_names_newabi[32] = |
2776 | 52da07d1 | ths | { |
2777 | 6643d27e | bellard | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
2778 | 6643d27e | bellard | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
2779 | 6643d27e | bellard | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
2780 | 6643d27e | bellard | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
2781 | 6643d27e | bellard | }; |
2782 | 6643d27e | bellard | |
2783 | 52da07d1 | ths | static const char * const mips_fpr_names_numeric[32] = |
2784 | 52da07d1 | ths | { |
2785 | 6643d27e | bellard | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
2786 | 6643d27e | bellard | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", |
2787 | 6643d27e | bellard | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", |
2788 | 6643d27e | bellard | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" |
2789 | 6643d27e | bellard | }; |
2790 | 6643d27e | bellard | |
2791 | 52da07d1 | ths | static const char * const mips_fpr_names_32[32] = |
2792 | 52da07d1 | ths | { |
2793 | 6643d27e | bellard | "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", |
2794 | 6643d27e | bellard | "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", |
2795 | 6643d27e | bellard | "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", |
2796 | 6643d27e | bellard | "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" |
2797 | 6643d27e | bellard | }; |
2798 | 6643d27e | bellard | |
2799 | 52da07d1 | ths | static const char * const mips_fpr_names_n32[32] = |
2800 | 52da07d1 | ths | { |
2801 | 6643d27e | bellard | "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", |
2802 | 6643d27e | bellard | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", |
2803 | 6643d27e | bellard | "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", |
2804 | 6643d27e | bellard | "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" |
2805 | 6643d27e | bellard | }; |
2806 | 6643d27e | bellard | |
2807 | 52da07d1 | ths | static const char * const mips_fpr_names_64[32] = |
2808 | 52da07d1 | ths | { |
2809 | 6643d27e | bellard | "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", |
2810 | 6643d27e | bellard | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", |
2811 | 6643d27e | bellard | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", |
2812 | 6643d27e | bellard | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" |
2813 | 6643d27e | bellard | }; |
2814 | 6643d27e | bellard | |
2815 | 52da07d1 | ths | static const char * const mips_cp0_names_numeric[32] = |
2816 | 52da07d1 | ths | { |
2817 | 6643d27e | bellard | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
2818 | 6643d27e | bellard | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
2819 | 6643d27e | bellard | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
2820 | 6643d27e | bellard | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
2821 | 6643d27e | bellard | }; |
2822 | 6643d27e | bellard | |
2823 | 52da07d1 | ths | static const char * const mips_cp0_names_mips3264[32] = |
2824 | 52da07d1 | ths | { |
2825 | 6643d27e | bellard | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
2826 | 6643d27e | bellard | "c0_context", "c0_pagemask", "c0_wired", "$7", |
2827 | 6643d27e | bellard | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
2828 | 6643d27e | bellard | "c0_status", "c0_cause", "c0_epc", "c0_prid", |
2829 | 6643d27e | bellard | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
2830 | 6643d27e | bellard | "c0_xcontext", "$21", "$22", "c0_debug", |
2831 | 6643d27e | bellard | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", |
2832 | 6643d27e | bellard | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", |
2833 | 6643d27e | bellard | }; |
2834 | 6643d27e | bellard | |
2835 | 52da07d1 | ths | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = |
2836 | 52da07d1 | ths | { |
2837 | 52da07d1 | ths | { 4, 1, "c0_contextconfig" }, |
2838 | 52da07d1 | ths | { 0, 1, "c0_mvpcontrol" }, |
2839 | 52da07d1 | ths | { 0, 2, "c0_mvpconf0" }, |
2840 | 52da07d1 | ths | { 0, 3, "c0_mvpconf1" }, |
2841 | 52da07d1 | ths | { 1, 1, "c0_vpecontrol" }, |
2842 | 52da07d1 | ths | { 1, 2, "c0_vpeconf0" }, |
2843 | 52da07d1 | ths | { 1, 3, "c0_vpeconf1" }, |
2844 | 52da07d1 | ths | { 1, 4, "c0_yqmask" }, |
2845 | 52da07d1 | ths | { 1, 5, "c0_vpeschedule" }, |
2846 | 52da07d1 | ths | { 1, 6, "c0_vpeschefback" }, |
2847 | 52da07d1 | ths | { 2, 1, "c0_tcstatus" }, |
2848 | 52da07d1 | ths | { 2, 2, "c0_tcbind" }, |
2849 | 52da07d1 | ths | { 2, 3, "c0_tcrestart" }, |
2850 | 52da07d1 | ths | { 2, 4, "c0_tchalt" }, |
2851 | 52da07d1 | ths | { 2, 5, "c0_tccontext" }, |
2852 | 52da07d1 | ths | { 2, 6, "c0_tcschedule" }, |
2853 | 52da07d1 | ths | { 2, 7, "c0_tcschefback" }, |
2854 | 52da07d1 | ths | { 5, 1, "c0_pagegrain" }, |
2855 | 52da07d1 | ths | { 6, 1, "c0_srsconf0" }, |
2856 | 52da07d1 | ths | { 6, 2, "c0_srsconf1" }, |
2857 | 52da07d1 | ths | { 6, 3, "c0_srsconf2" }, |
2858 | 52da07d1 | ths | { 6, 4, "c0_srsconf3" }, |
2859 | 52da07d1 | ths | { 6, 5, "c0_srsconf4" }, |
2860 | 52da07d1 | ths | { 12, 1, "c0_intctl" }, |
2861 | 52da07d1 | ths | { 12, 2, "c0_srsctl" }, |
2862 | 52da07d1 | ths | { 12, 3, "c0_srsmap" }, |
2863 | 52da07d1 | ths | { 15, 1, "c0_ebase" }, |
2864 | 6643d27e | bellard | { 16, 1, "c0_config1" }, |
2865 | 6643d27e | bellard | { 16, 2, "c0_config2" }, |
2866 | 6643d27e | bellard | { 16, 3, "c0_config3" }, |
2867 | 6643d27e | bellard | { 18, 1, "c0_watchlo,1" }, |
2868 | 6643d27e | bellard | { 18, 2, "c0_watchlo,2" }, |
2869 | 6643d27e | bellard | { 18, 3, "c0_watchlo,3" }, |
2870 | 6643d27e | bellard | { 18, 4, "c0_watchlo,4" }, |
2871 | 6643d27e | bellard | { 18, 5, "c0_watchlo,5" }, |
2872 | 6643d27e | bellard | { 18, 6, "c0_watchlo,6" }, |
2873 | 6643d27e | bellard | { 18, 7, "c0_watchlo,7" }, |
2874 | 6643d27e | bellard | { 19, 1, "c0_watchhi,1" }, |
2875 | 6643d27e | bellard | { 19, 2, "c0_watchhi,2" }, |
2876 | 6643d27e | bellard | { 19, 3, "c0_watchhi,3" }, |
2877 | 6643d27e | bellard | { 19, 4, "c0_watchhi,4" }, |
2878 | 6643d27e | bellard | { 19, 5, "c0_watchhi,5" }, |
2879 | 6643d27e | bellard | { 19, 6, "c0_watchhi,6" }, |
2880 | 6643d27e | bellard | { 19, 7, "c0_watchhi,7" }, |
2881 | 52da07d1 | ths | { 23, 1, "c0_tracecontrol" }, |
2882 | 52da07d1 | ths | { 23, 2, "c0_tracecontrol2" }, |
2883 | 52da07d1 | ths | { 23, 3, "c0_usertracedata" }, |
2884 | 52da07d1 | ths | { 23, 4, "c0_tracebpc" }, |
2885 | 6643d27e | bellard | { 25, 1, "c0_perfcnt,1" }, |
2886 | 6643d27e | bellard | { 25, 2, "c0_perfcnt,2" }, |
2887 | 6643d27e | bellard | { 25, 3, "c0_perfcnt,3" }, |
2888 | 6643d27e | bellard | { 25, 4, "c0_perfcnt,4" }, |
2889 | 6643d27e | bellard | { 25, 5, "c0_perfcnt,5" }, |
2890 | 6643d27e | bellard | { 25, 6, "c0_perfcnt,6" }, |
2891 | 6643d27e | bellard | { 25, 7, "c0_perfcnt,7" }, |
2892 | 6643d27e | bellard | { 27, 1, "c0_cacheerr,1" }, |
2893 | 6643d27e | bellard | { 27, 2, "c0_cacheerr,2" }, |
2894 | 6643d27e | bellard | { 27, 3, "c0_cacheerr,3" }, |
2895 | 6643d27e | bellard | { 28, 1, "c0_datalo" }, |
2896 | 52da07d1 | ths | { 28, 2, "c0_taglo1" }, |
2897 | 52da07d1 | ths | { 28, 3, "c0_datalo1" }, |
2898 | 52da07d1 | ths | { 28, 4, "c0_taglo2" }, |
2899 | 52da07d1 | ths | { 28, 5, "c0_datalo2" }, |
2900 | 52da07d1 | ths | { 28, 6, "c0_taglo3" }, |
2901 | 52da07d1 | ths | { 28, 7, "c0_datalo3" }, |
2902 | 52da07d1 | ths | { 29, 1, "c0_datahi" }, |
2903 | 52da07d1 | ths | { 29, 2, "c0_taghi1" }, |
2904 | 52da07d1 | ths | { 29, 3, "c0_datahi1" }, |
2905 | 52da07d1 | ths | { 29, 4, "c0_taghi2" }, |
2906 | 52da07d1 | ths | { 29, 5, "c0_datahi2" }, |
2907 | 52da07d1 | ths | { 29, 6, "c0_taghi3" }, |
2908 | 52da07d1 | ths | { 29, 7, "c0_datahi3" }, |
2909 | 6643d27e | bellard | }; |
2910 | 6643d27e | bellard | |
2911 | 52da07d1 | ths | static const char * const mips_cp0_names_mips3264r2[32] = |
2912 | 52da07d1 | ths | { |
2913 | 6643d27e | bellard | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
2914 | 6643d27e | bellard | "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", |
2915 | 6643d27e | bellard | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
2916 | 6643d27e | bellard | "c0_status", "c0_cause", "c0_epc", "c0_prid", |
2917 | 6643d27e | bellard | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
2918 | 6643d27e | bellard | "c0_xcontext", "$21", "$22", "c0_debug", |
2919 | 6643d27e | bellard | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", |
2920 | 6643d27e | bellard | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", |
2921 | 6643d27e | bellard | }; |
2922 | 6643d27e | bellard | |
2923 | 52da07d1 | ths | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = |
2924 | 52da07d1 | ths | { |
2925 | 6643d27e | bellard | { 4, 1, "c0_contextconfig" }, |
2926 | 6643d27e | bellard | { 5, 1, "c0_pagegrain" }, |
2927 | 6643d27e | bellard | { 12, 1, "c0_intctl" }, |
2928 | 6643d27e | bellard | { 12, 2, "c0_srsctl" }, |
2929 | 6643d27e | bellard | { 12, 3, "c0_srsmap" }, |
2930 | 6643d27e | bellard | { 15, 1, "c0_ebase" }, |
2931 | 6643d27e | bellard | { 16, 1, "c0_config1" }, |
2932 | 6643d27e | bellard | { 16, 2, "c0_config2" }, |
2933 | 6643d27e | bellard | { 16, 3, "c0_config3" }, |
2934 | 6643d27e | bellard | { 18, 1, "c0_watchlo,1" }, |
2935 | 6643d27e | bellard | { 18, 2, "c0_watchlo,2" }, |
2936 | 6643d27e | bellard | { 18, 3, "c0_watchlo,3" }, |
2937 | 6643d27e | bellard | { 18, 4, "c0_watchlo,4" }, |
2938 | 6643d27e | bellard | { 18, 5, "c0_watchlo,5" }, |
2939 | 6643d27e | bellard | { 18, 6, "c0_watchlo,6" }, |
2940 | 6643d27e | bellard | { 18, 7, "c0_watchlo,7" }, |
2941 | 6643d27e | bellard | { 19, 1, "c0_watchhi,1" }, |
2942 | 6643d27e | bellard | { 19, 2, "c0_watchhi,2" }, |
2943 | 6643d27e | bellard | { 19, 3, "c0_watchhi,3" }, |
2944 | 6643d27e | bellard | { 19, 4, "c0_watchhi,4" }, |
2945 | 6643d27e | bellard | { 19, 5, "c0_watchhi,5" }, |
2946 | 6643d27e | bellard | { 19, 6, "c0_watchhi,6" }, |
2947 | 6643d27e | bellard | { 19, 7, "c0_watchhi,7" }, |
2948 | 6643d27e | bellard | { 23, 1, "c0_tracecontrol" }, |
2949 | 6643d27e | bellard | { 23, 2, "c0_tracecontrol2" }, |
2950 | 6643d27e | bellard | { 23, 3, "c0_usertracedata" }, |
2951 | 6643d27e | bellard | { 23, 4, "c0_tracebpc" }, |
2952 | 6643d27e | bellard | { 25, 1, "c0_perfcnt,1" }, |
2953 | 6643d27e | bellard | { 25, 2, "c0_perfcnt,2" }, |
2954 | 6643d27e | bellard | { 25, 3, "c0_perfcnt,3" }, |
2955 | 6643d27e | bellard | { 25, 4, "c0_perfcnt,4" }, |
2956 | 6643d27e | bellard | { 25, 5, "c0_perfcnt,5" }, |
2957 | 6643d27e | bellard | { 25, 6, "c0_perfcnt,6" }, |
2958 | 6643d27e | bellard | { 25, 7, "c0_perfcnt,7" }, |
2959 | 6643d27e | bellard | { 27, 1, "c0_cacheerr,1" }, |
2960 | 6643d27e | bellard | { 27, 2, "c0_cacheerr,2" }, |
2961 | 6643d27e | bellard | { 27, 3, "c0_cacheerr,3" }, |
2962 | 6643d27e | bellard | { 28, 1, "c0_datalo" }, |
2963 | 6643d27e | bellard | { 28, 2, "c0_taglo1" }, |
2964 | 6643d27e | bellard | { 28, 3, "c0_datalo1" }, |
2965 | 6643d27e | bellard | { 28, 4, "c0_taglo2" }, |
2966 | 6643d27e | bellard | { 28, 5, "c0_datalo2" }, |
2967 | 6643d27e | bellard | { 28, 6, "c0_taglo3" }, |
2968 | 6643d27e | bellard | { 28, 7, "c0_datalo3" }, |
2969 | 6643d27e | bellard | { 29, 1, "c0_datahi" }, |
2970 | 6643d27e | bellard | { 29, 2, "c0_taghi1" }, |
2971 | 6643d27e | bellard | { 29, 3, "c0_datahi1" }, |
2972 | 6643d27e | bellard | { 29, 4, "c0_taghi2" }, |
2973 | 6643d27e | bellard | { 29, 5, "c0_datahi2" }, |
2974 | 6643d27e | bellard | { 29, 6, "c0_taghi3" }, |
2975 | 6643d27e | bellard | { 29, 7, "c0_datahi3" }, |
2976 | 6643d27e | bellard | }; |
2977 | 6643d27e | bellard | |
2978 | 6643d27e | bellard | /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
|
2979 | 52da07d1 | ths | static const char * const mips_cp0_names_sb1[32] = |
2980 | 52da07d1 | ths | { |
2981 | 6643d27e | bellard | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
2982 | 6643d27e | bellard | "c0_context", "c0_pagemask", "c0_wired", "$7", |
2983 | 6643d27e | bellard | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
2984 | 6643d27e | bellard | "c0_status", "c0_cause", "c0_epc", "c0_prid", |
2985 | 6643d27e | bellard | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
2986 | 6643d27e | bellard | "c0_xcontext", "$21", "$22", "c0_debug", |
2987 | 6643d27e | bellard | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", |
2988 | 6643d27e | bellard | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", |
2989 | 6643d27e | bellard | }; |
2990 | 6643d27e | bellard | |
2991 | 52da07d1 | ths | static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = |
2992 | 52da07d1 | ths | { |
2993 | 6643d27e | bellard | { 16, 1, "c0_config1" }, |
2994 | 6643d27e | bellard | { 18, 1, "c0_watchlo,1" }, |
2995 | 6643d27e | bellard | { 19, 1, "c0_watchhi,1" }, |
2996 | 6643d27e | bellard | { 22, 0, "c0_perftrace" }, |
2997 | 6643d27e | bellard | { 23, 3, "c0_edebug" }, |
2998 | 6643d27e | bellard | { 25, 1, "c0_perfcnt,1" }, |
2999 | 6643d27e | bellard | { 25, 2, "c0_perfcnt,2" }, |
3000 | 6643d27e | bellard | { 25, 3, "c0_perfcnt,3" }, |
3001 | 6643d27e | bellard | { 25, 4, "c0_perfcnt,4" }, |
3002 | 6643d27e | bellard | { 25, 5, "c0_perfcnt,5" }, |
3003 | 6643d27e | bellard | { 25, 6, "c0_perfcnt,6" }, |
3004 | 6643d27e | bellard | { 25, 7, "c0_perfcnt,7" }, |
3005 | 6643d27e | bellard | { 26, 1, "c0_buserr_pa" }, |
3006 | 6643d27e | bellard | { 27, 1, "c0_cacheerr_d" }, |
3007 | 6643d27e | bellard | { 27, 3, "c0_cacheerr_d_pa" }, |
3008 | 6643d27e | bellard | { 28, 1, "c0_datalo_i" }, |
3009 | 6643d27e | bellard | { 28, 2, "c0_taglo_d" }, |
3010 | 6643d27e | bellard | { 28, 3, "c0_datalo_d" }, |
3011 | 6643d27e | bellard | { 29, 1, "c0_datahi_i" }, |
3012 | 6643d27e | bellard | { 29, 2, "c0_taghi_d" }, |
3013 | 6643d27e | bellard | { 29, 3, "c0_datahi_d" }, |
3014 | 6643d27e | bellard | }; |
3015 | 6643d27e | bellard | |
3016 | 52da07d1 | ths | static const char * const mips_hwr_names_numeric[32] = |
3017 | 52da07d1 | ths | { |
3018 | 6643d27e | bellard | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
3019 | 6643d27e | bellard | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
3020 | 6643d27e | bellard | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
3021 | 6643d27e | bellard | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
3022 | 6643d27e | bellard | }; |
3023 | 6643d27e | bellard | |
3024 | 52da07d1 | ths | static const char * const mips_hwr_names_mips3264r2[32] = |
3025 | 52da07d1 | ths | { |
3026 | 6643d27e | bellard | "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", |
3027 | 6643d27e | bellard | "$4", "$5", "$6", "$7", |
3028 | 6643d27e | bellard | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
3029 | 6643d27e | bellard | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
3030 | 6643d27e | bellard | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
3031 | 6643d27e | bellard | }; |
3032 | 6643d27e | bellard | |
3033 | 52da07d1 | ths | struct mips_abi_choice
|
3034 | 52da07d1 | ths | { |
3035 | 6643d27e | bellard | const char *name; |
3036 | 6643d27e | bellard | const char * const *gpr_names; |
3037 | 6643d27e | bellard | const char * const *fpr_names; |
3038 | 6643d27e | bellard | }; |
3039 | 6643d27e | bellard | |
3040 | 52da07d1 | ths | struct mips_abi_choice mips_abi_choices[] =
|
3041 | 52da07d1 | ths | { |
3042 | 6643d27e | bellard | { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
|
3043 | 6643d27e | bellard | { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
|
3044 | 6643d27e | bellard | { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
|
3045 | 6643d27e | bellard | { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
|
3046 | 6643d27e | bellard | }; |
3047 | 6643d27e | bellard | |
3048 | 52da07d1 | ths | struct mips_arch_choice
|
3049 | 52da07d1 | ths | { |
3050 | 6643d27e | bellard | const char *name; |
3051 | 6643d27e | bellard | int bfd_mach_valid;
|
3052 | 6643d27e | bellard | unsigned long bfd_mach; |
3053 | 6643d27e | bellard | int processor;
|
3054 | 6643d27e | bellard | int isa;
|
3055 | 6643d27e | bellard | const char * const *cp0_names; |
3056 | 6643d27e | bellard | const struct mips_cp0sel_name *cp0sel_names; |
3057 | 6643d27e | bellard | unsigned int cp0sel_names_len; |
3058 | 6643d27e | bellard | const char * const *hwr_names; |
3059 | 6643d27e | bellard | }; |
3060 | 6643d27e | bellard | |
3061 | 6643d27e | bellard | #define bfd_mach_mips3000 3000 |
3062 | 6643d27e | bellard | #define bfd_mach_mips3900 3900 |
3063 | 6643d27e | bellard | #define bfd_mach_mips4000 4000 |
3064 | 6643d27e | bellard | #define bfd_mach_mips4010 4010 |
3065 | 6643d27e | bellard | #define bfd_mach_mips4100 4100 |
3066 | 6643d27e | bellard | #define bfd_mach_mips4111 4111 |
3067 | 6643d27e | bellard | #define bfd_mach_mips4120 4120 |
3068 | 6643d27e | bellard | #define bfd_mach_mips4300 4300 |
3069 | 6643d27e | bellard | #define bfd_mach_mips4400 4400 |
3070 | 6643d27e | bellard | #define bfd_mach_mips4600 4600 |
3071 | 6643d27e | bellard | #define bfd_mach_mips4650 4650 |
3072 | 6643d27e | bellard | #define bfd_mach_mips5000 5000 |
3073 | 6643d27e | bellard | #define bfd_mach_mips5400 5400 |
3074 | 6643d27e | bellard | #define bfd_mach_mips5500 5500 |
3075 | 6643d27e | bellard | #define bfd_mach_mips6000 6000 |
3076 | 6643d27e | bellard | #define bfd_mach_mips7000 7000 |
3077 | 6643d27e | bellard | #define bfd_mach_mips8000 8000 |
3078 | 52da07d1 | ths | #define bfd_mach_mips9000 9000 |
3079 | 6643d27e | bellard | #define bfd_mach_mips10000 10000 |
3080 | 6643d27e | bellard | #define bfd_mach_mips12000 12000 |
3081 | 6643d27e | bellard | #define bfd_mach_mips16 16 |
3082 | 6643d27e | bellard | #define bfd_mach_mips5 5 |
3083 | 6643d27e | bellard | #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ |
3084 | 6643d27e | bellard | #define bfd_mach_mipsisa32 32 |
3085 | 6643d27e | bellard | #define bfd_mach_mipsisa32r2 33 |
3086 | 6643d27e | bellard | #define bfd_mach_mipsisa64 64 |
3087 | 6643d27e | bellard | #define bfd_mach_mipsisa64r2 65 |
3088 | 6643d27e | bellard | |
3089 | 6643d27e | bellard | #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) |
3090 | 6643d27e | bellard | |
3091 | 52da07d1 | ths | const struct mips_arch_choice mips_arch_choices[] = |
3092 | 52da07d1 | ths | { |
3093 | 6643d27e | bellard | { "numeric", 0, 0, 0, 0, |
3094 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3095 | 6643d27e | bellard | |
3096 | 6643d27e | bellard | { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, |
3097 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3098 | 6643d27e | bellard | { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, |
3099 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3100 | 6643d27e | bellard | { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, |
3101 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3102 | 6643d27e | bellard | { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, |
3103 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3104 | 6643d27e | bellard | { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, |
3105 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3106 | 6643d27e | bellard | { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, |
3107 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3108 | 6643d27e | bellard | { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, |
3109 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3110 | 6643d27e | bellard | { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, |
3111 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3112 | 6643d27e | bellard | { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, |
3113 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3114 | 6643d27e | bellard | { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, |
3115 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3116 | 6643d27e | bellard | { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, |
3117 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3118 | 6643d27e | bellard | { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, |
3119 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3120 | 6643d27e | bellard | { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, |
3121 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3122 | 6643d27e | bellard | { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, |
3123 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3124 | 6643d27e | bellard | { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, |
3125 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3126 | 6643d27e | bellard | { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, |
3127 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3128 | 6643d27e | bellard | { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, |
3129 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3130 | 6643d27e | bellard | { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, |
3131 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3132 | 6643d27e | bellard | { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, |
3133 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3134 | 6643d27e | bellard | { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, |
3135 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3136 | 6643d27e | bellard | { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, |
3137 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3138 | 6643d27e | bellard | |
3139 | 6643d27e | bellard | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
|
3140 | 6643d27e | bellard | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
|
3141 | 6643d27e | bellard | _MIPS32 Architecture For Programmers Volume I: Introduction to the
|
3142 | 6643d27e | bellard | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
|
3143 | 6643d27e | bellard | page 1. */
|
3144 | 6643d27e | bellard | { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, |
3145 | 52da07d1 | ths | ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, |
3146 | 6643d27e | bellard | mips_cp0_names_mips3264, |
3147 | 6643d27e | bellard | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), |
3148 | 6643d27e | bellard | mips_hwr_names_numeric }, |
3149 | 6643d27e | bellard | |
3150 | 6643d27e | bellard | { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, |
3151 | 52da07d1 | ths | (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 |
3152 | 52da07d1 | ths | | INSN_MIPS3D | INSN_MT), |
3153 | 6643d27e | bellard | mips_cp0_names_mips3264r2, |
3154 | 6643d27e | bellard | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), |
3155 | 6643d27e | bellard | mips_hwr_names_mips3264r2 }, |
3156 | 6643d27e | bellard | |
3157 | 6643d27e | bellard | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
|
3158 | 6643d27e | bellard | { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, |
3159 | 6643d27e | bellard | ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, |
3160 | 6643d27e | bellard | mips_cp0_names_mips3264, |
3161 | 6643d27e | bellard | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), |
3162 | 6643d27e | bellard | mips_hwr_names_numeric }, |
3163 | 6643d27e | bellard | |
3164 | 6643d27e | bellard | { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, |
3165 | 52da07d1 | ths | (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 |
3166 | 52da07d1 | ths | | INSN_DSP64 | INSN_MT | INSN_MDMX), |
3167 | 6643d27e | bellard | mips_cp0_names_mips3264r2, |
3168 | 6643d27e | bellard | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), |
3169 | 6643d27e | bellard | mips_hwr_names_mips3264r2 }, |
3170 | 6643d27e | bellard | |
3171 | 6643d27e | bellard | { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, |
3172 | 6643d27e | bellard | ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, |
3173 | 6643d27e | bellard | mips_cp0_names_sb1, |
3174 | 6643d27e | bellard | mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), |
3175 | 6643d27e | bellard | mips_hwr_names_numeric }, |
3176 | 6643d27e | bellard | |
3177 | 6643d27e | bellard | /* This entry, mips16, is here only for ISA/processor selection; do
|
3178 | 6643d27e | bellard | not print its name. */
|
3179 | 6643d27e | bellard | { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, |
3180 | 6643d27e | bellard | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3181 | 6643d27e | bellard | }; |
3182 | 6643d27e | bellard | |
3183 | 6643d27e | bellard | /* ISA and processor type to disassemble for, and register names to use.
|
3184 | 6643d27e | bellard | set_default_mips_dis_options and parse_mips_dis_options fill in these
|
3185 | 6643d27e | bellard | values. */
|
3186 | 6643d27e | bellard | static int mips_processor; |
3187 | 6643d27e | bellard | static int mips_isa; |
3188 | 6643d27e | bellard | static const char * const *mips_gpr_names; |
3189 | 6643d27e | bellard | static const char * const *mips_fpr_names; |
3190 | 6643d27e | bellard | static const char * const *mips_cp0_names; |
3191 | 6643d27e | bellard | static const struct mips_cp0sel_name *mips_cp0sel_names; |
3192 | 6643d27e | bellard | static int mips_cp0sel_names_len; |
3193 | 6643d27e | bellard | static const char * const *mips_hwr_names; |
3194 | 6643d27e | bellard | |
3195 | 52da07d1 | ths | /* Other options */
|
3196 | 52da07d1 | ths | static int no_aliases; /* If set disassemble as most general inst. */ |
3197 | 6643d27e | bellard | |
3198 | 6643d27e | bellard | static const struct mips_abi_choice * |
3199 | 52da07d1 | ths | choose_abi_by_name (const char *name, unsigned int namelen) |
3200 | 6643d27e | bellard | { |
3201 | 6643d27e | bellard | const struct mips_abi_choice *c; |
3202 | 6643d27e | bellard | unsigned int i; |
3203 | 6643d27e | bellard | |
3204 | 6643d27e | bellard | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) |
3205 | 52da07d1 | ths | if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 |
3206 | 52da07d1 | ths | && strlen (mips_abi_choices[i].name) == namelen) |
3207 | 52da07d1 | ths | c = &mips_abi_choices[i]; |
3208 | 52da07d1 | ths | |
3209 | 6643d27e | bellard | return c;
|
3210 | 6643d27e | bellard | } |
3211 | 6643d27e | bellard | |
3212 | 6643d27e | bellard | static const struct mips_arch_choice * |
3213 | 52da07d1 | ths | choose_arch_by_name (const char *name, unsigned int namelen) |
3214 | 6643d27e | bellard | { |
3215 | 6643d27e | bellard | const struct mips_arch_choice *c = NULL; |
3216 | 6643d27e | bellard | unsigned int i; |
3217 | 6643d27e | bellard | |
3218 | 6643d27e | bellard | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) |
3219 | 52da07d1 | ths | if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 |
3220 | 52da07d1 | ths | && strlen (mips_arch_choices[i].name) == namelen) |
3221 | 52da07d1 | ths | c = &mips_arch_choices[i]; |
3222 | 52da07d1 | ths | |
3223 | 6643d27e | bellard | return c;
|
3224 | 6643d27e | bellard | } |
3225 | 6643d27e | bellard | |
3226 | 6643d27e | bellard | static const struct mips_arch_choice * |
3227 | 52da07d1 | ths | choose_arch_by_number (unsigned long mach) |
3228 | 6643d27e | bellard | { |
3229 | 6643d27e | bellard | static unsigned long hint_bfd_mach; |
3230 | 6643d27e | bellard | static const struct mips_arch_choice *hint_arch_choice; |
3231 | 6643d27e | bellard | const struct mips_arch_choice *c; |
3232 | 6643d27e | bellard | unsigned int i; |
3233 | 6643d27e | bellard | |
3234 | 6643d27e | bellard | /* We optimize this because even if the user specifies no
|
3235 | 6643d27e | bellard | flags, this will be done for every instruction! */
|
3236 | 6643d27e | bellard | if (hint_bfd_mach == mach
|
3237 | 6643d27e | bellard | && hint_arch_choice != NULL
|
3238 | 6643d27e | bellard | && hint_arch_choice->bfd_mach == hint_bfd_mach) |
3239 | 6643d27e | bellard | return hint_arch_choice;
|
3240 | 6643d27e | bellard | |
3241 | 6643d27e | bellard | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) |
3242 | 6643d27e | bellard | { |
3243 | 6643d27e | bellard | if (mips_arch_choices[i].bfd_mach_valid
|
3244 | 6643d27e | bellard | && mips_arch_choices[i].bfd_mach == mach) |
3245 | 6643d27e | bellard | { |
3246 | 6643d27e | bellard | c = &mips_arch_choices[i]; |
3247 | 6643d27e | bellard | hint_bfd_mach = mach; |
3248 | 6643d27e | bellard | hint_arch_choice = c; |
3249 | 6643d27e | bellard | } |
3250 | 6643d27e | bellard | } |
3251 | 6643d27e | bellard | return c;
|
3252 | 6643d27e | bellard | } |
3253 | 6643d27e | bellard | |
3254 | f9480ffc | ths | static void |
3255 | 52da07d1 | ths | set_default_mips_dis_options (struct disassemble_info *info)
|
3256 | 6643d27e | bellard | { |
3257 | 6643d27e | bellard | const struct mips_arch_choice *chosen_arch; |
3258 | 6643d27e | bellard | |
3259 | 6643d27e | bellard | /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
|
3260 | 6643d27e | bellard | and numeric FPR, CP0 register, and HWR names. */
|
3261 | 6643d27e | bellard | mips_isa = ISA_MIPS3; |
3262 | 6643d27e | bellard | mips_processor = CPU_R3000; |
3263 | 6643d27e | bellard | mips_gpr_names = mips_gpr_names_oldabi; |
3264 | 6643d27e | bellard | mips_fpr_names = mips_fpr_names_numeric; |
3265 | 6643d27e | bellard | mips_cp0_names = mips_cp0_names_numeric; |
3266 | 6643d27e | bellard | mips_cp0sel_names = NULL;
|
3267 | 6643d27e | bellard | mips_cp0sel_names_len = 0;
|
3268 | 6643d27e | bellard | mips_hwr_names = mips_hwr_names_numeric; |
3269 | 52da07d1 | ths | no_aliases = 0;
|
3270 | 6643d27e | bellard | |
3271 | 6643d27e | bellard | /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
|
3272 | 6643d27e | bellard | #if 0
|
3273 | 6643d27e | bellard | if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
|
3274 | 6643d27e | bellard | {
|
3275 | 6643d27e | bellard | Elf_Internal_Ehdr *header;
|
3276 | 6643d27e | bellard | |
3277 | 6643d27e | bellard | header = elf_elfheader (info->section->owner);
|
3278 | 6643d27e | bellard | if (is_newabi (header))
|
3279 | 6643d27e | bellard | mips_gpr_names = mips_gpr_names_newabi;
|
3280 | 6643d27e | bellard | }
|
3281 | 6643d27e | bellard | #endif
|
3282 | 6643d27e | bellard | |
3283 | 6643d27e | bellard | /* Set ISA, architecture, and cp0 register names as best we can. */
|
3284 | eb38c52c | blueswir1 | #if !defined(SYMTAB_AVAILABLE) && 0 |
3285 | 6643d27e | bellard | /* This is running out on a target machine, not in a host tool.
|
3286 | 6643d27e | bellard | FIXME: Where does mips_target_info come from? */
|
3287 | 6643d27e | bellard | target_processor = mips_target_info.processor; |
3288 | 6643d27e | bellard | mips_isa = mips_target_info.isa; |
3289 | 6643d27e | bellard | #else
|
3290 | 6643d27e | bellard | chosen_arch = choose_arch_by_number (info->mach); |
3291 | 6643d27e | bellard | if (chosen_arch != NULL) |
3292 | 6643d27e | bellard | { |
3293 | 6643d27e | bellard | mips_processor = chosen_arch->processor; |
3294 | 6643d27e | bellard | mips_isa = chosen_arch->isa; |
3295 | 6643d27e | bellard | mips_cp0_names = chosen_arch->cp0_names; |
3296 | 6643d27e | bellard | mips_cp0sel_names = chosen_arch->cp0sel_names; |
3297 | 6643d27e | bellard | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
3298 | 6643d27e | bellard | mips_hwr_names = chosen_arch->hwr_names; |
3299 | 6643d27e | bellard | } |
3300 | 6643d27e | bellard | #endif
|
3301 | 6643d27e | bellard | } |
3302 | 6643d27e | bellard | |
3303 | f9480ffc | ths | static void |
3304 | a5f1b965 | blueswir1 | parse_mips_dis_option (const char *option, unsigned int len) |
3305 | 6643d27e | bellard | { |
3306 | 6643d27e | bellard | unsigned int i, optionlen, vallen; |
3307 | 6643d27e | bellard | const char *val; |
3308 | 6643d27e | bellard | const struct mips_abi_choice *chosen_abi; |
3309 | 6643d27e | bellard | const struct mips_arch_choice *chosen_arch; |
3310 | 6643d27e | bellard | |
3311 | 6643d27e | bellard | /* Look for the = that delimits the end of the option name. */
|
3312 | 6643d27e | bellard | for (i = 0; i < len; i++) |
3313 | 6643d27e | bellard | { |
3314 | 6643d27e | bellard | if (option[i] == '=') |
3315 | 6643d27e | bellard | break;
|
3316 | 6643d27e | bellard | } |
3317 | 6643d27e | bellard | if (i == 0) /* Invalid option: no name before '='. */ |
3318 | 6643d27e | bellard | return;
|
3319 | 6643d27e | bellard | if (i == len) /* Invalid option: no '='. */ |
3320 | 6643d27e | bellard | return;
|
3321 | 6643d27e | bellard | if (i == (len - 1)) /* Invalid option: no value after '='. */ |
3322 | 6643d27e | bellard | return;
|
3323 | 6643d27e | bellard | |
3324 | 6643d27e | bellard | optionlen = i; |
3325 | 6643d27e | bellard | val = option + (optionlen + 1);
|
3326 | 6643d27e | bellard | vallen = len - (optionlen + 1);
|
3327 | 6643d27e | bellard | |
3328 | 6643d27e | bellard | if (strncmp("gpr-names", option, optionlen) == 0 |
3329 | 6643d27e | bellard | && strlen("gpr-names") == optionlen)
|
3330 | 6643d27e | bellard | { |
3331 | 6643d27e | bellard | chosen_abi = choose_abi_by_name (val, vallen); |
3332 | 6643d27e | bellard | if (chosen_abi != NULL) |
3333 | 6643d27e | bellard | mips_gpr_names = chosen_abi->gpr_names; |
3334 | 6643d27e | bellard | return;
|
3335 | 6643d27e | bellard | } |
3336 | 6643d27e | bellard | |
3337 | 6643d27e | bellard | if (strncmp("fpr-names", option, optionlen) == 0 |
3338 | 6643d27e | bellard | && strlen("fpr-names") == optionlen)
|
3339 | 6643d27e | bellard | { |
3340 | 6643d27e | bellard | chosen_abi = choose_abi_by_name (val, vallen); |
3341 | 6643d27e | bellard | if (chosen_abi != NULL) |
3342 | 6643d27e | bellard | mips_fpr_names = chosen_abi->fpr_names; |
3343 | 6643d27e | bellard | return;
|
3344 | 6643d27e | bellard | } |
3345 | 6643d27e | bellard | |
3346 | 6643d27e | bellard | if (strncmp("cp0-names", option, optionlen) == 0 |
3347 | 6643d27e | bellard | && strlen("cp0-names") == optionlen)
|
3348 | 6643d27e | bellard | { |
3349 | 6643d27e | bellard | chosen_arch = choose_arch_by_name (val, vallen); |
3350 | 6643d27e | bellard | if (chosen_arch != NULL) |
3351 | 6643d27e | bellard | { |
3352 | 6643d27e | bellard | mips_cp0_names = chosen_arch->cp0_names; |
3353 | 6643d27e | bellard | mips_cp0sel_names = chosen_arch->cp0sel_names; |
3354 | 6643d27e | bellard | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
3355 | 6643d27e | bellard | } |
3356 | 6643d27e | bellard | return;
|
3357 | 6643d27e | bellard | } |
3358 | 6643d27e | bellard | |
3359 | 6643d27e | bellard | if (strncmp("hwr-names", option, optionlen) == 0 |
3360 | 6643d27e | bellard | && strlen("hwr-names") == optionlen)
|
3361 | 6643d27e | bellard | { |
3362 | 6643d27e | bellard | chosen_arch = choose_arch_by_name (val, vallen); |
3363 | 6643d27e | bellard | if (chosen_arch != NULL) |
3364 | 6643d27e | bellard | mips_hwr_names = chosen_arch->hwr_names; |
3365 | 6643d27e | bellard | return;
|
3366 | 6643d27e | bellard | } |
3367 | 6643d27e | bellard | |
3368 | 6643d27e | bellard | if (strncmp("reg-names", option, optionlen) == 0 |
3369 | 6643d27e | bellard | && strlen("reg-names") == optionlen)
|
3370 | 6643d27e | bellard | { |
3371 | 6643d27e | bellard | /* We check both ABI and ARCH here unconditionally, so
|
3372 | 6643d27e | bellard | that "numeric" will do the desirable thing: select
|
3373 | 6643d27e | bellard | numeric register names for all registers. Other than
|
3374 | 6643d27e | bellard | that, a given name probably won't match both. */
|
3375 | 6643d27e | bellard | chosen_abi = choose_abi_by_name (val, vallen); |
3376 | 6643d27e | bellard | if (chosen_abi != NULL) |
3377 | 6643d27e | bellard | { |
3378 | 6643d27e | bellard | mips_gpr_names = chosen_abi->gpr_names; |
3379 | 6643d27e | bellard | mips_fpr_names = chosen_abi->fpr_names; |
3380 | 6643d27e | bellard | } |
3381 | 6643d27e | bellard | chosen_arch = choose_arch_by_name (val, vallen); |
3382 | 6643d27e | bellard | if (chosen_arch != NULL) |
3383 | 6643d27e | bellard | { |
3384 | 6643d27e | bellard | mips_cp0_names = chosen_arch->cp0_names; |
3385 | 6643d27e | bellard | mips_cp0sel_names = chosen_arch->cp0sel_names; |
3386 | 6643d27e | bellard | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
3387 | 6643d27e | bellard | mips_hwr_names = chosen_arch->hwr_names; |
3388 | 6643d27e | bellard | } |
3389 | 6643d27e | bellard | return;
|
3390 | 6643d27e | bellard | } |
3391 | 6643d27e | bellard | |
3392 | 6643d27e | bellard | /* Invalid option. */
|
3393 | 6643d27e | bellard | } |
3394 | 6643d27e | bellard | |
3395 | 52da07d1 | ths | static void |
3396 | 52da07d1 | ths | parse_mips_dis_options (const char *options) |
3397 | 6643d27e | bellard | { |
3398 | 6643d27e | bellard | const char *option_end; |
3399 | 6643d27e | bellard | |
3400 | 6643d27e | bellard | if (options == NULL) |
3401 | 6643d27e | bellard | return;
|
3402 | 6643d27e | bellard | |
3403 | 6643d27e | bellard | while (*options != '\0') |
3404 | 6643d27e | bellard | { |
3405 | 6643d27e | bellard | /* Skip empty options. */
|
3406 | 6643d27e | bellard | if (*options == ',') |
3407 | 6643d27e | bellard | { |
3408 | 6643d27e | bellard | options++; |
3409 | 6643d27e | bellard | continue;
|
3410 | 6643d27e | bellard | } |
3411 | 6643d27e | bellard | |
3412 | 6643d27e | bellard | /* We know that *options is neither NUL or a comma. */
|
3413 | 6643d27e | bellard | option_end = options + 1;
|
3414 | 6643d27e | bellard | while (*option_end != ',' && *option_end != '\0') |
3415 | 6643d27e | bellard | option_end++; |
3416 | 6643d27e | bellard | |
3417 | 6643d27e | bellard | parse_mips_dis_option (options, option_end - options); |
3418 | 6643d27e | bellard | |
3419 | 6643d27e | bellard | /* Go on to the next one. If option_end points to a comma, it
|
3420 | 6643d27e | bellard | will be skipped above. */
|
3421 | 6643d27e | bellard | options = option_end; |
3422 | 6643d27e | bellard | } |
3423 | 6643d27e | bellard | } |
3424 | 6643d27e | bellard | |
3425 | 6643d27e | bellard | static const struct mips_cp0sel_name * |
3426 | 52da07d1 | ths | lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, |
3427 | 52da07d1 | ths | unsigned int len, |
3428 | 52da07d1 | ths | unsigned int cp0reg, |
3429 | 52da07d1 | ths | unsigned int sel) |
3430 | 6643d27e | bellard | { |
3431 | 6643d27e | bellard | unsigned int i; |
3432 | 6643d27e | bellard | |
3433 | 6643d27e | bellard | for (i = 0; i < len; i++) |
3434 | 6643d27e | bellard | if (names[i].cp0reg == cp0reg && names[i].sel == sel)
|
3435 | 6643d27e | bellard | return &names[i];
|
3436 | 6643d27e | bellard | return NULL; |
3437 | 6643d27e | bellard | } |
3438 | 6643d27e | bellard | |
3439 | 6643d27e | bellard | /* Print insn arguments for 32/64-bit code. */
|
3440 | 6643d27e | bellard | |
3441 | 6643d27e | bellard | static void |
3442 | 52da07d1 | ths | print_insn_args (const char *d, |
3443 | 52da07d1 | ths | register unsigned long int l, |
3444 | 52da07d1 | ths | bfd_vma pc, |
3445 | 52da07d1 | ths | struct disassemble_info *info,
|
3446 | 52da07d1 | ths | const struct mips_opcode *opp) |
3447 | 6643d27e | bellard | { |
3448 | 6643d27e | bellard | int op, delta;
|
3449 | 6643d27e | bellard | unsigned int lsb, msb, msbd; |
3450 | 6643d27e | bellard | |
3451 | 6643d27e | bellard | lsb = 0;
|
3452 | 6643d27e | bellard | |
3453 | 6643d27e | bellard | for (; *d != '\0'; d++) |
3454 | 6643d27e | bellard | { |
3455 | 6643d27e | bellard | switch (*d)
|
3456 | 6643d27e | bellard | { |
3457 | 6643d27e | bellard | case ',': |
3458 | 6643d27e | bellard | case '(': |
3459 | 6643d27e | bellard | case ')': |
3460 | 6643d27e | bellard | case '[': |
3461 | 6643d27e | bellard | case ']': |
3462 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%c", *d);
|
3463 | 6643d27e | bellard | break;
|
3464 | 6643d27e | bellard | |
3465 | 6643d27e | bellard | case '+': |
3466 | 6643d27e | bellard | /* Extension character; switch for second char. */
|
3467 | 6643d27e | bellard | d++; |
3468 | 6643d27e | bellard | switch (*d)
|
3469 | 6643d27e | bellard | { |
3470 | 6643d27e | bellard | case '\0': |
3471 | 6643d27e | bellard | /* xgettext:c-format */
|
3472 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, |
3473 | 6643d27e | bellard | _("# internal error, incomplete extension sequence (+)"));
|
3474 | 6643d27e | bellard | return;
|
3475 | 6643d27e | bellard | |
3476 | 6643d27e | bellard | case 'A': |
3477 | 6643d27e | bellard | lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; |
3478 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", lsb);
|
3479 | 6643d27e | bellard | break;
|
3480 | 52da07d1 | ths | |
3481 | 6643d27e | bellard | case 'B': |
3482 | 6643d27e | bellard | msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; |
3483 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); |
3484 | 6643d27e | bellard | break;
|
3485 | 6643d27e | bellard | |
3486 | 52da07d1 | ths | case '1': |
3487 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3488 | 52da07d1 | ths | (l >> OP_SH_UDI1) & OP_MASK_UDI1); |
3489 | 52da07d1 | ths | break;
|
3490 | 52da07d1 | ths | |
3491 | 52da07d1 | ths | case '2': |
3492 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3493 | 52da07d1 | ths | (l >> OP_SH_UDI2) & OP_MASK_UDI2); |
3494 | 52da07d1 | ths | break;
|
3495 | 52da07d1 | ths | |
3496 | 52da07d1 | ths | case '3': |
3497 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3498 | 52da07d1 | ths | (l >> OP_SH_UDI3) & OP_MASK_UDI3); |
3499 | 52da07d1 | ths | break;
|
3500 | 52da07d1 | ths | |
3501 | 52da07d1 | ths | case '4': |
3502 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3503 | 52da07d1 | ths | (l >> OP_SH_UDI4) & OP_MASK_UDI4); |
3504 | 52da07d1 | ths | break;
|
3505 | 52da07d1 | ths | |
3506 | 6643d27e | bellard | case 'C': |
3507 | 6643d27e | bellard | case 'H': |
3508 | 6643d27e | bellard | msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; |
3509 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); |
3510 | 6643d27e | bellard | break;
|
3511 | 6643d27e | bellard | |
3512 | 6643d27e | bellard | case 'D': |
3513 | 6643d27e | bellard | { |
3514 | 6643d27e | bellard | const struct mips_cp0sel_name *n; |
3515 | 6643d27e | bellard | unsigned int cp0reg, sel; |
3516 | 6643d27e | bellard | |
3517 | 6643d27e | bellard | cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; |
3518 | 6643d27e | bellard | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; |
3519 | 6643d27e | bellard | |
3520 | 6643d27e | bellard | /* CP0 register including 'sel' code for mtcN (et al.), to be
|
3521 | 6643d27e | bellard | printed textually if known. If not known, print both
|
3522 | 6643d27e | bellard | CP0 register name and sel numerically since CP0 register
|
3523 | 6643d27e | bellard | with sel 0 may have a name unrelated to register being
|
3524 | 6643d27e | bellard | printed. */
|
3525 | 6643d27e | bellard | n = lookup_mips_cp0sel_name(mips_cp0sel_names, |
3526 | 6643d27e | bellard | mips_cp0sel_names_len, cp0reg, sel); |
3527 | 6643d27e | bellard | if (n != NULL) |
3528 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", n->name);
|
3529 | 6643d27e | bellard | else
|
3530 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
|
3531 | 6643d27e | bellard | break;
|
3532 | 6643d27e | bellard | } |
3533 | 6643d27e | bellard | |
3534 | 6643d27e | bellard | case 'E': |
3535 | 6643d27e | bellard | lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
|
3536 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", lsb);
|
3537 | 6643d27e | bellard | break;
|
3538 | 5fafdf24 | ths | |
3539 | 6643d27e | bellard | case 'F': |
3540 | 6643d27e | bellard | msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
|
3541 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); |
3542 | 6643d27e | bellard | break;
|
3543 | 6643d27e | bellard | |
3544 | 6643d27e | bellard | case 'G': |
3545 | 6643d27e | bellard | msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
|
3546 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); |
3547 | 6643d27e | bellard | break;
|
3548 | 6643d27e | bellard | |
3549 | 52da07d1 | ths | case 't': /* Coprocessor 0 reg name */ |
3550 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%s",
|
3551 | 52da07d1 | ths | mips_cp0_names[(l >> OP_SH_RT) & |
3552 | 52da07d1 | ths | OP_MASK_RT]); |
3553 | 52da07d1 | ths | break;
|
3554 | 52da07d1 | ths | |
3555 | 52da07d1 | ths | case 'T': /* Coprocessor 0 reg name */ |
3556 | 52da07d1 | ths | { |
3557 | 52da07d1 | ths | const struct mips_cp0sel_name *n; |
3558 | 52da07d1 | ths | unsigned int cp0reg, sel; |
3559 | 52da07d1 | ths | |
3560 | 52da07d1 | ths | cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; |
3561 | 52da07d1 | ths | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; |
3562 | 52da07d1 | ths | |
3563 | 52da07d1 | ths | /* CP0 register including 'sel' code for mftc0, to be
|
3564 | 52da07d1 | ths | printed textually if known. If not known, print both
|
3565 | 52da07d1 | ths | CP0 register name and sel numerically since CP0 register
|
3566 | 52da07d1 | ths | with sel 0 may have a name unrelated to register being
|
3567 | 52da07d1 | ths | printed. */
|
3568 | 52da07d1 | ths | n = lookup_mips_cp0sel_name(mips_cp0sel_names, |
3569 | 52da07d1 | ths | mips_cp0sel_names_len, cp0reg, sel); |
3570 | 52da07d1 | ths | if (n != NULL) |
3571 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%s", n->name);
|
3572 | 52da07d1 | ths | else
|
3573 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
|
3574 | 52da07d1 | ths | break;
|
3575 | 52da07d1 | ths | } |
3576 | 52da07d1 | ths | |
3577 | 6643d27e | bellard | default:
|
3578 | 6643d27e | bellard | /* xgettext:c-format */
|
3579 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, |
3580 | 6643d27e | bellard | _("# internal error, undefined extension sequence (+%c)"),
|
3581 | 6643d27e | bellard | *d); |
3582 | 6643d27e | bellard | return;
|
3583 | 6643d27e | bellard | } |
3584 | 6643d27e | bellard | break;
|
3585 | 6643d27e | bellard | |
3586 | 52da07d1 | ths | case '2': |
3587 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3588 | 52da07d1 | ths | (l >> OP_SH_BP) & OP_MASK_BP); |
3589 | 52da07d1 | ths | break;
|
3590 | 52da07d1 | ths | |
3591 | 52da07d1 | ths | case '3': |
3592 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3593 | 52da07d1 | ths | (l >> OP_SH_SA3) & OP_MASK_SA3); |
3594 | 52da07d1 | ths | break;
|
3595 | 52da07d1 | ths | |
3596 | 52da07d1 | ths | case '4': |
3597 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3598 | 52da07d1 | ths | (l >> OP_SH_SA4) & OP_MASK_SA4); |
3599 | 52da07d1 | ths | break;
|
3600 | 52da07d1 | ths | |
3601 | 52da07d1 | ths | case '5': |
3602 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3603 | 52da07d1 | ths | (l >> OP_SH_IMM8) & OP_MASK_IMM8); |
3604 | 52da07d1 | ths | break;
|
3605 | 52da07d1 | ths | |
3606 | 52da07d1 | ths | case '6': |
3607 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3608 | 52da07d1 | ths | (l >> OP_SH_RS) & OP_MASK_RS); |
3609 | 52da07d1 | ths | break;
|
3610 | 52da07d1 | ths | |
3611 | 52da07d1 | ths | case '7': |
3612 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$ac%ld",
|
3613 | 52da07d1 | ths | (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); |
3614 | 52da07d1 | ths | break;
|
3615 | 52da07d1 | ths | |
3616 | 52da07d1 | ths | case '8': |
3617 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3618 | 52da07d1 | ths | (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); |
3619 | 52da07d1 | ths | break;
|
3620 | 52da07d1 | ths | |
3621 | 52da07d1 | ths | case '9': |
3622 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$ac%ld",
|
3623 | 52da07d1 | ths | (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); |
3624 | 52da07d1 | ths | break;
|
3625 | 52da07d1 | ths | |
3626 | 52da07d1 | ths | case '0': /* dsp 6-bit signed immediate in bit 20 */ |
3627 | 52da07d1 | ths | delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); |
3628 | 52da07d1 | ths | if (delta & 0x20) /* test sign bit */ |
3629 | 52da07d1 | ths | delta |= ~OP_MASK_DSPSFT; |
3630 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%d", delta);
|
3631 | 52da07d1 | ths | break;
|
3632 | 52da07d1 | ths | |
3633 | 52da07d1 | ths | case ':': /* dsp 7-bit signed immediate in bit 19 */ |
3634 | 52da07d1 | ths | delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); |
3635 | 52da07d1 | ths | if (delta & 0x40) /* test sign bit */ |
3636 | 52da07d1 | ths | delta |= ~OP_MASK_DSPSFT_7; |
3637 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%d", delta);
|
3638 | 52da07d1 | ths | break;
|
3639 | 52da07d1 | ths | |
3640 | 52da07d1 | ths | case '\'': |
3641 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3642 | 52da07d1 | ths | (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); |
3643 | 52da07d1 | ths | break;
|
3644 | 52da07d1 | ths | |
3645 | 52da07d1 | ths | case '@': /* dsp 10-bit signed immediate in bit 16 */ |
3646 | 52da07d1 | ths | delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); |
3647 | 52da07d1 | ths | if (delta & 0x200) /* test sign bit */ |
3648 | 52da07d1 | ths | delta |= ~OP_MASK_IMM10; |
3649 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%d", delta);
|
3650 | 52da07d1 | ths | break;
|
3651 | 52da07d1 | ths | |
3652 | 52da07d1 | ths | case '!': |
3653 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3654 | 52da07d1 | ths | (l >> OP_SH_MT_U) & OP_MASK_MT_U); |
3655 | 52da07d1 | ths | break;
|
3656 | 52da07d1 | ths | |
3657 | 52da07d1 | ths | case '$': |
3658 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3659 | 52da07d1 | ths | (l >> OP_SH_MT_H) & OP_MASK_MT_H); |
3660 | 52da07d1 | ths | break;
|
3661 | 52da07d1 | ths | |
3662 | 52da07d1 | ths | case '*': |
3663 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$ac%ld",
|
3664 | 52da07d1 | ths | (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); |
3665 | 52da07d1 | ths | break;
|
3666 | 52da07d1 | ths | |
3667 | 52da07d1 | ths | case '&': |
3668 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$ac%ld",
|
3669 | 52da07d1 | ths | (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); |
3670 | 52da07d1 | ths | break;
|
3671 | 52da07d1 | ths | |
3672 | 52da07d1 | ths | case 'g': |
3673 | 52da07d1 | ths | /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
|
3674 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$%ld",
|
3675 | 52da07d1 | ths | (l >> OP_SH_RD) & OP_MASK_RD); |
3676 | 52da07d1 | ths | break;
|
3677 | 52da07d1 | ths | |
3678 | 6643d27e | bellard | case 's': |
3679 | 6643d27e | bellard | case 'b': |
3680 | 6643d27e | bellard | case 'r': |
3681 | 6643d27e | bellard | case 'v': |
3682 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3683 | 6643d27e | bellard | mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); |
3684 | 6643d27e | bellard | break;
|
3685 | 6643d27e | bellard | |
3686 | 6643d27e | bellard | case 't': |
3687 | 6643d27e | bellard | case 'w': |
3688 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3689 | 6643d27e | bellard | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
3690 | 6643d27e | bellard | break;
|
3691 | 6643d27e | bellard | |
3692 | 6643d27e | bellard | case 'i': |
3693 | 6643d27e | bellard | case 'u': |
3694 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3695 | 6643d27e | bellard | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
3696 | 6643d27e | bellard | break;
|
3697 | 6643d27e | bellard | |
3698 | 6643d27e | bellard | case 'j': /* Same as i, but sign-extended. */ |
3699 | 6643d27e | bellard | case 'o': |
3700 | 6643d27e | bellard | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
3701 | 6643d27e | bellard | if (delta & 0x8000) |
3702 | 6643d27e | bellard | delta |= ~0xffff;
|
3703 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%d",
|
3704 | 6643d27e | bellard | delta); |
3705 | 6643d27e | bellard | break;
|
3706 | 6643d27e | bellard | |
3707 | 6643d27e | bellard | case 'h': |
3708 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x",
|
3709 | 6643d27e | bellard | (unsigned int) ((l >> OP_SH_PREFX) |
3710 | 6643d27e | bellard | & OP_MASK_PREFX)); |
3711 | 6643d27e | bellard | break;
|
3712 | 6643d27e | bellard | |
3713 | 6643d27e | bellard | case 'k': |
3714 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x",
|
3715 | 6643d27e | bellard | (unsigned int) ((l >> OP_SH_CACHE) |
3716 | 6643d27e | bellard | & OP_MASK_CACHE)); |
3717 | 6643d27e | bellard | break;
|
3718 | 6643d27e | bellard | |
3719 | 6643d27e | bellard | case 'a': |
3720 | 6643d27e | bellard | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) |
3721 | 6643d27e | bellard | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
|
3722 | 52da07d1 | ths | /* For gdb disassembler, force odd address on jalx. */
|
3723 | 52da07d1 | ths | if (info->flavour == bfd_target_unknown_flavour
|
3724 | 52da07d1 | ths | && strcmp (opp->name, "jalx") == 0) |
3725 | 52da07d1 | ths | info->target |= 1;
|
3726 | 6643d27e | bellard | (*info->print_address_func) (info->target, info); |
3727 | 6643d27e | bellard | break;
|
3728 | 6643d27e | bellard | |
3729 | 6643d27e | bellard | case 'p': |
3730 | 6643d27e | bellard | /* Sign extend the displacement. */
|
3731 | 6643d27e | bellard | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
3732 | 6643d27e | bellard | if (delta & 0x8000) |
3733 | 6643d27e | bellard | delta |= ~0xffff;
|
3734 | 6643d27e | bellard | info->target = (delta << 2) + pc + INSNLEN;
|
3735 | 6643d27e | bellard | (*info->print_address_func) (info->target, info); |
3736 | 6643d27e | bellard | break;
|
3737 | 6643d27e | bellard | |
3738 | 6643d27e | bellard | case 'd': |
3739 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3740 | 6643d27e | bellard | mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
3741 | 6643d27e | bellard | break;
|
3742 | 6643d27e | bellard | |
3743 | 6643d27e | bellard | case 'U': |
3744 | 6643d27e | bellard | { |
3745 | 6643d27e | bellard | /* First check for both rd and rt being equal. */
|
3746 | 6643d27e | bellard | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; |
3747 | 6643d27e | bellard | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
|
3748 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3749 | 6643d27e | bellard | mips_gpr_names[reg]); |
3750 | 6643d27e | bellard | else
|
3751 | 6643d27e | bellard | { |
3752 | 6643d27e | bellard | /* If one is zero use the other. */
|
3753 | 6643d27e | bellard | if (reg == 0) |
3754 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3755 | 6643d27e | bellard | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
3756 | 6643d27e | bellard | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) |
3757 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3758 | 6643d27e | bellard | mips_gpr_names[reg]); |
3759 | 6643d27e | bellard | else /* Bogus, result depends on processor. */ |
3760 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s or %s",
|
3761 | 6643d27e | bellard | mips_gpr_names[reg], |
3762 | 6643d27e | bellard | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
3763 | 6643d27e | bellard | } |
3764 | 6643d27e | bellard | } |
3765 | 6643d27e | bellard | break;
|
3766 | 6643d27e | bellard | |
3767 | 6643d27e | bellard | case 'z': |
3768 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
3769 | 6643d27e | bellard | break;
|
3770 | 6643d27e | bellard | |
3771 | 6643d27e | bellard | case '<': |
3772 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3773 | 6643d27e | bellard | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); |
3774 | 6643d27e | bellard | break;
|
3775 | 6643d27e | bellard | |
3776 | 6643d27e | bellard | case 'c': |
3777 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3778 | 6643d27e | bellard | (l >> OP_SH_CODE) & OP_MASK_CODE); |
3779 | 6643d27e | bellard | break;
|
3780 | 6643d27e | bellard | |
3781 | 6643d27e | bellard | case 'q': |
3782 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3783 | 6643d27e | bellard | (l >> OP_SH_CODE2) & OP_MASK_CODE2); |
3784 | 6643d27e | bellard | break;
|
3785 | 6643d27e | bellard | |
3786 | 6643d27e | bellard | case 'C': |
3787 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3788 | 6643d27e | bellard | (l >> OP_SH_COPZ) & OP_MASK_COPZ); |
3789 | 6643d27e | bellard | break;
|
3790 | 6643d27e | bellard | |
3791 | 6643d27e | bellard | case 'B': |
3792 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3793 | 52da07d1 | ths | |
3794 | 6643d27e | bellard | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
3795 | 6643d27e | bellard | break;
|
3796 | 6643d27e | bellard | |
3797 | 6643d27e | bellard | case 'J': |
3798 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3799 | 6643d27e | bellard | (l >> OP_SH_CODE19) & OP_MASK_CODE19); |
3800 | 6643d27e | bellard | break;
|
3801 | 6643d27e | bellard | |
3802 | 6643d27e | bellard | case 'S': |
3803 | 6643d27e | bellard | case 'V': |
3804 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3805 | 6643d27e | bellard | mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); |
3806 | 6643d27e | bellard | break;
|
3807 | 6643d27e | bellard | |
3808 | 6643d27e | bellard | case 'T': |
3809 | 6643d27e | bellard | case 'W': |
3810 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3811 | 6643d27e | bellard | mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); |
3812 | 6643d27e | bellard | break;
|
3813 | 6643d27e | bellard | |
3814 | 6643d27e | bellard | case 'D': |
3815 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3816 | 6643d27e | bellard | mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); |
3817 | 6643d27e | bellard | break;
|
3818 | 6643d27e | bellard | |
3819 | 6643d27e | bellard | case 'R': |
3820 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3821 | 6643d27e | bellard | mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); |
3822 | 6643d27e | bellard | break;
|
3823 | 6643d27e | bellard | |
3824 | 6643d27e | bellard | case 'E': |
3825 | 6643d27e | bellard | /* Coprocessor register for lwcN instructions, et al.
|
3826 | 6643d27e | bellard | |
3827 | 6643d27e | bellard | Note that there is no load/store cp0 instructions, and
|
3828 | 6643d27e | bellard | that FPU (cp1) instructions disassemble this field using
|
3829 | 6643d27e | bellard | 'T' format. Therefore, until we gain understanding of
|
3830 | 6643d27e | bellard | cp2 register names, we can simply print the register
|
3831 | 6643d27e | bellard | numbers. */
|
3832 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$%ld",
|
3833 | 6643d27e | bellard | (l >> OP_SH_RT) & OP_MASK_RT); |
3834 | 6643d27e | bellard | break;
|
3835 | 6643d27e | bellard | |
3836 | 6643d27e | bellard | case 'G': |
3837 | 6643d27e | bellard | /* Coprocessor register for mtcN instructions, et al. Note
|
3838 | 6643d27e | bellard | that FPU (cp1) instructions disassemble this field using
|
3839 | 6643d27e | bellard | 'S' format. Therefore, we only need to worry about cp0,
|
3840 | 6643d27e | bellard | cp2, and cp3. */
|
3841 | 6643d27e | bellard | op = (l >> OP_SH_OP) & OP_MASK_OP; |
3842 | 6643d27e | bellard | if (op == OP_OP_COP0)
|
3843 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3844 | 6643d27e | bellard | mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
3845 | 6643d27e | bellard | else
|
3846 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$%ld",
|
3847 | 6643d27e | bellard | (l >> OP_SH_RD) & OP_MASK_RD); |
3848 | 6643d27e | bellard | break;
|
3849 | 6643d27e | bellard | |
3850 | 6643d27e | bellard | case 'K': |
3851 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
3852 | 6643d27e | bellard | mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
3853 | 6643d27e | bellard | break;
|
3854 | 6643d27e | bellard | |
3855 | 6643d27e | bellard | case 'N': |
3856 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, |
3857 | 52da07d1 | ths | ((opp->pinfo & (FP_D | FP_S)) != 0
|
3858 | 52da07d1 | ths | ? "$fcc%ld" : "$cc%ld"), |
3859 | 6643d27e | bellard | (l >> OP_SH_BCC) & OP_MASK_BCC); |
3860 | 6643d27e | bellard | break;
|
3861 | 6643d27e | bellard | |
3862 | 6643d27e | bellard | case 'M': |
3863 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$fcc%ld",
|
3864 | 6643d27e | bellard | (l >> OP_SH_CCC) & OP_MASK_CCC); |
3865 | 6643d27e | bellard | break;
|
3866 | 6643d27e | bellard | |
3867 | 6643d27e | bellard | case 'P': |
3868 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3869 | 6643d27e | bellard | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); |
3870 | 6643d27e | bellard | break;
|
3871 | 6643d27e | bellard | |
3872 | 6643d27e | bellard | case 'e': |
3873 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3874 | 6643d27e | bellard | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); |
3875 | 6643d27e | bellard | break;
|
3876 | 6643d27e | bellard | |
3877 | 6643d27e | bellard | case '%': |
3878 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3879 | 6643d27e | bellard | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); |
3880 | 6643d27e | bellard | break;
|
3881 | 6643d27e | bellard | |
3882 | 6643d27e | bellard | case 'H': |
3883 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3884 | 6643d27e | bellard | (l >> OP_SH_SEL) & OP_MASK_SEL); |
3885 | 6643d27e | bellard | break;
|
3886 | 6643d27e | bellard | |
3887 | 6643d27e | bellard | case 'O': |
3888 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%ld",
|
3889 | 6643d27e | bellard | (l >> OP_SH_ALN) & OP_MASK_ALN); |
3890 | 6643d27e | bellard | break;
|
3891 | 6643d27e | bellard | |
3892 | 6643d27e | bellard | case 'Q': |
3893 | 6643d27e | bellard | { |
3894 | 6643d27e | bellard | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; |
3895 | 52da07d1 | ths | |
3896 | 6643d27e | bellard | if ((vsel & 0x10) == 0) |
3897 | 6643d27e | bellard | { |
3898 | 6643d27e | bellard | int fmt;
|
3899 | 52da07d1 | ths | |
3900 | 6643d27e | bellard | vsel &= 0x0f;
|
3901 | 6643d27e | bellard | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) |
3902 | 6643d27e | bellard | if ((vsel & 1) == 0) |
3903 | 6643d27e | bellard | break;
|
3904 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$v%ld[%d]",
|
3905 | 6643d27e | bellard | (l >> OP_SH_FT) & OP_MASK_FT, |
3906 | 6643d27e | bellard | vsel >> 1);
|
3907 | 6643d27e | bellard | } |
3908 | 6643d27e | bellard | else if ((vsel & 0x08) == 0) |
3909 | 6643d27e | bellard | { |
3910 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$v%ld",
|
3911 | 6643d27e | bellard | (l >> OP_SH_FT) & OP_MASK_FT); |
3912 | 6643d27e | bellard | } |
3913 | 6643d27e | bellard | else
|
3914 | 6643d27e | bellard | { |
3915 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx",
|
3916 | 6643d27e | bellard | (l >> OP_SH_FT) & OP_MASK_FT); |
3917 | 6643d27e | bellard | } |
3918 | 6643d27e | bellard | } |
3919 | 6643d27e | bellard | break;
|
3920 | 6643d27e | bellard | |
3921 | 6643d27e | bellard | case 'X': |
3922 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$v%ld",
|
3923 | 6643d27e | bellard | (l >> OP_SH_FD) & OP_MASK_FD); |
3924 | 6643d27e | bellard | break;
|
3925 | 6643d27e | bellard | |
3926 | 6643d27e | bellard | case 'Y': |
3927 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$v%ld",
|
3928 | 6643d27e | bellard | (l >> OP_SH_FS) & OP_MASK_FS); |
3929 | 6643d27e | bellard | break;
|
3930 | 6643d27e | bellard | |
3931 | 6643d27e | bellard | case 'Z': |
3932 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "$v%ld",
|
3933 | 6643d27e | bellard | (l >> OP_SH_FT) & OP_MASK_FT); |
3934 | 6643d27e | bellard | break;
|
3935 | 6643d27e | bellard | |
3936 | 6643d27e | bellard | default:
|
3937 | 6643d27e | bellard | /* xgettext:c-format */
|
3938 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, |
3939 | 6643d27e | bellard | _("# internal error, undefined modifier(%c)"),
|
3940 | 6643d27e | bellard | *d); |
3941 | 6643d27e | bellard | return;
|
3942 | 6643d27e | bellard | } |
3943 | 6643d27e | bellard | } |
3944 | 6643d27e | bellard | } |
3945 | 6643d27e | bellard | |
3946 | 6643d27e | bellard | /* Check if the object uses NewABI conventions. */
|
3947 | 6643d27e | bellard | #if 0
|
3948 | 6643d27e | bellard | static int
|
3949 | 6643d27e | bellard | is_newabi (header)
|
3950 | 6643d27e | bellard | Elf_Internal_Ehdr *header;
|
3951 | 6643d27e | bellard | {
|
3952 | 6643d27e | bellard | /* There are no old-style ABIs which use 64-bit ELF. */
|
3953 | 6643d27e | bellard | if (header->e_ident[EI_CLASS] == ELFCLASS64)
|
3954 | 6643d27e | bellard | return 1;
|
3955 | 6643d27e | bellard | |
3956 | 6643d27e | bellard | /* If a 32-bit ELF file, n32 is a new-style ABI. */
|
3957 | 6643d27e | bellard | if ((header->e_flags & EF_MIPS_ABI2) != 0)
|
3958 | 6643d27e | bellard | return 1;
|
3959 | 6643d27e | bellard | |
3960 | 6643d27e | bellard | return 0;
|
3961 | 6643d27e | bellard | }
|
3962 | 6643d27e | bellard | #endif
|
3963 | 6643d27e | bellard | |
3964 | 6643d27e | bellard | /* Print the mips instruction at address MEMADDR in debugged memory,
|
3965 | 6643d27e | bellard | on using INFO. Returns length of the instruction, in bytes, which is
|
3966 | 6643d27e | bellard | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
|
3967 | 6643d27e | bellard | this is little-endian code. */
|
3968 | 6643d27e | bellard | |
3969 | 6643d27e | bellard | static int |
3970 | 52da07d1 | ths | print_insn_mips (bfd_vma memaddr, |
3971 | 52da07d1 | ths | unsigned long int word, |
3972 | 52da07d1 | ths | struct disassemble_info *info)
|
3973 | 6643d27e | bellard | { |
3974 | 52da07d1 | ths | const struct mips_opcode *op; |
3975 | 6643d27e | bellard | static bfd_boolean init = 0; |
3976 | 6643d27e | bellard | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; |
3977 | 6643d27e | bellard | |
3978 | 6643d27e | bellard | /* Build a hash table to shorten the search time. */
|
3979 | 6643d27e | bellard | if (! init)
|
3980 | 6643d27e | bellard | { |
3981 | 6643d27e | bellard | unsigned int i; |
3982 | 6643d27e | bellard | |
3983 | 6643d27e | bellard | for (i = 0; i <= OP_MASK_OP; i++) |
3984 | 6643d27e | bellard | { |
3985 | 6643d27e | bellard | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
|
3986 | 6643d27e | bellard | { |
3987 | 52da07d1 | ths | if (op->pinfo == INSN_MACRO
|
3988 | 52da07d1 | ths | || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) |
3989 | 6643d27e | bellard | continue;
|
3990 | 6643d27e | bellard | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
|
3991 | 6643d27e | bellard | { |
3992 | 6643d27e | bellard | mips_hash[i] = op; |
3993 | 6643d27e | bellard | break;
|
3994 | 6643d27e | bellard | } |
3995 | 6643d27e | bellard | } |
3996 | 6643d27e | bellard | } |
3997 | 6643d27e | bellard | |
3998 | 6643d27e | bellard | init = 1;
|
3999 | 6643d27e | bellard | } |
4000 | 6643d27e | bellard | |
4001 | 6643d27e | bellard | info->bytes_per_chunk = INSNLEN; |
4002 | 6643d27e | bellard | info->display_endian = info->endian; |
4003 | 6643d27e | bellard | info->insn_info_valid = 1;
|
4004 | 6643d27e | bellard | info->branch_delay_insns = 0;
|
4005 | 6643d27e | bellard | info->data_size = 0;
|
4006 | 6643d27e | bellard | info->insn_type = dis_nonbranch; |
4007 | 6643d27e | bellard | info->target = 0;
|
4008 | 6643d27e | bellard | info->target2 = 0;
|
4009 | 6643d27e | bellard | |
4010 | 6643d27e | bellard | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; |
4011 | 6643d27e | bellard | if (op != NULL) |
4012 | 6643d27e | bellard | { |
4013 | 6643d27e | bellard | for (; op < &mips_opcodes[NUMOPCODES]; op++)
|
4014 | 6643d27e | bellard | { |
4015 | 52da07d1 | ths | if (op->pinfo != INSN_MACRO
|
4016 | 52da07d1 | ths | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) |
4017 | 52da07d1 | ths | && (word & op->mask) == op->match) |
4018 | 6643d27e | bellard | { |
4019 | 52da07d1 | ths | const char *d; |
4020 | 6643d27e | bellard | |
4021 | 6643d27e | bellard | /* We always allow to disassemble the jalx instruction. */
|
4022 | 6643d27e | bellard | if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
|
4023 | 6643d27e | bellard | && strcmp (op->name, "jalx"))
|
4024 | 6643d27e | bellard | continue;
|
4025 | 6643d27e | bellard | |
4026 | 6643d27e | bellard | /* Figure out instruction type and branch delay information. */
|
4027 | 6643d27e | bellard | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
4028 | 6643d27e | bellard | { |
4029 | 6643d27e | bellard | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) |
4030 | 6643d27e | bellard | info->insn_type = dis_jsr; |
4031 | 6643d27e | bellard | else
|
4032 | 6643d27e | bellard | info->insn_type = dis_branch; |
4033 | 6643d27e | bellard | info->branch_delay_insns = 1;
|
4034 | 6643d27e | bellard | } |
4035 | 6643d27e | bellard | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY |
4036 | 6643d27e | bellard | | INSN_COND_BRANCH_LIKELY)) != 0)
|
4037 | 6643d27e | bellard | { |
4038 | 6643d27e | bellard | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) |
4039 | 6643d27e | bellard | info->insn_type = dis_condjsr; |
4040 | 6643d27e | bellard | else
|
4041 | 6643d27e | bellard | info->insn_type = dis_condbranch; |
4042 | 6643d27e | bellard | info->branch_delay_insns = 1;
|
4043 | 6643d27e | bellard | } |
4044 | 6643d27e | bellard | else if ((op->pinfo & (INSN_STORE_MEMORY |
4045 | 6643d27e | bellard | | INSN_LOAD_MEMORY_DELAY)) != 0)
|
4046 | 6643d27e | bellard | info->insn_type = dis_dref; |
4047 | 6643d27e | bellard | |
4048 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", op->name);
|
4049 | 6643d27e | bellard | |
4050 | 6643d27e | bellard | d = op->args; |
4051 | 6643d27e | bellard | if (d != NULL && *d != '\0') |
4052 | 6643d27e | bellard | { |
4053 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "\t");
|
4054 | 52da07d1 | ths | print_insn_args (d, word, memaddr, info, op); |
4055 | 6643d27e | bellard | } |
4056 | 6643d27e | bellard | |
4057 | 6643d27e | bellard | return INSNLEN;
|
4058 | 6643d27e | bellard | } |
4059 | 6643d27e | bellard | } |
4060 | 6643d27e | bellard | } |
4061 | 6643d27e | bellard | |
4062 | 6643d27e | bellard | /* Handle undefined instructions. */
|
4063 | 6643d27e | bellard | info->insn_type = dis_noninsn; |
4064 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "0x%lx", word);
|
4065 | 6643d27e | bellard | return INSNLEN;
|
4066 | 6643d27e | bellard | } |
4067 | 6643d27e | bellard | |
4068 | 6643d27e | bellard | /* In an environment where we do not know the symbol type of the
|
4069 | 6643d27e | bellard | instruction we are forced to assume that the low order bit of the
|
4070 | 6643d27e | bellard | instructions' address may mark it as a mips16 instruction. If we
|
4071 | 6643d27e | bellard | are single stepping, or the pc is within the disassembled function,
|
4072 | 6643d27e | bellard | this works. Otherwise, we need a clue. Sometimes. */
|
4073 | 6643d27e | bellard | |
4074 | 6643d27e | bellard | static int |
4075 | 52da07d1 | ths | _print_insn_mips (bfd_vma memaddr, |
4076 | 52da07d1 | ths | struct disassemble_info *info,
|
4077 | 52da07d1 | ths | enum bfd_endian endianness)
|
4078 | 6643d27e | bellard | { |
4079 | 6643d27e | bellard | bfd_byte buffer[INSNLEN]; |
4080 | 6643d27e | bellard | int status;
|
4081 | 6643d27e | bellard | |
4082 | 6643d27e | bellard | set_default_mips_dis_options (info); |
4083 | 6643d27e | bellard | parse_mips_dis_options (info->disassembler_options); |
4084 | 6643d27e | bellard | |
4085 | 6643d27e | bellard | #if 0
|
4086 | 6643d27e | bellard | #if 1
|
4087 | 6643d27e | bellard | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
|
4088 | 6643d27e | bellard | /* Only a few tools will work this way. */
|
4089 | 6643d27e | bellard | if (memaddr & 0x01)
|
4090 | 6643d27e | bellard | return print_insn_mips16 (memaddr, info);
|
4091 | 6643d27e | bellard | #endif
|
4092 | 6643d27e | bellard | |
4093 | 6643d27e | bellard | #if SYMTAB_AVAILABLE
|
4094 | 6643d27e | bellard | if (info->mach == bfd_mach_mips16
|
4095 | 6643d27e | bellard | || (info->flavour == bfd_target_elf_flavour |
4096 | 6643d27e | bellard | && info->symbols != NULL
|
4097 | 6643d27e | bellard | && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other |
4098 | 6643d27e | bellard | == STO_MIPS16))) |
4099 | 6643d27e | bellard | return print_insn_mips16 (memaddr, info);
|
4100 | 6643d27e | bellard | #endif
|
4101 | 6643d27e | bellard | #endif
|
4102 | 6643d27e | bellard | |
4103 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); |
4104 | 6643d27e | bellard | if (status == 0) |
4105 | 6643d27e | bellard | { |
4106 | 6643d27e | bellard | unsigned long insn; |
4107 | 6643d27e | bellard | |
4108 | 6643d27e | bellard | if (endianness == BFD_ENDIAN_BIG)
|
4109 | 6643d27e | bellard | insn = (unsigned long) bfd_getb32 (buffer); |
4110 | 6643d27e | bellard | else
|
4111 | 6643d27e | bellard | insn = (unsigned long) bfd_getl32 (buffer); |
4112 | 6643d27e | bellard | |
4113 | 6643d27e | bellard | return print_insn_mips (memaddr, insn, info);
|
4114 | 6643d27e | bellard | } |
4115 | 6643d27e | bellard | else
|
4116 | 6643d27e | bellard | { |
4117 | 6643d27e | bellard | (*info->memory_error_func) (status, memaddr, info); |
4118 | 6643d27e | bellard | return -1; |
4119 | 6643d27e | bellard | } |
4120 | 6643d27e | bellard | } |
4121 | 6643d27e | bellard | |
4122 | 6643d27e | bellard | int
|
4123 | 52da07d1 | ths | print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
|
4124 | 6643d27e | bellard | { |
4125 | 6643d27e | bellard | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
|
4126 | 6643d27e | bellard | } |
4127 | 6643d27e | bellard | |
4128 | 6643d27e | bellard | int
|
4129 | 52da07d1 | ths | print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
|
4130 | 6643d27e | bellard | { |
4131 | 6643d27e | bellard | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
|
4132 | 6643d27e | bellard | } |
4133 | 6643d27e | bellard | |
4134 | 6643d27e | bellard | /* Disassemble mips16 instructions. */
|
4135 | 6643d27e | bellard | #if 0
|
4136 | 6643d27e | bellard | static int
|
4137 | 52da07d1 | ths | print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
4138 | 6643d27e | bellard | {
|
4139 | 6643d27e | bellard | int status;
|
4140 | 6643d27e | bellard | bfd_byte buffer[2];
|
4141 | 6643d27e | bellard | int length;
|
4142 | 6643d27e | bellard | int insn;
|
4143 | 6643d27e | bellard | bfd_boolean use_extend;
|
4144 | 6643d27e | bellard | int extend = 0;
|
4145 | 6643d27e | bellard | const struct mips_opcode *op, *opend;
|
4146 | 6643d27e | bellard | |
4147 | 6643d27e | bellard | info->bytes_per_chunk = 2;
|
4148 | 6643d27e | bellard | info->display_endian = info->endian;
|
4149 | 6643d27e | bellard | info->insn_info_valid = 1;
|
4150 | 6643d27e | bellard | info->branch_delay_insns = 0;
|
4151 | 6643d27e | bellard | info->data_size = 0;
|
4152 | 6643d27e | bellard | info->insn_type = dis_nonbranch;
|
4153 | 6643d27e | bellard | info->target = 0;
|
4154 | 6643d27e | bellard | info->target2 = 0;
|
4155 | 6643d27e | bellard | |
4156 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
4157 | 6643d27e | bellard | if (status != 0)
|
4158 | 6643d27e | bellard | {
|
4159 | 6643d27e | bellard | (*info->memory_error_func) (status, memaddr, info);
|
4160 | 6643d27e | bellard | return -1;
|
4161 | 6643d27e | bellard | }
|
4162 | 6643d27e | bellard | |
4163 | 6643d27e | bellard | length = 2;
|
4164 | 6643d27e | bellard | |
4165 | 6643d27e | bellard | if (info->endian == BFD_ENDIAN_BIG)
|
4166 | 6643d27e | bellard | insn = bfd_getb16 (buffer);
|
4167 | 6643d27e | bellard | else
|
4168 | 6643d27e | bellard | insn = bfd_getl16 (buffer);
|
4169 | 6643d27e | bellard | |
4170 | 6643d27e | bellard | /* Handle the extend opcode specially. */
|
4171 | 6643d27e | bellard | use_extend = FALSE;
|
4172 | 6643d27e | bellard | if ((insn & 0xf800) == 0xf000)
|
4173 | 6643d27e | bellard | {
|
4174 | 6643d27e | bellard | use_extend = TRUE;
|
4175 | 6643d27e | bellard | extend = insn & 0x7ff;
|
4176 | 6643d27e | bellard | |
4177 | 6643d27e | bellard | memaddr += 2;
|
4178 | 6643d27e | bellard | |
4179 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
4180 | 6643d27e | bellard | if (status != 0)
|
4181 | 6643d27e | bellard | {
|
4182 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "extend 0x%x",
|
4183 | 6643d27e | bellard | (unsigned int) extend);
|
4184 | 6643d27e | bellard | (*info->memory_error_func) (status, memaddr, info);
|
4185 | 6643d27e | bellard | return -1;
|
4186 | 6643d27e | bellard | }
|
4187 | 6643d27e | bellard | |
4188 | 6643d27e | bellard | if (info->endian == BFD_ENDIAN_BIG)
|
4189 | 6643d27e | bellard | insn = bfd_getb16 (buffer);
|
4190 | 6643d27e | bellard | else
|
4191 | 6643d27e | bellard | insn = bfd_getl16 (buffer);
|
4192 | 6643d27e | bellard | |
4193 | 6643d27e | bellard | /* Check for an extend opcode followed by an extend opcode. */
|
4194 | 6643d27e | bellard | if ((insn & 0xf800) == 0xf000)
|
4195 | 6643d27e | bellard | {
|
4196 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "extend 0x%x",
|
4197 | 6643d27e | bellard | (unsigned int) extend);
|
4198 | 6643d27e | bellard | info->insn_type = dis_noninsn;
|
4199 | 6643d27e | bellard | return length;
|
4200 | 6643d27e | bellard | }
|
4201 | 6643d27e | bellard | |
4202 | 6643d27e | bellard | length += 2;
|
4203 | 6643d27e | bellard | }
|
4204 | 6643d27e | bellard | |
4205 | 6643d27e | bellard | /* FIXME: Should probably use a hash table on the major opcode here. */
|
4206 | 6643d27e | bellard | |
4207 | 6643d27e | bellard | opend = mips16_opcodes + bfd_mips16_num_opcodes;
|
4208 | 6643d27e | bellard | for (op = mips16_opcodes; op < opend; op++)
|
4209 | 6643d27e | bellard | {
|
4210 | 52da07d1 | ths | if (op->pinfo != INSN_MACRO
|
4211 | 52da07d1 | ths | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
|
4212 | 52da07d1 | ths | && (insn & op->mask) == op->match)
|
4213 | 6643d27e | bellard | {
|
4214 | 6643d27e | bellard | const char *s;
|
4215 | 6643d27e | bellard | |
4216 | 6643d27e | bellard | if (strchr (op->args, 'a') != NULL)
|
4217 | 6643d27e | bellard | {
|
4218 | 6643d27e | bellard | if (use_extend)
|
4219 | 6643d27e | bellard | {
|
4220 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "extend 0x%x",
|
4221 | 6643d27e | bellard | (unsigned int) extend);
|
4222 | 6643d27e | bellard | info->insn_type = dis_noninsn;
|
4223 | 6643d27e | bellard | return length - 2;
|
4224 | 6643d27e | bellard | }
|
4225 | 6643d27e | bellard | |
4226 | 6643d27e | bellard | use_extend = FALSE;
|
4227 | 6643d27e | bellard | |
4228 | 6643d27e | bellard | memaddr += 2;
|
4229 | 6643d27e | bellard | |
4230 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr, buffer, 2,
|
4231 | 6643d27e | bellard | info);
|
4232 | 6643d27e | bellard | if (status == 0)
|
4233 | 6643d27e | bellard | {
|
4234 | 6643d27e | bellard | use_extend = TRUE;
|
4235 | 6643d27e | bellard | if (info->endian == BFD_ENDIAN_BIG)
|
4236 | 6643d27e | bellard | extend = bfd_getb16 (buffer);
|
4237 | 6643d27e | bellard | else
|
4238 | 6643d27e | bellard | extend = bfd_getl16 (buffer);
|
4239 | 6643d27e | bellard | length += 2;
|
4240 | 6643d27e | bellard | }
|
4241 | 6643d27e | bellard | }
|
4242 | 6643d27e | bellard | |
4243 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", op->name);
|
4244 | 6643d27e | bellard | if (op->args[0] != '\0')
|
4245 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "\t");
|
4246 | 6643d27e | bellard | |
4247 | 6643d27e | bellard | for (s = op->args; *s != '\0'; s++)
|
4248 | 6643d27e | bellard | {
|
4249 | 6643d27e | bellard | if (*s == ','
|
4250 | 6643d27e | bellard | && s[1] == 'w'
|
4251 | 6643d27e | bellard | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
|
4252 | 6643d27e | bellard | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
|
4253 | 6643d27e | bellard | {
|
4254 | 6643d27e | bellard | /* Skip the register and the comma. */
|
4255 | 6643d27e | bellard | ++s;
|
4256 | 6643d27e | bellard | continue;
|
4257 | 6643d27e | bellard | }
|
4258 | 6643d27e | bellard | if (*s == ','
|
4259 | 6643d27e | bellard | && s[1] == 'v'
|
4260 | 6643d27e | bellard | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
|
4261 | 6643d27e | bellard | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
|
4262 | 6643d27e | bellard | {
|
4263 | 6643d27e | bellard | /* Skip the register and the comma. */
|
4264 | 6643d27e | bellard | ++s;
|
4265 | 6643d27e | bellard | continue;
|
4266 | 6643d27e | bellard | }
|
4267 | 6643d27e | bellard | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
|
4268 | 6643d27e | bellard | info);
|
4269 | 6643d27e | bellard | }
|
4270 | 6643d27e | bellard | |
4271 | 6643d27e | bellard | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
|
4272 | 6643d27e | bellard | {
|
4273 | 6643d27e | bellard | info->branch_delay_insns = 1;
|
4274 | 6643d27e | bellard | if (info->insn_type != dis_jsr)
|
4275 | 6643d27e | bellard | info->insn_type = dis_branch;
|
4276 | 6643d27e | bellard | }
|
4277 | 6643d27e | bellard | |
4278 | 6643d27e | bellard | return length;
|
4279 | 6643d27e | bellard | }
|
4280 | 6643d27e | bellard | }
|
4281 | 6643d27e | bellard | |
4282 | 6643d27e | bellard | if (use_extend)
|
4283 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
|
4284 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "0x%x", insn);
|
4285 | 6643d27e | bellard | info->insn_type = dis_noninsn;
|
4286 | 6643d27e | bellard | |
4287 | 6643d27e | bellard | return length;
|
4288 | 6643d27e | bellard | }
|
4289 | 6643d27e | bellard | |
4290 | 6643d27e | bellard | /* Disassemble an operand for a mips16 instruction. */
|
4291 | 6643d27e | bellard | |
4292 | 6643d27e | bellard | static void
|
4293 | 52da07d1 | ths | print_mips16_insn_arg (char type,
|
4294 | 52da07d1 | ths | const struct mips_opcode *op,
|
4295 | 52da07d1 | ths | int l,
|
4296 | 52da07d1 | ths | bfd_boolean use_extend,
|
4297 | 52da07d1 | ths | int extend,
|
4298 | 52da07d1 | ths | bfd_vma memaddr,
|
4299 | 52da07d1 | ths | struct disassemble_info *info)
|
4300 | 6643d27e | bellard | {
|
4301 | 6643d27e | bellard | switch (type)
|
4302 | 6643d27e | bellard | {
|
4303 | 6643d27e | bellard | case ',':
|
4304 | 6643d27e | bellard | case '(':
|
4305 | 6643d27e | bellard | case ')':
|
4306 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%c", type);
|
4307 | 6643d27e | bellard | break;
|
4308 | 6643d27e | bellard | |
4309 | 6643d27e | bellard | case 'y':
|
4310 | 6643d27e | bellard | case 'w':
|
4311 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4312 | 52da07d1 | ths | mips16_reg_names(((l >> MIPS16OP_SH_RY)
|
4313 | 52da07d1 | ths | & MIPS16OP_MASK_RY)));
|
4314 | 6643d27e | bellard | break;
|
4315 | 6643d27e | bellard | |
4316 | 6643d27e | bellard | case 'x':
|
4317 | 6643d27e | bellard | case 'v':
|
4318 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4319 | 52da07d1 | ths | mips16_reg_names(((l >> MIPS16OP_SH_RX)
|
4320 | 52da07d1 | ths | & MIPS16OP_MASK_RX)));
|
4321 | 6643d27e | bellard | break;
|
4322 | 6643d27e | bellard | |
4323 | 6643d27e | bellard | case 'z':
|
4324 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4325 | 52da07d1 | ths | mips16_reg_names(((l >> MIPS16OP_SH_RZ)
|
4326 | 52da07d1 | ths | & MIPS16OP_MASK_RZ)));
|
4327 | 6643d27e | bellard | break;
|
4328 | 6643d27e | bellard | |
4329 | 6643d27e | bellard | case 'Z':
|
4330 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4331 | 52da07d1 | ths | mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
|
4332 | 52da07d1 | ths | & MIPS16OP_MASK_MOVE32Z)));
|
4333 | 6643d27e | bellard | break;
|
4334 | 6643d27e | bellard | |
4335 | 6643d27e | bellard | case '0':
|
4336 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
|
4337 | 6643d27e | bellard | break;
|
4338 | 6643d27e | bellard | |
4339 | 6643d27e | bellard | case 'S':
|
4340 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
|
4341 | 6643d27e | bellard | break;
|
4342 | 6643d27e | bellard | |
4343 | 6643d27e | bellard | case 'P':
|
4344 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "$pc");
|
4345 | 6643d27e | bellard | break;
|
4346 | 6643d27e | bellard | |
4347 | 6643d27e | bellard | case 'R':
|
4348 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
|
4349 | 6643d27e | bellard | break;
|
4350 | 6643d27e | bellard | |
4351 | 6643d27e | bellard | case 'X':
|
4352 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4353 | 6643d27e | bellard | mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
|
4354 | 6643d27e | bellard | & MIPS16OP_MASK_REGR32)]);
|
4355 | 6643d27e | bellard | break;
|
4356 | 6643d27e | bellard | |
4357 | 6643d27e | bellard | case 'Y':
|
4358 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s",
|
4359 | 6643d27e | bellard | mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
|
4360 | 6643d27e | bellard | break;
|
4361 | 6643d27e | bellard | |
4362 | 6643d27e | bellard | case '<':
|
4363 | 6643d27e | bellard | case '>':
|
4364 | 6643d27e | bellard | case '[':
|
4365 | 6643d27e | bellard | case ']':
|
4366 | 6643d27e | bellard | case '4':
|
4367 | 6643d27e | bellard | case '5':
|
4368 | 6643d27e | bellard | case 'H':
|
4369 | 6643d27e | bellard | case 'W':
|
4370 | 6643d27e | bellard | case 'D':
|
4371 | 6643d27e | bellard | case 'j':
|
4372 | 6643d27e | bellard | case '6':
|
4373 | 6643d27e | bellard | case '8':
|
4374 | 6643d27e | bellard | case 'V':
|
4375 | 6643d27e | bellard | case 'C':
|
4376 | 6643d27e | bellard | case 'U':
|
4377 | 6643d27e | bellard | case 'k':
|
4378 | 6643d27e | bellard | case 'K':
|
4379 | 6643d27e | bellard | case 'p':
|
4380 | 6643d27e | bellard | case 'q':
|
4381 | 6643d27e | bellard | case 'A':
|
4382 | 6643d27e | bellard | case 'B':
|
4383 | 6643d27e | bellard | case 'E':
|
4384 | 6643d27e | bellard | {
|
4385 | 6643d27e | bellard | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
|
4386 | 6643d27e | bellard | |
4387 | 6643d27e | bellard | shift = 0;
|
4388 | 6643d27e | bellard | signedp = 0;
|
4389 | 6643d27e | bellard | extbits = 16;
|
4390 | 6643d27e | bellard | pcrel = 0;
|
4391 | 6643d27e | bellard | extu = 0;
|
4392 | 6643d27e | bellard | branch = 0;
|
4393 | 6643d27e | bellard | switch (type)
|
4394 | 6643d27e | bellard | {
|
4395 | 6643d27e | bellard | case '<':
|
4396 | 6643d27e | bellard | nbits = 3;
|
4397 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
|
4398 | 6643d27e | bellard | extbits = 5;
|
4399 | 6643d27e | bellard | extu = 1;
|
4400 | 6643d27e | bellard | break;
|
4401 | 6643d27e | bellard | case '>':
|
4402 | 6643d27e | bellard | nbits = 3;
|
4403 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
|
4404 | 6643d27e | bellard | extbits = 5;
|
4405 | 6643d27e | bellard | extu = 1;
|
4406 | 6643d27e | bellard | break;
|
4407 | 6643d27e | bellard | case '[':
|
4408 | 6643d27e | bellard | nbits = 3;
|
4409 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
|
4410 | 6643d27e | bellard | extbits = 6;
|
4411 | 6643d27e | bellard | extu = 1;
|
4412 | 6643d27e | bellard | break;
|
4413 | 6643d27e | bellard | case ']':
|
4414 | 6643d27e | bellard | nbits = 3;
|
4415 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
|
4416 | 6643d27e | bellard | extbits = 6;
|
4417 | 6643d27e | bellard | extu = 1;
|
4418 | 6643d27e | bellard | break;
|
4419 | 6643d27e | bellard | case '4':
|
4420 | 6643d27e | bellard | nbits = 4;
|
4421 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
|
4422 | 6643d27e | bellard | signedp = 1;
|
4423 | 6643d27e | bellard | extbits = 15;
|
4424 | 6643d27e | bellard | break;
|
4425 | 6643d27e | bellard | case '5':
|
4426 | 6643d27e | bellard | nbits = 5;
|
4427 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4428 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4429 | 6643d27e | bellard | info->data_size = 1;
|
4430 | 6643d27e | bellard | break;
|
4431 | 6643d27e | bellard | case 'H':
|
4432 | 6643d27e | bellard | nbits = 5;
|
4433 | 6643d27e | bellard | shift = 1;
|
4434 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4435 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4436 | 6643d27e | bellard | info->data_size = 2;
|
4437 | 6643d27e | bellard | break;
|
4438 | 6643d27e | bellard | case 'W':
|
4439 | 6643d27e | bellard | nbits = 5;
|
4440 | 6643d27e | bellard | shift = 2;
|
4441 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4442 | 6643d27e | bellard | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
|
4443 | 6643d27e | bellard | && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
|
4444 | 6643d27e | bellard | {
|
4445 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4446 | 6643d27e | bellard | info->data_size = 4;
|
4447 | 6643d27e | bellard | }
|
4448 | 6643d27e | bellard | break;
|
4449 | 6643d27e | bellard | case 'D':
|
4450 | 6643d27e | bellard | nbits = 5;
|
4451 | 6643d27e | bellard | shift = 3;
|
4452 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4453 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4454 | 6643d27e | bellard | info->data_size = 8;
|
4455 | 6643d27e | bellard | break;
|
4456 | 6643d27e | bellard | case 'j':
|
4457 | 6643d27e | bellard | nbits = 5;
|
4458 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4459 | 6643d27e | bellard | signedp = 1;
|
4460 | 6643d27e | bellard | break;
|
4461 | 6643d27e | bellard | case '6':
|
4462 | 6643d27e | bellard | nbits = 6;
|
4463 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
|
4464 | 6643d27e | bellard | break;
|
4465 | 6643d27e | bellard | case '8':
|
4466 | 6643d27e | bellard | nbits = 8;
|
4467 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4468 | 6643d27e | bellard | break;
|
4469 | 6643d27e | bellard | case 'V':
|
4470 | 6643d27e | bellard | nbits = 8;
|
4471 | 6643d27e | bellard | shift = 2;
|
4472 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4473 | 6643d27e | bellard | /* FIXME: This might be lw, or it might be addiu to $sp or
|
4474 | 6643d27e | bellard | $pc. We assume it's load. */
|
4475 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4476 | 6643d27e | bellard | info->data_size = 4;
|
4477 | 6643d27e | bellard | break;
|
4478 | 6643d27e | bellard | case 'C':
|
4479 | 6643d27e | bellard | nbits = 8;
|
4480 | 6643d27e | bellard | shift = 3;
|
4481 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4482 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4483 | 6643d27e | bellard | info->data_size = 8;
|
4484 | 6643d27e | bellard | break;
|
4485 | 6643d27e | bellard | case 'U':
|
4486 | 6643d27e | bellard | nbits = 8;
|
4487 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4488 | 6643d27e | bellard | extu = 1;
|
4489 | 6643d27e | bellard | break;
|
4490 | 6643d27e | bellard | case 'k':
|
4491 | 6643d27e | bellard | nbits = 8;
|
4492 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4493 | 6643d27e | bellard | signedp = 1;
|
4494 | 6643d27e | bellard | break;
|
4495 | 6643d27e | bellard | case 'K':
|
4496 | 6643d27e | bellard | nbits = 8;
|
4497 | 6643d27e | bellard | shift = 3;
|
4498 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4499 | 6643d27e | bellard | signedp = 1;
|
4500 | 6643d27e | bellard | break;
|
4501 | 6643d27e | bellard | case 'p':
|
4502 | 6643d27e | bellard | nbits = 8;
|
4503 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4504 | 6643d27e | bellard | signedp = 1;
|
4505 | 6643d27e | bellard | pcrel = 1;
|
4506 | 6643d27e | bellard | branch = 1;
|
4507 | 6643d27e | bellard | info->insn_type = dis_condbranch;
|
4508 | 6643d27e | bellard | break;
|
4509 | 6643d27e | bellard | case 'q':
|
4510 | 6643d27e | bellard | nbits = 11;
|
4511 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
|
4512 | 6643d27e | bellard | signedp = 1;
|
4513 | 6643d27e | bellard | pcrel = 1;
|
4514 | 6643d27e | bellard | branch = 1;
|
4515 | 6643d27e | bellard | info->insn_type = dis_branch;
|
4516 | 6643d27e | bellard | break;
|
4517 | 6643d27e | bellard | case 'A':
|
4518 | 6643d27e | bellard | nbits = 8;
|
4519 | 6643d27e | bellard | shift = 2;
|
4520 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
|
4521 | 6643d27e | bellard | pcrel = 1;
|
4522 | 6643d27e | bellard | /* FIXME: This can be lw or la. We assume it is lw. */
|
4523 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4524 | 6643d27e | bellard | info->data_size = 4;
|
4525 | 6643d27e | bellard | break;
|
4526 | 6643d27e | bellard | case 'B':
|
4527 | 6643d27e | bellard | nbits = 5;
|
4528 | 6643d27e | bellard | shift = 3;
|
4529 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4530 | 6643d27e | bellard | pcrel = 1;
|
4531 | 6643d27e | bellard | info->insn_type = dis_dref;
|
4532 | 6643d27e | bellard | info->data_size = 8;
|
4533 | 6643d27e | bellard | break;
|
4534 | 6643d27e | bellard | case 'E':
|
4535 | 6643d27e | bellard | nbits = 5;
|
4536 | 6643d27e | bellard | shift = 2;
|
4537 | 6643d27e | bellard | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
|
4538 | 6643d27e | bellard | pcrel = 1;
|
4539 | 6643d27e | bellard | break;
|
4540 | 6643d27e | bellard | default:
|
4541 | 6643d27e | bellard | abort ();
|
4542 | 6643d27e | bellard | }
|
4543 | 6643d27e | bellard | |
4544 | 6643d27e | bellard | if (! use_extend)
|
4545 | 6643d27e | bellard | {
|
4546 | 6643d27e | bellard | if (signedp && immed >= (1 << (nbits - 1)))
|
4547 | 6643d27e | bellard | immed -= 1 << nbits;
|
4548 | 6643d27e | bellard | immed <<= shift;
|
4549 | 6643d27e | bellard | if ((type == '<' || type == '>' || type == '[' || type == ']')
|
4550 | 6643d27e | bellard | && immed == 0)
|
4551 | 6643d27e | bellard | immed = 8;
|
4552 | 6643d27e | bellard | }
|
4553 | 6643d27e | bellard | else
|
4554 | 6643d27e | bellard | {
|
4555 | 6643d27e | bellard | if (extbits == 16)
|
4556 | 6643d27e | bellard | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
|
4557 | 6643d27e | bellard | else if (extbits == 15)
|
4558 | 6643d27e | bellard | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
|
4559 | 6643d27e | bellard | else
|
4560 | 6643d27e | bellard | immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
|
4561 | 6643d27e | bellard | immed &= (1 << extbits) - 1;
|
4562 | 6643d27e | bellard | if (! extu && immed >= (1 << (extbits - 1)))
|
4563 | 6643d27e | bellard | immed -= 1 << extbits;
|
4564 | 6643d27e | bellard | }
|
4565 | 6643d27e | bellard | |
4566 | 6643d27e | bellard | if (! pcrel)
|
4567 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%d", immed);
|
4568 | 6643d27e | bellard | else
|
4569 | 6643d27e | bellard | {
|
4570 | 6643d27e | bellard | bfd_vma baseaddr;
|
4571 | 6643d27e | bellard | |
4572 | 6643d27e | bellard | if (branch)
|
4573 | 6643d27e | bellard | {
|
4574 | 6643d27e | bellard | immed *= 2;
|
4575 | 6643d27e | bellard | baseaddr = memaddr + 2;
|
4576 | 6643d27e | bellard | }
|
4577 | 6643d27e | bellard | else if (use_extend)
|
4578 | 6643d27e | bellard | baseaddr = memaddr - 2;
|
4579 | 6643d27e | bellard | else
|
4580 | 6643d27e | bellard | {
|
4581 | 6643d27e | bellard | int status;
|
4582 | 6643d27e | bellard | bfd_byte buffer[2];
|
4583 | 6643d27e | bellard | |
4584 | 6643d27e | bellard | baseaddr = memaddr;
|
4585 | 6643d27e | bellard | |
4586 | 6643d27e | bellard | /* If this instruction is in the delay slot of a jr
|
4587 | 6643d27e | bellard | instruction, the base address is the address of the
|
4588 | 6643d27e | bellard | jr instruction. If it is in the delay slot of jalr
|
4589 | 6643d27e | bellard | instruction, the base address is the address of the
|
4590 | 6643d27e | bellard | jalr instruction. This test is unreliable: we have
|
4591 | 6643d27e | bellard | no way of knowing whether the previous word is
|
4592 | 6643d27e | bellard | instruction or data. */
|
4593 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
|
4594 | 6643d27e | bellard | info);
|
4595 | 6643d27e | bellard | if (status == 0
|
4596 | 6643d27e | bellard | && (((info->endian == BFD_ENDIAN_BIG
|
4597 | 6643d27e | bellard | ? bfd_getb16 (buffer)
|
4598 | 6643d27e | bellard | : bfd_getl16 (buffer))
|
4599 | 6643d27e | bellard | & 0xf800) == 0x1800))
|
4600 | 6643d27e | bellard | baseaddr = memaddr - 4;
|
4601 | 6643d27e | bellard | else
|
4602 | 6643d27e | bellard | {
|
4603 | 6643d27e | bellard | status = (*info->read_memory_func) (memaddr - 2, buffer,
|
4604 | 6643d27e | bellard | 2, info);
|
4605 | 6643d27e | bellard | if (status == 0
|
4606 | 6643d27e | bellard | && (((info->endian == BFD_ENDIAN_BIG
|
4607 | 6643d27e | bellard | ? bfd_getb16 (buffer)
|
4608 | 6643d27e | bellard | : bfd_getl16 (buffer))
|
4609 | 6643d27e | bellard | & 0xf81f) == 0xe800))
|
4610 | 6643d27e | bellard | baseaddr = memaddr - 2;
|
4611 | 6643d27e | bellard | }
|
4612 | 6643d27e | bellard | }
|
4613 | 6643d27e | bellard | info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
|
4614 | 52da07d1 | ths | if (pcrel && branch
|
4615 | 52da07d1 | ths | && info->flavour == bfd_target_unknown_flavour)
|
4616 | 52da07d1 | ths | /* For gdb disassembler, maintain odd address. */
|
4617 | 52da07d1 | ths | info->target |= 1;
|
4618 | 6643d27e | bellard | (*info->print_address_func) (info->target, info);
|
4619 | 6643d27e | bellard | }
|
4620 | 6643d27e | bellard | }
|
4621 | 6643d27e | bellard | break;
|
4622 | 6643d27e | bellard | |
4623 | 6643d27e | bellard | case 'a':
|
4624 | 52da07d1 | ths | {
|
4625 | 52da07d1 | ths | int jalx = l & 0x400;
|
4626 | 52da07d1 | ths | |
4627 | 52da07d1 | ths | if (! use_extend)
|
4628 | 52da07d1 | ths | extend = 0;
|
4629 | 52da07d1 | ths | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
|
4630 | 52da07d1 | ths | if (!jalx && info->flavour == bfd_target_unknown_flavour)
|
4631 | 52da07d1 | ths | /* For gdb disassembler, maintain odd address. */
|
4632 | 52da07d1 | ths | l |= 1;
|
4633 | 52da07d1 | ths | }
|
4634 | 6643d27e | bellard | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
|
4635 | 6643d27e | bellard | (*info->print_address_func) (info->target, info);
|
4636 | 6643d27e | bellard | info->insn_type = dis_jsr;
|
4637 | 6643d27e | bellard | info->branch_delay_insns = 1;
|
4638 | 6643d27e | bellard | break;
|
4639 | 6643d27e | bellard | |
4640 | 6643d27e | bellard | case 'l':
|
4641 | 6643d27e | bellard | case 'L':
|
4642 | 6643d27e | bellard | {
|
4643 | 6643d27e | bellard | int need_comma, amask, smask;
|
4644 | 6643d27e | bellard | |
4645 | 6643d27e | bellard | need_comma = 0;
|
4646 | 6643d27e | bellard | |
4647 | 6643d27e | bellard | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
|
4648 | 6643d27e | bellard | |
4649 | 6643d27e | bellard | amask = (l >> 3) & 7;
|
4650 | 6643d27e | bellard | |
4651 | 6643d27e | bellard | if (amask > 0 && amask < 5)
|
4652 | 6643d27e | bellard | {
|
4653 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
|
4654 | 6643d27e | bellard | if (amask > 1)
|
4655 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "-%s",
|
4656 | 6643d27e | bellard | mips_gpr_names[amask + 3]);
|
4657 | 6643d27e | bellard | need_comma = 1;
|
4658 | 6643d27e | bellard | }
|
4659 | 6643d27e | bellard | |
4660 | 6643d27e | bellard | smask = (l >> 1) & 3;
|
4661 | 6643d27e | bellard | if (smask == 3)
|
4662 | 6643d27e | bellard | {
|
4663 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s??",
|
4664 | 6643d27e | bellard | need_comma ? "," : "");
|
4665 | 6643d27e | bellard | need_comma = 1;
|
4666 | 6643d27e | bellard | }
|
4667 | 6643d27e | bellard | else if (smask > 0)
|
4668 | 6643d27e | bellard | {
|
4669 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s%s",
|
4670 | 6643d27e | bellard | need_comma ? "," : "",
|
4671 | 6643d27e | bellard | mips_gpr_names[16]);
|
4672 | 6643d27e | bellard | if (smask > 1)
|
4673 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "-%s",
|
4674 | 6643d27e | bellard | mips_gpr_names[smask + 15]);
|
4675 | 6643d27e | bellard | need_comma = 1;
|
4676 | 6643d27e | bellard | }
|
4677 | 6643d27e | bellard | |
4678 | 6643d27e | bellard | if (l & 1)
|
4679 | 6643d27e | bellard | {
|
4680 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s%s",
|
4681 | 6643d27e | bellard | need_comma ? "," : "",
|
4682 | 6643d27e | bellard | mips_gpr_names[31]);
|
4683 | 6643d27e | bellard | need_comma = 1;
|
4684 | 6643d27e | bellard | }
|
4685 | 6643d27e | bellard | |
4686 | 6643d27e | bellard | if (amask == 5 || amask == 6)
|
4687 | 6643d27e | bellard | {
|
4688 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "%s$f0",
|
4689 | 6643d27e | bellard | need_comma ? "," : "");
|
4690 | 6643d27e | bellard | if (amask == 6)
|
4691 | 6643d27e | bellard | (*info->fprintf_func) (info->stream, "-$f1");
|
4692 | 6643d27e | bellard | }
|
4693 | 6643d27e | bellard | }
|
4694 | 6643d27e | bellard | break;
|
4695 | 6643d27e | bellard | |
4696 | 52da07d1 | ths | case 'm':
|
4697 | 52da07d1 | ths | case 'M':
|
4698 | 52da07d1 | ths | /* MIPS16e save/restore. */
|
4699 | 52da07d1 | ths | {
|
4700 | 52da07d1 | ths | int need_comma = 0;
|
4701 | 52da07d1 | ths | int amask, args, statics;
|
4702 | 52da07d1 | ths | int nsreg, smask;
|
4703 | 52da07d1 | ths | int framesz;
|
4704 | 52da07d1 | ths | int i, j;
|
4705 | 52da07d1 | ths | |
4706 | 52da07d1 | ths | l = l & 0x7f;
|
4707 | 52da07d1 | ths | if (use_extend)
|
4708 | 52da07d1 | ths | l |= extend << 16;
|
4709 | 52da07d1 | ths | |
4710 | 52da07d1 | ths | amask = (l >> 16) & 0xf;
|
4711 | 52da07d1 | ths | if (amask == MIPS16_ALL_ARGS)
|
4712 | 52da07d1 | ths | {
|
4713 | 52da07d1 | ths | args = 4;
|
4714 | 52da07d1 | ths | statics = 0;
|
4715 | 52da07d1 | ths | }
|
4716 | 52da07d1 | ths | else if (amask == MIPS16_ALL_STATICS)
|
4717 | 52da07d1 | ths | {
|
4718 | 52da07d1 | ths | args = 0;
|
4719 | 52da07d1 | ths | statics = 4;
|
4720 | 52da07d1 | ths | }
|
4721 | 52da07d1 | ths | else
|
4722 | 52da07d1 | ths | {
|
4723 | 52da07d1 | ths | args = amask >> 2;
|
4724 | 52da07d1 | ths | statics = amask & 3;
|
4725 | 52da07d1 | ths | }
|
4726 | 52da07d1 | ths | |
4727 | 52da07d1 | ths | if (args > 0) {
|
4728 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
|
4729 | 52da07d1 | ths | if (args > 1)
|
4730 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "-%s",
|
4731 | 52da07d1 | ths | mips_gpr_names[4 + args - 1]);
|
4732 | 52da07d1 | ths | need_comma = 1;
|
4733 | 52da07d1 | ths | }
|
4734 | 52da07d1 | ths | |
4735 | 52da07d1 | ths | framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
|
4736 | 52da07d1 | ths | if (framesz == 0 && !use_extend)
|
4737 | 52da07d1 | ths | framesz = 128;
|
4738 | 52da07d1 | ths | |
4739 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "%s%d",
|
4740 | 52da07d1 | ths | need_comma ? "," : "",
|
4741 | 52da07d1 | ths | framesz);
|
4742 | 52da07d1 | ths | |
4743 | 52da07d1 | ths | if (l & 0x40) /* $ra */
|
4744 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
|
4745 | 52da07d1 | ths | |
4746 | 52da07d1 | ths | nsreg = (l >> 24) & 0x7;
|
4747 | 52da07d1 | ths | smask = 0;
|
4748 | 52da07d1 | ths | if (l & 0x20) /* $s0 */
|
4749 | 52da07d1 | ths | smask |= 1 << 0;
|
4750 | 52da07d1 | ths | if (l & 0x10) /* $s1 */
|
4751 | 52da07d1 | ths | smask |= 1 << 1;
|
4752 | 52da07d1 | ths | if (nsreg > 0) /* $s2-$s8 */
|
4753 | 52da07d1 | ths | smask |= ((1 << nsreg) - 1) << 2;
|
4754 | 52da07d1 | ths | |
4755 | 52da07d1 | ths | /* Find first set static reg bit. */
|
4756 | 52da07d1 | ths | for (i = 0; i < 9; i++)
|
4757 | 52da07d1 | ths | {
|
4758 | 52da07d1 | ths | if (smask & (1 << i))
|
4759 | 52da07d1 | ths | {
|
4760 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, ",%s",
|
4761 | 52da07d1 | ths | mips_gpr_names[i == 8 ? 30 : (16 + i)]);
|
4762 | 52da07d1 | ths | /* Skip over string of set bits. */
|
4763 | 52da07d1 | ths | for (j = i; smask & (2 << j); j++)
|
4764 | 52da07d1 | ths | continue;
|
4765 | 52da07d1 | ths | if (j > i)
|
4766 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, "-%s",
|
4767 | 52da07d1 | ths | mips_gpr_names[j == 8 ? 30 : (16 + j)]);
|
4768 | 52da07d1 | ths | i = j + 1;
|
4769 | 52da07d1 | ths | }
|
4770 | 52da07d1 | ths | }
|
4771 | 52da07d1 | ths | |
4772 | 52da07d1 | ths | /* Statics $ax - $a3. */
|
4773 | 52da07d1 | ths | if (statics == 1)
|
4774 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
|
4775 | 52da07d1 | ths | else if (statics > 0)
|
4776 | 52da07d1 | ths | (*info->fprintf_func) (info->stream, ",%s-%s",
|
4777 | 52da07d1 | ths | mips_gpr_names[7 - statics + 1],
|
4778 | 52da07d1 | ths | mips_gpr_names[7]);
|
4779 | 52da07d1 | ths | }
|
4780 | 52da07d1 | ths | break;
|
4781 | 52da07d1 | ths | |
4782 | 6643d27e | bellard | default:
|
4783 | 6643d27e | bellard | /* xgettext:c-format */
|
4784 | 6643d27e | bellard | (*info->fprintf_func)
|
4785 | 6643d27e | bellard | (info->stream,
|
4786 | 6643d27e | bellard | _("# internal disassembler error, unrecognised modifier (%c)"),
|
4787 | 6643d27e | bellard | type);
|
4788 | 6643d27e | bellard | abort ();
|
4789 | 6643d27e | bellard | }
|
4790 | 6643d27e | bellard | }
|
4791 | 6643d27e | bellard | |
4792 | 6643d27e | bellard | void
|
4793 | 52da07d1 | ths | print_mips_disassembler_options (FILE *stream)
|
4794 | 6643d27e | bellard | {
|
4795 | 6643d27e | bellard | unsigned int i;
|
4796 | 6643d27e | bellard | |
4797 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4798 | 6643d27e | bellard | The following MIPS specific disassembler options are supported for use\n\
|
4799 | 6643d27e | bellard | with the -M switch (multiple options should be separated by commas):\n"));
|
4800 | 6643d27e | bellard | |
4801 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4802 | 6643d27e | bellard | gpr-names=ABI Print GPR names according to specified ABI.\n\
|
4803 | 6643d27e | bellard | Default: based on binary being disassembled.\n"));
|
4804 | 6643d27e | bellard | |
4805 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4806 | 6643d27e | bellard | fpr-names=ABI Print FPR names according to specified ABI.\n\
|
4807 | 6643d27e | bellard | Default: numeric.\n"));
|
4808 | 6643d27e | bellard | |
4809 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4810 | 6643d27e | bellard | cp0-names=ARCH Print CP0 register names according to\n\
|
4811 | 6643d27e | bellard | specified architecture.\n\
|
4812 | 6643d27e | bellard | Default: based on binary being disassembled.\n"));
|
4813 | 6643d27e | bellard | |
4814 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4815 | 6643d27e | bellard | hwr-names=ARCH Print HWR names according to specified \n\
|
4816 | 6643d27e | bellard | architecture.\n\
|
4817 | 6643d27e | bellard | Default: based on binary being disassembled.\n"));
|
4818 | 6643d27e | bellard | |
4819 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4820 | 6643d27e | bellard | reg-names=ABI Print GPR and FPR names according to\n\
|
4821 | 6643d27e | bellard | specified ABI.\n"));
|
4822 | 6643d27e | bellard | |
4823 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4824 | 6643d27e | bellard | reg-names=ARCH Print CP0 register and HWR names according to\n\
|
4825 | 6643d27e | bellard | specified architecture.\n"));
|
4826 | 6643d27e | bellard | |
4827 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4828 | 6643d27e | bellard | For the options above, the following values are supported for \"ABI\":\n\
|
4829 | 6643d27e | bellard | "));
|
4830 | 6643d27e | bellard | for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
|
4831 | 6643d27e | bellard | fprintf (stream, " %s", mips_abi_choices[i].name);
|
4832 | 6643d27e | bellard | fprintf (stream, _("\n"));
|
4833 | 6643d27e | bellard | |
4834 | 6643d27e | bellard | fprintf (stream, _("\n\
|
4835 | 6643d27e | bellard | For the options above, The following values are supported for \"ARCH\":\n\
|
4836 | 6643d27e | bellard | "));
|
4837 | 6643d27e | bellard | for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
|
4838 | 6643d27e | bellard | if (*mips_arch_choices[i].name != '\0')
|
4839 | 6643d27e | bellard | fprintf (stream, " %s", mips_arch_choices[i].name);
|
4840 | 6643d27e | bellard | fprintf (stream, _("\n"));
|
4841 | 6643d27e | bellard | |
4842 | 6643d27e | bellard | fprintf (stream, _("\n"));
|
4843 | 6643d27e | bellard | }
|
4844 | f9480ffc | ths | #endif |