root / hw / tusb6010.c @ 59d94130
History | View | Annotate | Download (23.5 kB)
1 |
/*
|
---|---|
2 |
* Texas Instruments TUSB6010 emulation.
|
3 |
* Based on reverse-engineering of a linux driver.
|
4 |
*
|
5 |
* Copyright (C) 2008 Nokia Corporation
|
6 |
* Written by Andrzej Zaborowski <andrew@openedhand.com>
|
7 |
*
|
8 |
* This program is free software; you can redistribute it and/or
|
9 |
* modify it under the terms of the GNU General Public License as
|
10 |
* published by the Free Software Foundation; either version 2 or
|
11 |
* (at your option) version 3 of the License.
|
12 |
*
|
13 |
* This program is distributed in the hope that it will be useful,
|
14 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 |
* GNU General Public License for more details.
|
17 |
*
|
18 |
* You should have received a copy of the GNU General Public License along
|
19 |
* with this program; if not, write to the Free Software Foundation, Inc.,
|
20 |
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
21 |
*/
|
22 |
#include "qemu-common.h" |
23 |
#include "qemu-timer.h" |
24 |
#include "usb.h" |
25 |
#include "omap.h" |
26 |
#include "irq.h" |
27 |
#include "devices.h" |
28 |
|
29 |
struct tusb_s {
|
30 |
int iomemtype[2]; |
31 |
qemu_irq irq; |
32 |
struct musb_s *musb;
|
33 |
QEMUTimer *otg_timer; |
34 |
QEMUTimer *pwr_timer; |
35 |
|
36 |
int power;
|
37 |
uint32_t scratch; |
38 |
uint16_t test_reset; |
39 |
uint32_t prcm_config; |
40 |
uint32_t prcm_mngmt; |
41 |
uint16_t otg_status; |
42 |
uint32_t dev_config; |
43 |
int host_mode;
|
44 |
uint32_t intr; |
45 |
uint32_t intr_ok; |
46 |
uint32_t mask; |
47 |
uint32_t usbip_intr; |
48 |
uint32_t usbip_mask; |
49 |
uint32_t gpio_intr; |
50 |
uint32_t gpio_mask; |
51 |
uint32_t gpio_config; |
52 |
uint32_t dma_intr; |
53 |
uint32_t dma_mask; |
54 |
uint32_t dma_map; |
55 |
uint32_t dma_config; |
56 |
uint32_t ep0_config; |
57 |
uint32_t rx_config[15];
|
58 |
uint32_t tx_config[15];
|
59 |
uint32_t wkup_mask; |
60 |
uint32_t pullup[2];
|
61 |
uint32_t control_config; |
62 |
uint32_t otg_timer_val; |
63 |
}; |
64 |
|
65 |
#define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
66 |
|
67 |
#define TUSB_VLYNQ_CTRL 0x004 |
68 |
|
69 |
/* Mentor Graphics OTG core registers. */
|
70 |
#define TUSB_BASE_OFFSET 0x400 |
71 |
|
72 |
/* FIFO registers, 32-bit. */
|
73 |
#define TUSB_FIFO_BASE 0x600 |
74 |
|
75 |
/* Device System & Control registers, 32-bit. */
|
76 |
#define TUSB_SYS_REG_BASE 0x800 |
77 |
|
78 |
#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
79 |
#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
80 |
#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
81 |
#define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
82 |
#define TUSB_DEV_CONF_ID_SEL (1 << 0) |
83 |
|
84 |
#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
85 |
#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
86 |
#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
87 |
#define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
88 |
#define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
89 |
#define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
90 |
#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
91 |
#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
92 |
#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
93 |
#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
94 |
#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
95 |
#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
96 |
#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
97 |
#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
98 |
#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
99 |
#define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
100 |
#define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
101 |
#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
102 |
#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
103 |
#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
104 |
#define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
105 |
#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
106 |
#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
107 |
|
108 |
/* OTG status register */
|
109 |
#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
110 |
#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
111 |
#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
112 |
#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
113 |
#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
114 |
#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
115 |
#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
116 |
#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
117 |
#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
118 |
#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
119 |
#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
120 |
|
121 |
#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
122 |
#define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
123 |
#define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
124 |
#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
125 |
|
126 |
/* PRCM configuration register */
|
127 |
#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
128 |
#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
129 |
#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
130 |
|
131 |
/* PRCM management register */
|
132 |
#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
133 |
#define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
134 |
#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
135 |
#define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
136 |
#define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
137 |
#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
138 |
#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
139 |
#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
140 |
#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
141 |
#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
142 |
#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
143 |
#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
144 |
#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
145 |
#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
146 |
#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
147 |
|
148 |
/* Wake-up source clear and mask registers */
|
149 |
#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
150 |
#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
151 |
#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
152 |
#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
153 |
#define TUSB_PRCM_WGPIO_7 (1 << 12) |
154 |
#define TUSB_PRCM_WGPIO_6 (1 << 11) |
155 |
#define TUSB_PRCM_WGPIO_5 (1 << 10) |
156 |
#define TUSB_PRCM_WGPIO_4 (1 << 9) |
157 |
#define TUSB_PRCM_WGPIO_3 (1 << 8) |
158 |
#define TUSB_PRCM_WGPIO_2 (1 << 7) |
159 |
#define TUSB_PRCM_WGPIO_1 (1 << 6) |
160 |
#define TUSB_PRCM_WGPIO_0 (1 << 5) |
161 |
#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
162 |
#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
163 |
#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
164 |
#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
165 |
#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
166 |
|
167 |
#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
168 |
#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
169 |
#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
170 |
#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
171 |
#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
172 |
#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
173 |
#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
174 |
#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
175 |
#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
176 |
#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
177 |
#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
178 |
#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
179 |
#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
180 |
#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
181 |
#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
182 |
#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
183 |
|
184 |
/* NOR flash interrupt source registers */
|
185 |
#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
186 |
#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
187 |
#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
188 |
#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
189 |
#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
190 |
#define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
191 |
#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
192 |
#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
193 |
#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
194 |
#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
195 |
#define TUSB_INT_SRC_DEV_READY (1 << 12) |
196 |
#define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
197 |
#define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
198 |
#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
199 |
#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
200 |
#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
201 |
#define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
202 |
#define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
203 |
#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
204 |
#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
205 |
#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
206 |
|
207 |
#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
208 |
#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
209 |
#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
210 |
#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
211 |
#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
212 |
#define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
213 |
#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
214 |
#define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
215 |
#define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
216 |
#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
217 |
#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
218 |
#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
219 |
|
220 |
#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
221 |
#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
222 |
|
223 |
/* Device System & Control register bitfields */
|
224 |
#define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
225 |
#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
226 |
#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
227 |
#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
228 |
#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
229 |
#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
230 |
#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
231 |
#define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
232 |
#define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
233 |
#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
234 |
#define TUSB_EP_CONFIG_SW_EN (1 << 31) |
235 |
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
236 |
#define TUSB_PROD_TEST_RESET_VAL 0xa596 |
237 |
|
238 |
int tusb6010_sync_io(struct tusb_s *s) |
239 |
{ |
240 |
return s->iomemtype[0]; |
241 |
} |
242 |
|
243 |
int tusb6010_async_io(struct tusb_s *s) |
244 |
{ |
245 |
return s->iomemtype[1]; |
246 |
} |
247 |
|
248 |
static void tusb_intr_update(struct tusb_s *s) |
249 |
{ |
250 |
if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
|
251 |
qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
252 |
else
|
253 |
qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
254 |
} |
255 |
|
256 |
static void tusb_usbip_intr_update(struct tusb_s *s) |
257 |
{ |
258 |
/* TX interrupt in the MUSB */
|
259 |
if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
260 |
s->intr |= TUSB_INT_SRC_USB_IP_TX; |
261 |
else
|
262 |
s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
263 |
|
264 |
/* RX interrupt in the MUSB */
|
265 |
if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
266 |
s->intr |= TUSB_INT_SRC_USB_IP_RX; |
267 |
else
|
268 |
s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
269 |
|
270 |
/* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
|
271 |
|
272 |
tusb_intr_update(s); |
273 |
} |
274 |
|
275 |
static void tusb_dma_intr_update(struct tusb_s *s) |
276 |
{ |
277 |
if (s->dma_intr & ~s->dma_mask)
|
278 |
s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
279 |
else
|
280 |
s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
281 |
|
282 |
tusb_intr_update(s); |
283 |
} |
284 |
|
285 |
static void tusb_gpio_intr_update(struct tusb_s *s) |
286 |
{ |
287 |
/* TODO: How is this signalled? */
|
288 |
} |
289 |
|
290 |
extern CPUReadMemoryFunc *musb_read[];
|
291 |
extern CPUWriteMemoryFunc *musb_write[];
|
292 |
|
293 |
static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) |
294 |
{ |
295 |
struct tusb_s *s = (struct tusb_s *) opaque; |
296 |
|
297 |
switch (addr & 0xfff) { |
298 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
299 |
return musb_read[0](s->musb, addr & 0x1ff); |
300 |
|
301 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
302 |
return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
303 |
} |
304 |
|
305 |
printf("%s: unknown register at %03x\n",
|
306 |
__FUNCTION__, (int) (addr & 0xfff)); |
307 |
return 0; |
308 |
} |
309 |
|
310 |
static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) |
311 |
{ |
312 |
struct tusb_s *s = (struct tusb_s *) opaque; |
313 |
|
314 |
switch (addr & 0xfff) { |
315 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
316 |
return musb_read[1](s->musb, addr & 0x1ff); |
317 |
|
318 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
319 |
return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
320 |
} |
321 |
|
322 |
printf("%s: unknown register at %03x\n",
|
323 |
__FUNCTION__, (int) (addr & 0xfff)); |
324 |
return 0; |
325 |
} |
326 |
|
327 |
static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) |
328 |
{ |
329 |
struct tusb_s *s = (struct tusb_s *) opaque; |
330 |
int offset = addr & 0xfff; |
331 |
int epnum;
|
332 |
uint32_t ret; |
333 |
|
334 |
switch (offset) {
|
335 |
case TUSB_DEV_CONF:
|
336 |
return s->dev_config;
|
337 |
|
338 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
339 |
return musb_read[2](s->musb, offset & 0x1ff); |
340 |
|
341 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
342 |
return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
343 |
|
344 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
345 |
case TUSB_PHY_OTG_CTRL:
|
346 |
return 0x00; /* TODO */ |
347 |
|
348 |
case TUSB_DEV_OTG_STAT:
|
349 |
ret = s->otg_status; |
350 |
#if 0
|
351 |
if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
|
352 |
ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
|
353 |
#endif
|
354 |
return ret;
|
355 |
case TUSB_DEV_OTG_TIMER:
|
356 |
return s->otg_timer_val;
|
357 |
|
358 |
case TUSB_PRCM_REV:
|
359 |
return 0x20; |
360 |
case TUSB_PRCM_CONF:
|
361 |
return s->prcm_config;
|
362 |
case TUSB_PRCM_MNGMT:
|
363 |
return s->prcm_mngmt;
|
364 |
case TUSB_PRCM_WAKEUP_SOURCE:
|
365 |
case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
366 |
return 0x00000000; |
367 |
case TUSB_PRCM_WAKEUP_MASK:
|
368 |
return s->wkup_mask;
|
369 |
|
370 |
case TUSB_PULLUP_1_CTRL:
|
371 |
return s->pullup[0]; |
372 |
case TUSB_PULLUP_2_CTRL:
|
373 |
return s->pullup[1]; |
374 |
|
375 |
case TUSB_INT_CTRL_REV:
|
376 |
return 0x20; |
377 |
case TUSB_INT_CTRL_CONF:
|
378 |
return s->control_config;
|
379 |
|
380 |
case TUSB_USBIP_INT_SRC:
|
381 |
case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
382 |
case TUSB_USBIP_INT_CLEAR:
|
383 |
return s->usbip_intr;
|
384 |
case TUSB_USBIP_INT_MASK:
|
385 |
return s->usbip_mask;
|
386 |
|
387 |
case TUSB_DMA_INT_SRC:
|
388 |
case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
389 |
case TUSB_DMA_INT_CLEAR:
|
390 |
return s->dma_intr;
|
391 |
case TUSB_DMA_INT_MASK:
|
392 |
return s->dma_mask;
|
393 |
|
394 |
case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
395 |
case TUSB_GPIO_INT_SET:
|
396 |
case TUSB_GPIO_INT_CLEAR:
|
397 |
return s->gpio_intr;
|
398 |
case TUSB_GPIO_INT_MASK:
|
399 |
return s->gpio_mask;
|
400 |
|
401 |
case TUSB_INT_SRC:
|
402 |
case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
403 |
case TUSB_INT_SRC_CLEAR:
|
404 |
return s->intr;
|
405 |
case TUSB_INT_MASK:
|
406 |
return s->mask;
|
407 |
|
408 |
case TUSB_GPIO_REV:
|
409 |
return 0x30; |
410 |
case TUSB_GPIO_CONF:
|
411 |
return s->gpio_config;
|
412 |
|
413 |
case TUSB_DMA_CTRL_REV:
|
414 |
return 0x30; |
415 |
case TUSB_DMA_REQ_CONF:
|
416 |
return s->dma_config;
|
417 |
case TUSB_EP0_CONF:
|
418 |
return s->ep0_config;
|
419 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
420 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
421 |
return s->tx_config[epnum];
|
422 |
case TUSB_DMA_EP_MAP:
|
423 |
return s->dma_map;
|
424 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
425 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
426 |
return s->rx_config[epnum];
|
427 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
428 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
429 |
epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
430 |
return 0x00000000; /* TODO */ |
431 |
case TUSB_WAIT_COUNT:
|
432 |
return 0x00; /* TODO */ |
433 |
|
434 |
case TUSB_SCRATCH_PAD:
|
435 |
return s->scratch;
|
436 |
|
437 |
case TUSB_PROD_TEST_RESET:
|
438 |
return s->test_reset;
|
439 |
|
440 |
/* DIE IDs */
|
441 |
case TUSB_DIDR1_LO:
|
442 |
return 0xa9453c59; |
443 |
case TUSB_DIDR1_HI:
|
444 |
return 0x54059adf; |
445 |
} |
446 |
|
447 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
448 |
return 0; |
449 |
} |
450 |
|
451 |
static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, |
452 |
uint32_t value) |
453 |
{ |
454 |
struct tusb_s *s = (struct tusb_s *) opaque; |
455 |
|
456 |
switch (addr & 0xfff) { |
457 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
458 |
musb_write[0](s->musb, addr & 0x1ff, value); |
459 |
break;
|
460 |
|
461 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
462 |
musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
463 |
break;
|
464 |
|
465 |
default:
|
466 |
printf("%s: unknown register at %03x\n",
|
467 |
__FUNCTION__, (int) (addr & 0xfff)); |
468 |
return;
|
469 |
} |
470 |
} |
471 |
|
472 |
static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, |
473 |
uint32_t value) |
474 |
{ |
475 |
struct tusb_s *s = (struct tusb_s *) opaque; |
476 |
|
477 |
switch (addr & 0xfff) { |
478 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
479 |
musb_write[1](s->musb, addr & 0x1ff, value); |
480 |
break;
|
481 |
|
482 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
483 |
musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
484 |
break;
|
485 |
|
486 |
default:
|
487 |
printf("%s: unknown register at %03x\n",
|
488 |
__FUNCTION__, (int) (addr & 0xfff)); |
489 |
return;
|
490 |
} |
491 |
} |
492 |
|
493 |
static void tusb_async_writew(void *opaque, target_phys_addr_t addr, |
494 |
uint32_t value) |
495 |
{ |
496 |
struct tusb_s *s = (struct tusb_s *) opaque; |
497 |
int offset = addr & 0xfff; |
498 |
int epnum;
|
499 |
|
500 |
switch (offset) {
|
501 |
case TUSB_VLYNQ_CTRL:
|
502 |
break;
|
503 |
|
504 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
505 |
musb_write[2](s->musb, offset & 0x1ff, value); |
506 |
break;
|
507 |
|
508 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
509 |
musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
510 |
break;
|
511 |
|
512 |
case TUSB_DEV_CONF:
|
513 |
s->dev_config = value; |
514 |
s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
515 |
if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
|
516 |
cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
|
517 |
__FUNCTION__); |
518 |
break;
|
519 |
|
520 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
521 |
case TUSB_PHY_OTG_CTRL:
|
522 |
return; /* TODO */ |
523 |
case TUSB_DEV_OTG_TIMER:
|
524 |
s->otg_timer_val = value; |
525 |
if (value & TUSB_DEV_OTG_TIMER_ENABLE)
|
526 |
qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + |
527 |
muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
528 |
ticks_per_sec, TUSB_DEVCLOCK)); |
529 |
else
|
530 |
qemu_del_timer(s->otg_timer); |
531 |
break;
|
532 |
|
533 |
case TUSB_PRCM_CONF:
|
534 |
s->prcm_config = value; |
535 |
break;
|
536 |
case TUSB_PRCM_MNGMT:
|
537 |
s->prcm_mngmt = value; |
538 |
break;
|
539 |
case TUSB_PRCM_WAKEUP_CLEAR:
|
540 |
break;
|
541 |
case TUSB_PRCM_WAKEUP_MASK:
|
542 |
s->wkup_mask = value; |
543 |
break;
|
544 |
|
545 |
case TUSB_PULLUP_1_CTRL:
|
546 |
s->pullup[0] = value;
|
547 |
break;
|
548 |
case TUSB_PULLUP_2_CTRL:
|
549 |
s->pullup[1] = value;
|
550 |
break;
|
551 |
case TUSB_INT_CTRL_CONF:
|
552 |
s->control_config = value; |
553 |
tusb_intr_update(s); |
554 |
break;
|
555 |
|
556 |
case TUSB_USBIP_INT_SET:
|
557 |
s->usbip_intr |= value; |
558 |
tusb_usbip_intr_update(s); |
559 |
break;
|
560 |
case TUSB_USBIP_INT_CLEAR:
|
561 |
s->usbip_intr &= ~value; |
562 |
tusb_usbip_intr_update(s); |
563 |
musb_core_intr_clear(s->musb, ~value); |
564 |
break;
|
565 |
case TUSB_USBIP_INT_MASK:
|
566 |
s->usbip_mask = value; |
567 |
tusb_usbip_intr_update(s); |
568 |
break;
|
569 |
|
570 |
case TUSB_DMA_INT_SET:
|
571 |
s->dma_intr |= value; |
572 |
tusb_dma_intr_update(s); |
573 |
break;
|
574 |
case TUSB_DMA_INT_CLEAR:
|
575 |
s->dma_intr &= ~value; |
576 |
tusb_dma_intr_update(s); |
577 |
break;
|
578 |
case TUSB_DMA_INT_MASK:
|
579 |
s->dma_mask = value; |
580 |
tusb_dma_intr_update(s); |
581 |
break;
|
582 |
|
583 |
case TUSB_GPIO_INT_SET:
|
584 |
s->gpio_intr |= value; |
585 |
tusb_gpio_intr_update(s); |
586 |
break;
|
587 |
case TUSB_GPIO_INT_CLEAR:
|
588 |
s->gpio_intr &= ~value; |
589 |
tusb_gpio_intr_update(s); |
590 |
break;
|
591 |
case TUSB_GPIO_INT_MASK:
|
592 |
s->gpio_mask = value; |
593 |
tusb_gpio_intr_update(s); |
594 |
break;
|
595 |
|
596 |
case TUSB_INT_SRC_SET:
|
597 |
s->intr |= value; |
598 |
tusb_intr_update(s); |
599 |
break;
|
600 |
case TUSB_INT_SRC_CLEAR:
|
601 |
s->intr &= ~value; |
602 |
tusb_intr_update(s); |
603 |
break;
|
604 |
case TUSB_INT_MASK:
|
605 |
s->mask = value; |
606 |
tusb_intr_update(s); |
607 |
break;
|
608 |
|
609 |
case TUSB_GPIO_CONF:
|
610 |
s->gpio_config = value; |
611 |
break;
|
612 |
case TUSB_DMA_REQ_CONF:
|
613 |
s->dma_config = value; |
614 |
break;
|
615 |
case TUSB_EP0_CONF:
|
616 |
s->ep0_config = value & 0x1ff;
|
617 |
musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
|
618 |
value & TUSB_EP0_CONFIG_DIR_TX); |
619 |
break;
|
620 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
621 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
622 |
s->tx_config[epnum] = value; |
623 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
624 |
break;
|
625 |
case TUSB_DMA_EP_MAP:
|
626 |
s->dma_map = value; |
627 |
break;
|
628 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
629 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
630 |
s->rx_config[epnum] = value; |
631 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
632 |
break;
|
633 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
634 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
635 |
epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
636 |
return; /* TODO */ |
637 |
case TUSB_WAIT_COUNT:
|
638 |
return; /* TODO */ |
639 |
|
640 |
case TUSB_SCRATCH_PAD:
|
641 |
s->scratch = value; |
642 |
break;
|
643 |
|
644 |
case TUSB_PROD_TEST_RESET:
|
645 |
s->test_reset = value; |
646 |
break;
|
647 |
|
648 |
default:
|
649 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
650 |
return;
|
651 |
} |
652 |
} |
653 |
|
654 |
static CPUReadMemoryFunc *tusb_async_readfn[] = {
|
655 |
tusb_async_readb, |
656 |
tusb_async_readh, |
657 |
tusb_async_readw, |
658 |
}; |
659 |
|
660 |
static CPUWriteMemoryFunc *tusb_async_writefn[] = {
|
661 |
tusb_async_writeb, |
662 |
tusb_async_writeh, |
663 |
tusb_async_writew, |
664 |
}; |
665 |
|
666 |
static void tusb_otg_tick(void *opaque) |
667 |
{ |
668 |
struct tusb_s *s = (struct tusb_s *) opaque; |
669 |
|
670 |
s->otg_timer_val = 0;
|
671 |
s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
672 |
tusb_intr_update(s); |
673 |
} |
674 |
|
675 |
static void tusb_power_tick(void *opaque) |
676 |
{ |
677 |
struct tusb_s *s = (struct tusb_s *) opaque; |
678 |
|
679 |
if (s->power) {
|
680 |
s->intr_ok = ~0;
|
681 |
tusb_intr_update(s); |
682 |
} |
683 |
} |
684 |
|
685 |
static void tusb_musb_core_intr(void *opaque, int source, int level) |
686 |
{ |
687 |
struct tusb_s *s = (struct tusb_s *) opaque; |
688 |
uint16_t otg_status = s->otg_status; |
689 |
|
690 |
switch (source) {
|
691 |
case musb_set_vbus:
|
692 |
if (level)
|
693 |
otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
694 |
else
|
695 |
otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
696 |
|
697 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
|
698 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
|
699 |
if (s->otg_status != otg_status) {
|
700 |
s->otg_status = otg_status; |
701 |
s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
702 |
tusb_intr_update(s); |
703 |
} |
704 |
break;
|
705 |
|
706 |
case musb_set_session:
|
707 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
|
708 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
|
709 |
if (level) {
|
710 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
711 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
712 |
} else {
|
713 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
714 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
715 |
} |
716 |
|
717 |
/* XXX: some IRQ or anything? */
|
718 |
break;
|
719 |
|
720 |
case musb_irq_tx:
|
721 |
case musb_irq_rx:
|
722 |
s->usbip_intr = musb_core_intr_get(s->musb); |
723 |
/* Fall through. */
|
724 |
default:
|
725 |
if (level)
|
726 |
s->intr |= 1 << source;
|
727 |
else
|
728 |
s->intr &= ~(1 << source);
|
729 |
tusb_intr_update(s); |
730 |
break;
|
731 |
} |
732 |
} |
733 |
|
734 |
struct tusb_s *tusb6010_init(qemu_irq intr)
|
735 |
{ |
736 |
struct tusb_s *s = qemu_mallocz(sizeof(*s)); |
737 |
|
738 |
s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
739 |
s->host_mode = 0;
|
740 |
s->dev_config = 0;
|
741 |
s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
742 |
s->power = 0;
|
743 |
s->mask = 0xffffffff;
|
744 |
s->intr = 0x00000000;
|
745 |
s->otg_timer_val = 0;
|
746 |
s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn, |
747 |
tusb_async_writefn, s); |
748 |
s->irq = intr; |
749 |
s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); |
750 |
s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); |
751 |
s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, |
752 |
__musb_irq_max)); |
753 |
|
754 |
return s;
|
755 |
} |
756 |
|
757 |
void tusb6010_power(struct tusb_s *s, int on) |
758 |
{ |
759 |
if (!on)
|
760 |
s->power = 0;
|
761 |
else if (!s->power && on) { |
762 |
s->power = 1;
|
763 |
|
764 |
/* Pull the interrupt down after TUSB6010 comes up. */
|
765 |
s->intr_ok = 0;
|
766 |
tusb_intr_update(s); |
767 |
qemu_mod_timer(s->pwr_timer, |
768 |
qemu_get_clock(vm_clock) + ticks_per_sec / 2);
|
769 |
} |
770 |
} |