Revision 5a0eed37 tcg/mips/tcg-target.c
| b/tcg/mips/tcg-target.c | ||
|---|---|---|
| 68 | 68 |
#endif |
| 69 | 69 |
|
| 70 | 70 |
/* check if we really need so many registers :P */ |
| 71 |
static const int tcg_target_reg_alloc_order[] = {
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|
| 71 |
static const TCGReg tcg_target_reg_alloc_order[] = {
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|
| 72 | 72 |
TCG_REG_S0, |
| 73 | 73 |
TCG_REG_S1, |
| 74 | 74 |
TCG_REG_S2, |
| ... | ... | |
| 94 | 94 |
TCG_REG_V1 |
| 95 | 95 |
}; |
| 96 | 96 |
|
| 97 |
static const int tcg_target_call_iarg_regs[4] = {
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| 97 |
static const TCGReg tcg_target_call_iarg_regs[4] = {
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|
| 98 | 98 |
TCG_REG_A0, |
| 99 | 99 |
TCG_REG_A1, |
| 100 | 100 |
TCG_REG_A2, |
| 101 | 101 |
TCG_REG_A3 |
| 102 | 102 |
}; |
| 103 | 103 |
|
| 104 |
static const int tcg_target_call_oarg_regs[2] = {
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| 104 |
static const TCGReg tcg_target_call_oarg_regs[2] = {
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|
| 105 | 105 |
TCG_REG_V0, |
| 106 | 106 |
TCG_REG_V1 |
| 107 | 107 |
}; |
| ... | ... | |
| 327 | 327 |
/* |
| 328 | 328 |
* Type reg |
| 329 | 329 |
*/ |
| 330 |
static inline void tcg_out_opc_reg(TCGContext *s, int opc, int rd, int rs, int rt) |
|
| 330 |
static inline void tcg_out_opc_reg(TCGContext *s, int opc, |
|
| 331 |
TCGReg rd, TCGReg rs, TCGReg rt) |
|
| 331 | 332 |
{
|
| 332 | 333 |
int32_t inst; |
| 333 | 334 |
|
| ... | ... | |
| 341 | 342 |
/* |
| 342 | 343 |
* Type immediate |
| 343 | 344 |
*/ |
| 344 |
static inline void tcg_out_opc_imm(TCGContext *s, int opc, int rt, int rs, int imm) |
|
| 345 |
static inline void tcg_out_opc_imm(TCGContext *s, int opc, |
|
| 346 |
TCGReg rt, TCGReg rs, TCGArg imm) |
|
| 345 | 347 |
{
|
| 346 | 348 |
int32_t inst; |
| 347 | 349 |
|
| ... | ... | |
| 355 | 357 |
/* |
| 356 | 358 |
* Type branch |
| 357 | 359 |
*/ |
| 358 |
static inline void tcg_out_opc_br(TCGContext *s, int opc, int rt, int rs) |
|
| 360 |
static inline void tcg_out_opc_br(TCGContext *s, int opc, |
|
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TCGReg rt, TCGReg rs) |
|
| 359 | 362 |
{
|
| 360 | 363 |
/* We pay attention here to not modify the branch target by reading |
| 361 | 364 |
the existing value and using it again. This ensure that caches and |
| ... | ... | |
| 368 | 371 |
/* |
| 369 | 372 |
* Type sa |
| 370 | 373 |
*/ |
| 371 |
static inline void tcg_out_opc_sa(TCGContext *s, int opc, int rd, int rt, int sa) |
|
| 374 |
static inline void tcg_out_opc_sa(TCGContext *s, int opc, |
|
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TCGReg rd, TCGReg rt, TCGArg sa) |
|
| 372 | 376 |
{
|
| 373 | 377 |
int32_t inst; |
| 374 | 378 |
|
| ... | ... | |
| 407 | 411 |
} |
| 408 | 412 |
} |
| 409 | 413 |
|
| 410 |
static inline void tcg_out_bswap16(TCGContext *s, int ret, int arg)
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| 414 |
static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
|
|
| 411 | 415 |
{
|
| 412 | 416 |
/* ret and arg can't be register at */ |
| 413 | 417 |
if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
|
| ... | ... | |
| 422 | 426 |
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT); |
| 423 | 427 |
} |
| 424 | 428 |
|
| 425 |
static inline void tcg_out_bswap16s(TCGContext *s, int ret, int arg)
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static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
|
|
| 426 | 430 |
{
|
| 427 | 431 |
/* ret and arg can't be register at */ |
| 428 | 432 |
if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
|
| ... | ... | |
| 437 | 441 |
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT); |
| 438 | 442 |
} |
| 439 | 443 |
|
| 440 |
static inline void tcg_out_bswap32(TCGContext *s, int ret, int arg)
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static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
|
|
| 441 | 445 |
{
|
| 442 | 446 |
/* ret and arg must be different and can't be register at */ |
| 443 | 447 |
if (ret == arg || ret == TCG_REG_AT || arg == TCG_REG_AT) {
|
| ... | ... | |
| 458 | 462 |
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT); |
| 459 | 463 |
} |
| 460 | 464 |
|
| 461 |
static inline void tcg_out_ext8s(TCGContext *s, int ret, int arg)
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static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
|
|
| 462 | 466 |
{
|
| 463 | 467 |
#ifdef _MIPS_ARCH_MIPS32R2 |
| 464 | 468 |
tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); |
| ... | ... | |
| 468 | 472 |
#endif |
| 469 | 473 |
} |
| 470 | 474 |
|
| 471 |
static inline void tcg_out_ext16s(TCGContext *s, int ret, int arg)
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static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
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| 472 | 476 |
{
|
| 473 | 477 |
#ifdef _MIPS_ARCH_MIPS32R2 |
| 474 | 478 |
tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); |
| ... | ... | |
| 478 | 482 |
#endif |
| 479 | 483 |
} |
| 480 | 484 |
|
| 481 |
static inline void tcg_out_ldst(TCGContext *s, int opc, int arg,
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int arg1, tcg_target_long arg2)
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static inline void tcg_out_ldst(TCGContext *s, int opc, TCGArg arg,
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TCGReg arg1, TCGArg arg2)
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| 483 | 487 |
{
|
| 484 | 488 |
if (arg2 == (int16_t) arg2) {
|
| 485 | 489 |
tcg_out_opc_imm(s, opc, arg, arg1, arg2); |
| ... | ... | |
| 502 | 506 |
tcg_out_ldst(s, OPC_SW, arg, arg1, arg2); |
| 503 | 507 |
} |
| 504 | 508 |
|
| 505 |
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
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| 506 | 510 |
{
|
| 507 | 511 |
if (val == (int16_t)val) {
|
| 508 | 512 |
tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val); |
| ... | ... | |
| 543 | 547 |
#undef DEFINE_TCG_OUT_CALL_IARG_GET_ARG |
| 544 | 548 |
#define DEFINE_TCG_OUT_CALL_IARG_GET_ARG(A) \ |
| 545 | 549 |
tcg_out_movi(s, TCG_TYPE_I32, A, arg); |
| 546 |
DEFINE_TCG_OUT_CALL_IARG(tcg_out_call_iarg_imm32, uint32_t arg)
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DEFINE_TCG_OUT_CALL_IARG(tcg_out_call_iarg_imm32, TCGArg arg)
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| 547 | 551 |
#undef DEFINE_TCG_OUT_CALL_IARG_GET_ARG |
| 548 | 552 |
|
| 549 | 553 |
/* We don't use the macro for this one to avoid an unnecessary reg-reg |
| ... | ... | |
| 573 | 577 |
#endif |
| 574 | 578 |
} |
| 575 | 579 |
|
| 576 |
static void tcg_out_brcond(TCGContext *s, TCGCond cond, int arg1,
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| 577 |
int arg2, int label_index)
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| 580 |
static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
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TCGArg arg2, int label_index)
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| 578 | 582 |
{
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| 579 | 583 |
TCGLabel *l = &s->labels[label_index]; |
| 580 | 584 |
|
| ... | ... | |
| 631 | 635 |
|
| 632 | 636 |
/* XXX: we implement it at the target level to avoid having to |
| 633 | 637 |
handle cross basic blocks temporaries */ |
| 634 |
static void tcg_out_brcond2(TCGContext *s, TCGCond cond, int arg1, |
|
| 635 |
int arg2, int arg3, int arg4, int label_index) |
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| 638 |
static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1, |
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| 639 |
TCGArg arg2, TCGArg arg3, TCGArg arg4, |
|
| 640 |
int label_index) |
|
| 636 | 641 |
{
|
| 637 | 642 |
void *label_ptr; |
| 638 | 643 |
|
| ... | ... | |
| 694 | 699 |
reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr); |
| 695 | 700 |
} |
| 696 | 701 |
|
| 697 |
static void tcg_out_setcond(TCGContext *s, TCGCond cond, int ret,
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| 698 |
int arg1, int arg2)
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| 702 |
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
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| 703 |
TCGArg arg1, TCGArg arg2)
|
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| 699 | 704 |
{
|
| 700 | 705 |
switch (cond) {
|
| 701 | 706 |
case TCG_COND_EQ: |
| ... | ... | |
| 754 | 759 |
|
| 755 | 760 |
/* XXX: we implement it at the target level to avoid having to |
| 756 | 761 |
handle cross basic blocks temporaries */ |
| 757 |
static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
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| 758 |
int arg1, int arg2, int arg3, int arg4)
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| 762 |
static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
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TCGArg arg1, TCGArg arg2, TCGArg arg3, TCGArg arg4)
|
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| 759 | 764 |
{
|
| 760 | 765 |
switch (cond) {
|
| 761 | 766 |
case TCG_COND_EQ: |
| ... | ... | |
| 842 | 847 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
| 843 | 848 |
int opc) |
| 844 | 849 |
{
|
| 845 |
int addr_regl, data_regl, data_regh, data_reg1, data_reg2;
|
|
| 850 |
TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
|
|
| 846 | 851 |
#if defined(CONFIG_SOFTMMU) |
| 847 | 852 |
void *label1_ptr, *label2_ptr; |
| 848 | 853 |
int arg_num; |
| ... | ... | |
| 850 | 855 |
int addr_meml; |
| 851 | 856 |
# if TARGET_LONG_BITS == 64 |
| 852 | 857 |
uint8_t *label3_ptr; |
| 853 |
int addr_regh, addr_memh; |
|
| 858 |
TCGReg addr_regh; |
|
| 859 |
int addr_memh; |
|
| 854 | 860 |
# endif |
| 855 | 861 |
#endif |
| 856 | 862 |
data_regl = *args++; |
| ... | ... | |
| 1026 | 1032 |
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
| 1027 | 1033 |
int opc) |
| 1028 | 1034 |
{
|
| 1029 |
int addr_regl, data_regl, data_regh, data_reg1, data_reg2;
|
|
| 1035 |
TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
|
|
| 1030 | 1036 |
#if defined(CONFIG_SOFTMMU) |
| 1031 | 1037 |
uint8_t *label1_ptr, *label2_ptr; |
| 1032 | 1038 |
int arg_num; |
| ... | ... | |
| 1036 | 1042 |
#if TARGET_LONG_BITS == 64 |
| 1037 | 1043 |
# if defined(CONFIG_SOFTMMU) |
| 1038 | 1044 |
uint8_t *label3_ptr; |
| 1039 |
int addr_regh, addr_memh; |
|
| 1045 |
TCGReg addr_regh; |
|
| 1046 |
int addr_memh; |
|
| 1040 | 1047 |
# endif |
| 1041 | 1048 |
#endif |
| 1042 | 1049 |
data_regl = *args++; |
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