root / target-mips / exec.h @ 5a1e8ffb
History | View | Annotate | Download (4.6 kB)
1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
|
---|---|---|---|
2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
|
3 | 6af0bf9c | bellard | |
4 | 01dbbdf1 | bellard | //#define DEBUG_OP
|
5 | 6af0bf9c | bellard | |
6 | c570fd16 | ths | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
9 | 01179c38 | ths | #include "cpu-defs.h" |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
12 | 6af0bf9c | bellard | |
13 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
14 | c570fd16 | ths | #define T0 (env->t0)
|
15 | c570fd16 | ths | #define T1 (env->t1)
|
16 | c570fd16 | ths | #define T2 (env->t2)
|
17 | c570fd16 | ths | #else
|
18 | 01179c38 | ths | register target_ulong T0 asm(AREG1); |
19 | 01179c38 | ths | register target_ulong T1 asm(AREG2); |
20 | 01179c38 | ths | register target_ulong T2 asm(AREG3); |
21 | c570fd16 | ths | #endif
|
22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #if defined (USE_HOST_FLOAT_REGS)
|
24 | 6ea83fed | bellard | #error "implement me." |
25 | 6af0bf9c | bellard | #else
|
26 | 6ea83fed | bellard | #define FDT0 (env->ft0.fd)
|
27 | 6ea83fed | bellard | #define FDT1 (env->ft1.fd)
|
28 | 6ea83fed | bellard | #define FDT2 (env->ft2.fd)
|
29 | 6ea83fed | bellard | #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
|
30 | 6ea83fed | bellard | #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
|
31 | 6ea83fed | bellard | #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
|
32 | 5a5012ec | ths | #define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
|
33 | 5a5012ec | ths | #define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
|
34 | 5a5012ec | ths | #define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
|
35 | 6ea83fed | bellard | #define DT0 (env->ft0.d)
|
36 | 6ea83fed | bellard | #define DT1 (env->ft1.d)
|
37 | 6ea83fed | bellard | #define DT2 (env->ft2.d)
|
38 | 6ea83fed | bellard | #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
|
39 | 6ea83fed | bellard | #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
|
40 | 6ea83fed | bellard | #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
|
41 | 5a5012ec | ths | #define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
|
42 | 5a5012ec | ths | #define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
|
43 | 5a5012ec | ths | #define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
|
44 | 6af0bf9c | bellard | #endif
|
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | #if defined (DEBUG_OP)
|
47 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("nop" : : : "memory"); |
48 | 6af0bf9c | bellard | #else
|
49 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("" : : : "memory"); |
50 | 6af0bf9c | bellard | #endif
|
51 | 6af0bf9c | bellard | |
52 | 6af0bf9c | bellard | #include "cpu.h" |
53 | 6af0bf9c | bellard | #include "exec-all.h" |
54 | 6af0bf9c | bellard | |
55 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
|
56 | a9049a07 | bellard | #include "softmmu_exec.h" |
57 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
58 | 6af0bf9c | bellard | |
59 | 6af0bf9c | bellard | static inline void env_to_regs(void) |
60 | 6af0bf9c | bellard | { |
61 | 6af0bf9c | bellard | } |
62 | 6af0bf9c | bellard | |
63 | 6af0bf9c | bellard | static inline void regs_to_env(void) |
64 | 6af0bf9c | bellard | { |
65 | 6af0bf9c | bellard | } |
66 | 6af0bf9c | bellard | |
67 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
68 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
69 | c570fd16 | ths | void do_dsll (void); |
70 | c570fd16 | ths | void do_dsll32 (void); |
71 | c570fd16 | ths | void do_dsra (void); |
72 | c570fd16 | ths | void do_dsra32 (void); |
73 | c570fd16 | ths | void do_dsrl (void); |
74 | c570fd16 | ths | void do_dsrl32 (void); |
75 | c570fd16 | ths | void do_drotr (void); |
76 | c570fd16 | ths | void do_drotr32 (void); |
77 | c570fd16 | ths | void do_dsllv (void); |
78 | c570fd16 | ths | void do_dsrav (void); |
79 | c570fd16 | ths | void do_dsrlv (void); |
80 | c570fd16 | ths | void do_drotrv (void); |
81 | c570fd16 | ths | #endif
|
82 | c570fd16 | ths | #endif
|
83 | c570fd16 | ths | |
84 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
85 | 80c27194 | ths | void do_div (void); |
86 | 80c27194 | ths | #endif
|
87 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
88 | 6af0bf9c | bellard | void do_mult (void); |
89 | 6af0bf9c | bellard | void do_multu (void); |
90 | 6af0bf9c | bellard | void do_madd (void); |
91 | 6af0bf9c | bellard | void do_maddu (void); |
92 | 6af0bf9c | bellard | void do_msub (void); |
93 | 6af0bf9c | bellard | void do_msubu (void); |
94 | 80c27194 | ths | #endif
|
95 | 80c27194 | ths | #ifdef TARGET_MIPS64
|
96 | c570fd16 | ths | void do_ddiv (void); |
97 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
98 | c570fd16 | ths | void do_ddivu (void); |
99 | c570fd16 | ths | #endif
|
100 | c570fd16 | ths | void do_dmult (void); |
101 | c570fd16 | ths | void do_dmultu (void); |
102 | 6af0bf9c | bellard | #endif
|
103 | 873eb012 | ths | void do_mfc0_random(void); |
104 | 873eb012 | ths | void do_mfc0_count(void); |
105 | 7a387fff | ths | void do_mtc0_entryhi(uint32_t in);
|
106 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val);
|
107 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void); |
108 | 6af0bf9c | bellard | void do_tlbwi (void); |
109 | 6af0bf9c | bellard | void do_tlbwr (void); |
110 | 6af0bf9c | bellard | void do_tlbp (void); |
111 | 6af0bf9c | bellard | void do_tlbr (void); |
112 | 6ea83fed | bellard | void dump_fpu(CPUState *env);
|
113 | 6ea83fed | bellard | void fpu_dump_state(CPUState *env, FILE *f,
|
114 | 6ea83fed | bellard | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
115 | 6ea83fed | bellard | int flags);
|
116 | 6ea83fed | bellard | void dump_sc (void); |
117 | 4ad40f36 | bellard | void do_lwl_raw (uint32_t);
|
118 | 4ad40f36 | bellard | void do_lwr_raw (uint32_t);
|
119 | 4ad40f36 | bellard | uint32_t do_swl_raw (uint32_t); |
120 | 4ad40f36 | bellard | uint32_t do_swr_raw (uint32_t); |
121 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
122 | c570fd16 | ths | void do_ldl_raw (uint64_t);
|
123 | c570fd16 | ths | void do_ldr_raw (uint64_t);
|
124 | c570fd16 | ths | uint64_t do_sdl_raw (uint64_t); |
125 | c570fd16 | ths | uint64_t do_sdr_raw (uint64_t); |
126 | c570fd16 | ths | #endif
|
127 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
|
128 | 4ad40f36 | bellard | void do_lwl_user (uint32_t);
|
129 | 4ad40f36 | bellard | void do_lwl_kernel (uint32_t);
|
130 | 4ad40f36 | bellard | void do_lwr_user (uint32_t);
|
131 | 4ad40f36 | bellard | void do_lwr_kernel (uint32_t);
|
132 | 4ad40f36 | bellard | uint32_t do_swl_user (uint32_t); |
133 | 4ad40f36 | bellard | uint32_t do_swl_kernel (uint32_t); |
134 | 4ad40f36 | bellard | uint32_t do_swr_user (uint32_t); |
135 | 4ad40f36 | bellard | uint32_t do_swr_kernel (uint32_t); |
136 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
137 | c570fd16 | ths | void do_ldl_user (uint64_t);
|
138 | c570fd16 | ths | void do_ldl_kernel (uint64_t);
|
139 | c570fd16 | ths | void do_ldr_user (uint64_t);
|
140 | c570fd16 | ths | void do_ldr_kernel (uint64_t);
|
141 | c570fd16 | ths | uint64_t do_sdl_user (uint64_t); |
142 | c570fd16 | ths | uint64_t do_sdl_kernel (uint64_t); |
143 | c570fd16 | ths | uint64_t do_sdr_user (uint64_t); |
144 | c570fd16 | ths | uint64_t do_sdr_kernel (uint64_t); |
145 | c570fd16 | ths | #endif
|
146 | 6af0bf9c | bellard | #endif
|
147 | 6af0bf9c | bellard | void do_pmon (int function); |
148 | 6af0bf9c | bellard | |
149 | d2ec1774 | pbrook | void dump_sc (void); |
150 | d2ec1774 | pbrook | |
151 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
152 | 6af0bf9c | bellard | int is_user, int is_softmmu); |
153 | 6af0bf9c | bellard | void do_interrupt (CPUState *env);
|
154 | 2ee4aed8 | bellard | void invalidate_tlb (CPUState *env, int idx, int use_extra); |
155 | 6af0bf9c | bellard | |
156 | 6af0bf9c | bellard | void cpu_loop_exit(void); |
157 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
158 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception);
|
159 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code); |
160 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception);
|
161 | 6af0bf9c | bellard | |
162 | 6af0bf9c | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
163 | 6af0bf9c | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
164 | 6af0bf9c | bellard | int flags);
|
165 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void); |
166 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env); |
167 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env); |
168 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value);
|
169 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value);
|
170 | a4bc3afc | ths | void cpu_mips_update_irq (CPUState *env);
|
171 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env);
|
172 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
173 | 6af0bf9c | bellard | |
174 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |