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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation micro-operations for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger (FPU operations)
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6 | 6af0bf9c | bellard | *
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7 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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8 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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10 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 6af0bf9c | bellard | *
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12 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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13 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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16 | 6af0bf9c | bellard | *
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17 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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19 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 6af0bf9c | bellard | */
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21 | 6af0bf9c | bellard | |
22 | 6af0bf9c | bellard | #include "config.h" |
23 | 6af0bf9c | bellard | #include "exec.h" |
24 | 6af0bf9c | bellard | |
25 | 1b351e52 | bellard | #ifndef CALL_FROM_TB0
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26 | 5a5012ec | ths | #define CALL_FROM_TB0(func) func()
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27 | 1b351e52 | bellard | #endif
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28 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1
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29 | 5a5012ec | ths | #define CALL_FROM_TB1(func, arg0) func(arg0)
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30 | 1b351e52 | bellard | #endif
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31 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1_CONST16
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32 | 5a5012ec | ths | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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33 | 1b351e52 | bellard | #endif
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34 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2
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35 | 5a5012ec | ths | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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36 | 1b351e52 | bellard | #endif
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37 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2_CONST16
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38 | 1b351e52 | bellard | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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39 | 5a5012ec | ths | CALL_FROM_TB2(func, arg0, arg1) |
40 | 1b351e52 | bellard | #endif
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41 | 1b351e52 | bellard | #ifndef CALL_FROM_TB3
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42 | 5a5012ec | ths | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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43 | 1b351e52 | bellard | #endif
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44 | 1b351e52 | bellard | #ifndef CALL_FROM_TB4
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45 | 1b351e52 | bellard | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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46 | 5a5012ec | ths | func(arg0, arg1, arg2, arg3) |
47 | 1b351e52 | bellard | #endif
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48 | 1b351e52 | bellard | |
49 | 6af0bf9c | bellard | #define REG 1 |
50 | 6af0bf9c | bellard | #include "op_template.c" |
51 | 6af0bf9c | bellard | #undef REG
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52 | 6af0bf9c | bellard | #define REG 2 |
53 | 6af0bf9c | bellard | #include "op_template.c" |
54 | 6af0bf9c | bellard | #undef REG
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55 | 6af0bf9c | bellard | #define REG 3 |
56 | 6af0bf9c | bellard | #include "op_template.c" |
57 | 6af0bf9c | bellard | #undef REG
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58 | 6af0bf9c | bellard | #define REG 4 |
59 | 6af0bf9c | bellard | #include "op_template.c" |
60 | 6af0bf9c | bellard | #undef REG
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61 | 6af0bf9c | bellard | #define REG 5 |
62 | 6af0bf9c | bellard | #include "op_template.c" |
63 | 6af0bf9c | bellard | #undef REG
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64 | 6af0bf9c | bellard | #define REG 6 |
65 | 6af0bf9c | bellard | #include "op_template.c" |
66 | 6af0bf9c | bellard | #undef REG
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67 | 6af0bf9c | bellard | #define REG 7 |
68 | 6af0bf9c | bellard | #include "op_template.c" |
69 | 6af0bf9c | bellard | #undef REG
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70 | 6af0bf9c | bellard | #define REG 8 |
71 | 6af0bf9c | bellard | #include "op_template.c" |
72 | 6af0bf9c | bellard | #undef REG
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73 | 6af0bf9c | bellard | #define REG 9 |
74 | 6af0bf9c | bellard | #include "op_template.c" |
75 | 6af0bf9c | bellard | #undef REG
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76 | 6af0bf9c | bellard | #define REG 10 |
77 | 6af0bf9c | bellard | #include "op_template.c" |
78 | 6af0bf9c | bellard | #undef REG
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79 | 6af0bf9c | bellard | #define REG 11 |
80 | 6af0bf9c | bellard | #include "op_template.c" |
81 | 6af0bf9c | bellard | #undef REG
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82 | 6af0bf9c | bellard | #define REG 12 |
83 | 6af0bf9c | bellard | #include "op_template.c" |
84 | 6af0bf9c | bellard | #undef REG
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85 | 6af0bf9c | bellard | #define REG 13 |
86 | 6af0bf9c | bellard | #include "op_template.c" |
87 | 6af0bf9c | bellard | #undef REG
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88 | 6af0bf9c | bellard | #define REG 14 |
89 | 6af0bf9c | bellard | #include "op_template.c" |
90 | 6af0bf9c | bellard | #undef REG
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91 | 6af0bf9c | bellard | #define REG 15 |
92 | 6af0bf9c | bellard | #include "op_template.c" |
93 | 6af0bf9c | bellard | #undef REG
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94 | 6af0bf9c | bellard | #define REG 16 |
95 | 6af0bf9c | bellard | #include "op_template.c" |
96 | 6af0bf9c | bellard | #undef REG
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97 | 6af0bf9c | bellard | #define REG 17 |
98 | 6af0bf9c | bellard | #include "op_template.c" |
99 | 6af0bf9c | bellard | #undef REG
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100 | 6af0bf9c | bellard | #define REG 18 |
101 | 6af0bf9c | bellard | #include "op_template.c" |
102 | 6af0bf9c | bellard | #undef REG
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103 | 6af0bf9c | bellard | #define REG 19 |
104 | 6af0bf9c | bellard | #include "op_template.c" |
105 | 6af0bf9c | bellard | #undef REG
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106 | 6af0bf9c | bellard | #define REG 20 |
107 | 6af0bf9c | bellard | #include "op_template.c" |
108 | 6af0bf9c | bellard | #undef REG
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109 | 6af0bf9c | bellard | #define REG 21 |
110 | 6af0bf9c | bellard | #include "op_template.c" |
111 | 6af0bf9c | bellard | #undef REG
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112 | 6af0bf9c | bellard | #define REG 22 |
113 | 6af0bf9c | bellard | #include "op_template.c" |
114 | 6af0bf9c | bellard | #undef REG
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115 | 6af0bf9c | bellard | #define REG 23 |
116 | 6af0bf9c | bellard | #include "op_template.c" |
117 | 6af0bf9c | bellard | #undef REG
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118 | 6af0bf9c | bellard | #define REG 24 |
119 | 6af0bf9c | bellard | #include "op_template.c" |
120 | 6af0bf9c | bellard | #undef REG
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121 | 6af0bf9c | bellard | #define REG 25 |
122 | 6af0bf9c | bellard | #include "op_template.c" |
123 | 6af0bf9c | bellard | #undef REG
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124 | 6af0bf9c | bellard | #define REG 26 |
125 | 6af0bf9c | bellard | #include "op_template.c" |
126 | 6af0bf9c | bellard | #undef REG
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127 | 6af0bf9c | bellard | #define REG 27 |
128 | 6af0bf9c | bellard | #include "op_template.c" |
129 | 6af0bf9c | bellard | #undef REG
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130 | 6af0bf9c | bellard | #define REG 28 |
131 | 6af0bf9c | bellard | #include "op_template.c" |
132 | 6af0bf9c | bellard | #undef REG
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133 | 6af0bf9c | bellard | #define REG 29 |
134 | 6af0bf9c | bellard | #include "op_template.c" |
135 | 6af0bf9c | bellard | #undef REG
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136 | 6af0bf9c | bellard | #define REG 30 |
137 | 6af0bf9c | bellard | #include "op_template.c" |
138 | 6af0bf9c | bellard | #undef REG
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139 | 6af0bf9c | bellard | #define REG 31 |
140 | 6af0bf9c | bellard | #include "op_template.c" |
141 | 6af0bf9c | bellard | #undef REG
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142 | 6af0bf9c | bellard | |
143 | c570fd16 | ths | #define TN
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144 | 6af0bf9c | bellard | #include "op_template.c" |
145 | 6af0bf9c | bellard | #undef TN
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146 | 6af0bf9c | bellard | |
147 | 5a5012ec | ths | #define FREG 0 |
148 | 6ea83fed | bellard | #include "fop_template.c" |
149 | 5a5012ec | ths | #undef FREG
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150 | 5a5012ec | ths | #define FREG 1 |
151 | 6ea83fed | bellard | #include "fop_template.c" |
152 | 5a5012ec | ths | #undef FREG
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153 | 5a5012ec | ths | #define FREG 2 |
154 | 6ea83fed | bellard | #include "fop_template.c" |
155 | 5a5012ec | ths | #undef FREG
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156 | 5a5012ec | ths | #define FREG 3 |
157 | 6ea83fed | bellard | #include "fop_template.c" |
158 | 5a5012ec | ths | #undef FREG
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159 | 5a5012ec | ths | #define FREG 4 |
160 | 6ea83fed | bellard | #include "fop_template.c" |
161 | 5a5012ec | ths | #undef FREG
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162 | 5a5012ec | ths | #define FREG 5 |
163 | 6ea83fed | bellard | #include "fop_template.c" |
164 | 5a5012ec | ths | #undef FREG
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165 | 5a5012ec | ths | #define FREG 6 |
166 | 6ea83fed | bellard | #include "fop_template.c" |
167 | 5a5012ec | ths | #undef FREG
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168 | 5a5012ec | ths | #define FREG 7 |
169 | 6ea83fed | bellard | #include "fop_template.c" |
170 | 5a5012ec | ths | #undef FREG
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171 | 5a5012ec | ths | #define FREG 8 |
172 | 6ea83fed | bellard | #include "fop_template.c" |
173 | 5a5012ec | ths | #undef FREG
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174 | 5a5012ec | ths | #define FREG 9 |
175 | 6ea83fed | bellard | #include "fop_template.c" |
176 | 5a5012ec | ths | #undef FREG
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177 | 5a5012ec | ths | #define FREG 10 |
178 | 6ea83fed | bellard | #include "fop_template.c" |
179 | 5a5012ec | ths | #undef FREG
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180 | 5a5012ec | ths | #define FREG 11 |
181 | 6ea83fed | bellard | #include "fop_template.c" |
182 | 5a5012ec | ths | #undef FREG
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183 | 5a5012ec | ths | #define FREG 12 |
184 | 6ea83fed | bellard | #include "fop_template.c" |
185 | 5a5012ec | ths | #undef FREG
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186 | 5a5012ec | ths | #define FREG 13 |
187 | 6ea83fed | bellard | #include "fop_template.c" |
188 | 5a5012ec | ths | #undef FREG
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189 | 5a5012ec | ths | #define FREG 14 |
190 | 6ea83fed | bellard | #include "fop_template.c" |
191 | 5a5012ec | ths | #undef FREG
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192 | 5a5012ec | ths | #define FREG 15 |
193 | 6ea83fed | bellard | #include "fop_template.c" |
194 | 5a5012ec | ths | #undef FREG
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195 | 5a5012ec | ths | #define FREG 16 |
196 | 6ea83fed | bellard | #include "fop_template.c" |
197 | 5a5012ec | ths | #undef FREG
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198 | 5a5012ec | ths | #define FREG 17 |
199 | 6ea83fed | bellard | #include "fop_template.c" |
200 | 5a5012ec | ths | #undef FREG
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201 | 5a5012ec | ths | #define FREG 18 |
202 | 6ea83fed | bellard | #include "fop_template.c" |
203 | 5a5012ec | ths | #undef FREG
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204 | 5a5012ec | ths | #define FREG 19 |
205 | 6ea83fed | bellard | #include "fop_template.c" |
206 | 5a5012ec | ths | #undef FREG
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207 | 5a5012ec | ths | #define FREG 20 |
208 | 6ea83fed | bellard | #include "fop_template.c" |
209 | 5a5012ec | ths | #undef FREG
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210 | 5a5012ec | ths | #define FREG 21 |
211 | 6ea83fed | bellard | #include "fop_template.c" |
212 | 5a5012ec | ths | #undef FREG
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213 | 5a5012ec | ths | #define FREG 22 |
214 | 6ea83fed | bellard | #include "fop_template.c" |
215 | 5a5012ec | ths | #undef FREG
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216 | 5a5012ec | ths | #define FREG 23 |
217 | 6ea83fed | bellard | #include "fop_template.c" |
218 | 5a5012ec | ths | #undef FREG
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219 | 5a5012ec | ths | #define FREG 24 |
220 | 6ea83fed | bellard | #include "fop_template.c" |
221 | 5a5012ec | ths | #undef FREG
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222 | 5a5012ec | ths | #define FREG 25 |
223 | 6ea83fed | bellard | #include "fop_template.c" |
224 | 5a5012ec | ths | #undef FREG
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225 | 5a5012ec | ths | #define FREG 26 |
226 | 6ea83fed | bellard | #include "fop_template.c" |
227 | 5a5012ec | ths | #undef FREG
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228 | 5a5012ec | ths | #define FREG 27 |
229 | 6ea83fed | bellard | #include "fop_template.c" |
230 | 5a5012ec | ths | #undef FREG
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231 | 5a5012ec | ths | #define FREG 28 |
232 | 6ea83fed | bellard | #include "fop_template.c" |
233 | 5a5012ec | ths | #undef FREG
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234 | 5a5012ec | ths | #define FREG 29 |
235 | 6ea83fed | bellard | #include "fop_template.c" |
236 | 5a5012ec | ths | #undef FREG
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237 | 5a5012ec | ths | #define FREG 30 |
238 | 6ea83fed | bellard | #include "fop_template.c" |
239 | 5a5012ec | ths | #undef FREG
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240 | 5a5012ec | ths | #define FREG 31 |
241 | 6ea83fed | bellard | #include "fop_template.c" |
242 | 5a5012ec | ths | #undef FREG
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243 | 6ea83fed | bellard | |
244 | 6ea83fed | bellard | #define FTN
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245 | 6ea83fed | bellard | #include "fop_template.c" |
246 | 6ea83fed | bellard | #undef FTN
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247 | 6ea83fed | bellard | |
248 | 6af0bf9c | bellard | void op_dup_T0 (void) |
249 | 6af0bf9c | bellard | { |
250 | 6af0bf9c | bellard | T2 = T0; |
251 | 6af0bf9c | bellard | RETURN(); |
252 | 6af0bf9c | bellard | } |
253 | 6af0bf9c | bellard | |
254 | 6af0bf9c | bellard | void op_load_HI (void) |
255 | 6af0bf9c | bellard | { |
256 | 6af0bf9c | bellard | T0 = env->HI; |
257 | 6af0bf9c | bellard | RETURN(); |
258 | 6af0bf9c | bellard | } |
259 | 6af0bf9c | bellard | |
260 | 6af0bf9c | bellard | void op_store_HI (void) |
261 | 6af0bf9c | bellard | { |
262 | 6af0bf9c | bellard | env->HI = T0; |
263 | 6af0bf9c | bellard | RETURN(); |
264 | 6af0bf9c | bellard | } |
265 | 6af0bf9c | bellard | |
266 | 6af0bf9c | bellard | void op_load_LO (void) |
267 | 6af0bf9c | bellard | { |
268 | 6af0bf9c | bellard | T0 = env->LO; |
269 | 6af0bf9c | bellard | RETURN(); |
270 | 6af0bf9c | bellard | } |
271 | 6af0bf9c | bellard | |
272 | 6af0bf9c | bellard | void op_store_LO (void) |
273 | 6af0bf9c | bellard | { |
274 | 6af0bf9c | bellard | env->LO = T0; |
275 | 6af0bf9c | bellard | RETURN(); |
276 | 6af0bf9c | bellard | } |
277 | 6af0bf9c | bellard | |
278 | 6af0bf9c | bellard | /* Load and store */
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279 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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280 | 6af0bf9c | bellard | #include "op_mem.c" |
281 | 6af0bf9c | bellard | #undef MEMSUFFIX
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282 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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283 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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284 | 6af0bf9c | bellard | #include "op_mem.c" |
285 | 6af0bf9c | bellard | #undef MEMSUFFIX
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286 | 6af0bf9c | bellard | |
287 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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288 | 6af0bf9c | bellard | #include "op_mem.c" |
289 | 6af0bf9c | bellard | #undef MEMSUFFIX
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290 | 6af0bf9c | bellard | #endif
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291 | 6af0bf9c | bellard | |
292 | a6763a58 | ths | /* Addresses computation */
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293 | a6763a58 | ths | void op_addr_add (void) |
294 | a6763a58 | ths | { |
295 | a6763a58 | ths | /* For compatibility with 32-bit code, data reference in user mode
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296 | a6763a58 | ths | with Status_UX = 0 should be casted to 32-bit and sign extended.
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297 | a6763a58 | ths | See the MIPS64 PRA manual, section 4.10. */
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298 | a6763a58 | ths | #ifdef TARGET_MIPS64
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299 | a6763a58 | ths | if ((env->CP0_Status & (1 << CP0St_UM)) && |
300 | a6763a58 | ths | !(env->CP0_Status & (1 << CP0St_UX)))
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301 | a6763a58 | ths | T0 = (int64_t)(int32_t)(T0 + T1); |
302 | a6763a58 | ths | else
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303 | a6763a58 | ths | #endif
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304 | a6763a58 | ths | T0 += T1; |
305 | a6763a58 | ths | RETURN(); |
306 | a6763a58 | ths | } |
307 | a6763a58 | ths | |
308 | 6af0bf9c | bellard | /* Arithmetic */
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309 | 6af0bf9c | bellard | void op_add (void) |
310 | 6af0bf9c | bellard | { |
311 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
312 | 6af0bf9c | bellard | RETURN(); |
313 | 6af0bf9c | bellard | } |
314 | 6af0bf9c | bellard | |
315 | 6af0bf9c | bellard | void op_addo (void) |
316 | 6af0bf9c | bellard | { |
317 | 6af0bf9c | bellard | target_ulong tmp; |
318 | 6af0bf9c | bellard | |
319 | c570fd16 | ths | tmp = (int32_t)T0; |
320 | c570fd16 | ths | T0 = (int32_t)T0 + (int32_t)T1; |
321 | 76e050c2 | bellard | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
322 | c570fd16 | ths | /* operands of same sign, result different sign */
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323 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
324 | 6af0bf9c | bellard | } |
325 | 5dc4b744 | ths | T0 = (int32_t)T0; |
326 | 6af0bf9c | bellard | RETURN(); |
327 | 6af0bf9c | bellard | } |
328 | 6af0bf9c | bellard | |
329 | 6af0bf9c | bellard | void op_sub (void) |
330 | 6af0bf9c | bellard | { |
331 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
332 | 6af0bf9c | bellard | RETURN(); |
333 | 6af0bf9c | bellard | } |
334 | 6af0bf9c | bellard | |
335 | 6af0bf9c | bellard | void op_subo (void) |
336 | 6af0bf9c | bellard | { |
337 | 6af0bf9c | bellard | target_ulong tmp; |
338 | 6af0bf9c | bellard | |
339 | c570fd16 | ths | tmp = (int32_t)T0; |
340 | 6af0bf9c | bellard | T0 = (int32_t)T0 - (int32_t)T1; |
341 | 76e050c2 | bellard | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
342 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
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343 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
344 | 6af0bf9c | bellard | } |
345 | 5dc4b744 | ths | T0 = (int32_t)T0; |
346 | 6af0bf9c | bellard | RETURN(); |
347 | 6af0bf9c | bellard | } |
348 | 6af0bf9c | bellard | |
349 | 6af0bf9c | bellard | void op_mul (void) |
350 | 6af0bf9c | bellard | { |
351 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
352 | 6af0bf9c | bellard | RETURN(); |
353 | 6af0bf9c | bellard | } |
354 | 6af0bf9c | bellard | |
355 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
356 | 80c27194 | ths | void op_div (void) |
357 | 80c27194 | ths | { |
358 | 80c27194 | ths | CALL_FROM_TB0(do_div); |
359 | 80c27194 | ths | RETURN(); |
360 | 80c27194 | ths | } |
361 | 80c27194 | ths | #else
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362 | 6af0bf9c | bellard | void op_div (void) |
363 | 6af0bf9c | bellard | { |
364 | 6af0bf9c | bellard | if (T1 != 0) { |
365 | 80c27194 | ths | env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1); |
366 | 80c27194 | ths | env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1); |
367 | 6af0bf9c | bellard | } |
368 | 6af0bf9c | bellard | RETURN(); |
369 | 6af0bf9c | bellard | } |
370 | 80c27194 | ths | #endif
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371 | 6af0bf9c | bellard | |
372 | 6af0bf9c | bellard | void op_divu (void) |
373 | 6af0bf9c | bellard | { |
374 | 6af0bf9c | bellard | if (T1 != 0) { |
375 | 5dc4b744 | ths | env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1); |
376 | 5dc4b744 | ths | env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1); |
377 | c570fd16 | ths | } |
378 | c570fd16 | ths | RETURN(); |
379 | c570fd16 | ths | } |
380 | c570fd16 | ths | |
381 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
382 | c570fd16 | ths | /* Arithmetic */
|
383 | c570fd16 | ths | void op_dadd (void) |
384 | c570fd16 | ths | { |
385 | c570fd16 | ths | T0 += T1; |
386 | c570fd16 | ths | RETURN(); |
387 | c570fd16 | ths | } |
388 | c570fd16 | ths | |
389 | c570fd16 | ths | void op_daddo (void) |
390 | c570fd16 | ths | { |
391 | c570fd16 | ths | target_long tmp; |
392 | c570fd16 | ths | |
393 | c570fd16 | ths | tmp = T0; |
394 | c570fd16 | ths | T0 += T1; |
395 | c570fd16 | ths | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { |
396 | c570fd16 | ths | /* operands of same sign, result different sign */
|
397 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
398 | c570fd16 | ths | } |
399 | c570fd16 | ths | RETURN(); |
400 | c570fd16 | ths | } |
401 | c570fd16 | ths | |
402 | c570fd16 | ths | void op_dsub (void) |
403 | c570fd16 | ths | { |
404 | c570fd16 | ths | T0 -= T1; |
405 | c570fd16 | ths | RETURN(); |
406 | c570fd16 | ths | } |
407 | c570fd16 | ths | |
408 | c570fd16 | ths | void op_dsubo (void) |
409 | c570fd16 | ths | { |
410 | c570fd16 | ths | target_long tmp; |
411 | c570fd16 | ths | |
412 | c570fd16 | ths | tmp = T0; |
413 | c570fd16 | ths | T0 = (int64_t)T0 - (int64_t)T1; |
414 | c570fd16 | ths | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { |
415 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
|
416 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
417 | c570fd16 | ths | } |
418 | c570fd16 | ths | RETURN(); |
419 | c570fd16 | ths | } |
420 | c570fd16 | ths | |
421 | c570fd16 | ths | void op_dmul (void) |
422 | c570fd16 | ths | { |
423 | c570fd16 | ths | T0 = (int64_t)T0 * (int64_t)T1; |
424 | c570fd16 | ths | RETURN(); |
425 | c570fd16 | ths | } |
426 | c570fd16 | ths | |
427 | c570fd16 | ths | /* Those might call libgcc functions. */
|
428 | c570fd16 | ths | void op_ddiv (void) |
429 | c570fd16 | ths | { |
430 | c570fd16 | ths | do_ddiv(); |
431 | c570fd16 | ths | RETURN(); |
432 | c570fd16 | ths | } |
433 | c570fd16 | ths | |
434 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
435 | c570fd16 | ths | void op_ddivu (void) |
436 | c570fd16 | ths | { |
437 | c570fd16 | ths | do_ddivu(); |
438 | c570fd16 | ths | RETURN(); |
439 | c570fd16 | ths | } |
440 | c570fd16 | ths | #else
|
441 | c570fd16 | ths | void op_ddivu (void) |
442 | c570fd16 | ths | { |
443 | c570fd16 | ths | if (T1 != 0) { |
444 | 6af0bf9c | bellard | env->LO = T0 / T1; |
445 | 6af0bf9c | bellard | env->HI = T0 % T1; |
446 | 6af0bf9c | bellard | } |
447 | 6af0bf9c | bellard | RETURN(); |
448 | 6af0bf9c | bellard | } |
449 | c570fd16 | ths | #endif
|
450 | 60aa19ab | ths | #endif /* TARGET_MIPS64 */ |
451 | 6af0bf9c | bellard | |
452 | 6af0bf9c | bellard | /* Logical */
|
453 | 6af0bf9c | bellard | void op_and (void) |
454 | 6af0bf9c | bellard | { |
455 | 6af0bf9c | bellard | T0 &= T1; |
456 | 6af0bf9c | bellard | RETURN(); |
457 | 6af0bf9c | bellard | } |
458 | 6af0bf9c | bellard | |
459 | 6af0bf9c | bellard | void op_nor (void) |
460 | 6af0bf9c | bellard | { |
461 | 6af0bf9c | bellard | T0 = ~(T0 | T1); |
462 | 6af0bf9c | bellard | RETURN(); |
463 | 6af0bf9c | bellard | } |
464 | 6af0bf9c | bellard | |
465 | 6af0bf9c | bellard | void op_or (void) |
466 | 6af0bf9c | bellard | { |
467 | 6af0bf9c | bellard | T0 |= T1; |
468 | 6af0bf9c | bellard | RETURN(); |
469 | 6af0bf9c | bellard | } |
470 | 6af0bf9c | bellard | |
471 | 6af0bf9c | bellard | void op_xor (void) |
472 | 6af0bf9c | bellard | { |
473 | 6af0bf9c | bellard | T0 ^= T1; |
474 | 6af0bf9c | bellard | RETURN(); |
475 | 6af0bf9c | bellard | } |
476 | 6af0bf9c | bellard | |
477 | 6af0bf9c | bellard | void op_sll (void) |
478 | 6af0bf9c | bellard | { |
479 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 << T1); |
480 | 6af0bf9c | bellard | RETURN(); |
481 | 6af0bf9c | bellard | } |
482 | 6af0bf9c | bellard | |
483 | 6af0bf9c | bellard | void op_sra (void) |
484 | 6af0bf9c | bellard | { |
485 | 5a63bcb2 | ths | T0 = (int32_t)((int32_t)T0 >> T1); |
486 | 6af0bf9c | bellard | RETURN(); |
487 | 6af0bf9c | bellard | } |
488 | 6af0bf9c | bellard | |
489 | 6af0bf9c | bellard | void op_srl (void) |
490 | 6af0bf9c | bellard | { |
491 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1); |
492 | 6af0bf9c | bellard | RETURN(); |
493 | 6af0bf9c | bellard | } |
494 | 6af0bf9c | bellard | |
495 | 7a387fff | ths | void op_rotr (void) |
496 | 7a387fff | ths | { |
497 | 7a387fff | ths | target_ulong tmp; |
498 | 7a387fff | ths | |
499 | 7a387fff | ths | if (T1) {
|
500 | 5a63bcb2 | ths | tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
|
501 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; |
502 | 5a63bcb2 | ths | } |
503 | 7a387fff | ths | RETURN(); |
504 | 7a387fff | ths | } |
505 | 7a387fff | ths | |
506 | 6af0bf9c | bellard | void op_sllv (void) |
507 | 6af0bf9c | bellard | { |
508 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
509 | 6af0bf9c | bellard | RETURN(); |
510 | 6af0bf9c | bellard | } |
511 | 6af0bf9c | bellard | |
512 | 6af0bf9c | bellard | void op_srav (void) |
513 | 6af0bf9c | bellard | { |
514 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
515 | 6af0bf9c | bellard | RETURN(); |
516 | 6af0bf9c | bellard | } |
517 | 6af0bf9c | bellard | |
518 | 6af0bf9c | bellard | void op_srlv (void) |
519 | 6af0bf9c | bellard | { |
520 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
521 | 6af0bf9c | bellard | RETURN(); |
522 | 6af0bf9c | bellard | } |
523 | 6af0bf9c | bellard | |
524 | 7a387fff | ths | void op_rotrv (void) |
525 | 7a387fff | ths | { |
526 | 7a387fff | ths | target_ulong tmp; |
527 | 7a387fff | ths | |
528 | 7a387fff | ths | T0 &= 0x1F;
|
529 | 7a387fff | ths | if (T0) {
|
530 | 5dc4b744 | ths | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
531 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; |
532 | 7a387fff | ths | } else
|
533 | 7a387fff | ths | T0 = T1; |
534 | 7a387fff | ths | RETURN(); |
535 | 7a387fff | ths | } |
536 | 7a387fff | ths | |
537 | 6af0bf9c | bellard | void op_clo (void) |
538 | 6af0bf9c | bellard | { |
539 | 6af0bf9c | bellard | int n;
|
540 | 6af0bf9c | bellard | |
541 | c570fd16 | ths | if (T0 == ~((target_ulong)0)) { |
542 | 6af0bf9c | bellard | T0 = 32;
|
543 | 6af0bf9c | bellard | } else {
|
544 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
545 | 6af0bf9c | bellard | if (!(T0 & (1 << 31))) |
546 | 6af0bf9c | bellard | break;
|
547 | 6af0bf9c | bellard | T0 = T0 << 1;
|
548 | 6af0bf9c | bellard | } |
549 | 6af0bf9c | bellard | T0 = n; |
550 | 6af0bf9c | bellard | } |
551 | 6af0bf9c | bellard | RETURN(); |
552 | 6af0bf9c | bellard | } |
553 | 6af0bf9c | bellard | |
554 | 6af0bf9c | bellard | void op_clz (void) |
555 | 6af0bf9c | bellard | { |
556 | 6af0bf9c | bellard | int n;
|
557 | 6af0bf9c | bellard | |
558 | 6af0bf9c | bellard | if (T0 == 0) { |
559 | 6af0bf9c | bellard | T0 = 32;
|
560 | 6af0bf9c | bellard | } else {
|
561 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
562 | 6af0bf9c | bellard | if (T0 & (1 << 31)) |
563 | 6af0bf9c | bellard | break;
|
564 | 6af0bf9c | bellard | T0 = T0 << 1;
|
565 | 6af0bf9c | bellard | } |
566 | 6af0bf9c | bellard | T0 = n; |
567 | 6af0bf9c | bellard | } |
568 | 6af0bf9c | bellard | RETURN(); |
569 | 6af0bf9c | bellard | } |
570 | 6af0bf9c | bellard | |
571 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
572 | c570fd16 | ths | |
573 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
574 | c570fd16 | ths | /* Those might call libgcc functions. */
|
575 | c570fd16 | ths | void op_dsll (void) |
576 | 6af0bf9c | bellard | { |
577 | c570fd16 | ths | CALL_FROM_TB0(do_dsll); |
578 | c570fd16 | ths | RETURN(); |
579 | 6af0bf9c | bellard | } |
580 | 6af0bf9c | bellard | |
581 | c570fd16 | ths | void op_dsll32 (void) |
582 | 6af0bf9c | bellard | { |
583 | c570fd16 | ths | CALL_FROM_TB0(do_dsll32); |
584 | c570fd16 | ths | RETURN(); |
585 | 6af0bf9c | bellard | } |
586 | 6af0bf9c | bellard | |
587 | c570fd16 | ths | void op_dsra (void) |
588 | 6af0bf9c | bellard | { |
589 | c570fd16 | ths | CALL_FROM_TB0(do_dsra); |
590 | 6af0bf9c | bellard | RETURN(); |
591 | 6af0bf9c | bellard | } |
592 | 6af0bf9c | bellard | |
593 | c570fd16 | ths | void op_dsra32 (void) |
594 | 6af0bf9c | bellard | { |
595 | c570fd16 | ths | CALL_FROM_TB0(do_dsra32); |
596 | 6af0bf9c | bellard | RETURN(); |
597 | 6af0bf9c | bellard | } |
598 | 6af0bf9c | bellard | |
599 | c570fd16 | ths | void op_dsrl (void) |
600 | 6af0bf9c | bellard | { |
601 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl); |
602 | c570fd16 | ths | RETURN(); |
603 | c570fd16 | ths | } |
604 | 6af0bf9c | bellard | |
605 | c570fd16 | ths | void op_dsrl32 (void) |
606 | c570fd16 | ths | { |
607 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl32); |
608 | 6af0bf9c | bellard | RETURN(); |
609 | 6af0bf9c | bellard | } |
610 | 6af0bf9c | bellard | |
611 | c570fd16 | ths | void op_drotr (void) |
612 | 6af0bf9c | bellard | { |
613 | c570fd16 | ths | CALL_FROM_TB0(do_drotr); |
614 | c570fd16 | ths | RETURN(); |
615 | c570fd16 | ths | } |
616 | 6af0bf9c | bellard | |
617 | c570fd16 | ths | void op_drotr32 (void) |
618 | c570fd16 | ths | { |
619 | c570fd16 | ths | CALL_FROM_TB0(do_drotr32); |
620 | 6af0bf9c | bellard | RETURN(); |
621 | 6af0bf9c | bellard | } |
622 | 6af0bf9c | bellard | |
623 | c570fd16 | ths | void op_dsllv (void) |
624 | 6af0bf9c | bellard | { |
625 | c570fd16 | ths | CALL_FROM_TB0(do_dsllv); |
626 | c570fd16 | ths | RETURN(); |
627 | c570fd16 | ths | } |
628 | 6af0bf9c | bellard | |
629 | c570fd16 | ths | void op_dsrav (void) |
630 | c570fd16 | ths | { |
631 | c570fd16 | ths | CALL_FROM_TB0(do_dsrav); |
632 | 6af0bf9c | bellard | RETURN(); |
633 | 6af0bf9c | bellard | } |
634 | 6af0bf9c | bellard | |
635 | c570fd16 | ths | void op_dsrlv (void) |
636 | 6af0bf9c | bellard | { |
637 | c570fd16 | ths | CALL_FROM_TB0(do_dsrlv); |
638 | c570fd16 | ths | RETURN(); |
639 | c570fd16 | ths | } |
640 | 6af0bf9c | bellard | |
641 | c570fd16 | ths | void op_drotrv (void) |
642 | c570fd16 | ths | { |
643 | c570fd16 | ths | CALL_FROM_TB0(do_drotrv); |
644 | 6af0bf9c | bellard | RETURN(); |
645 | 6af0bf9c | bellard | } |
646 | c570fd16 | ths | |
647 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
648 | c570fd16 | ths | |
649 | c570fd16 | ths | void op_dsll (void) |
650 | c570fd16 | ths | { |
651 | c570fd16 | ths | T0 = T0 << T1; |
652 | c570fd16 | ths | RETURN(); |
653 | c570fd16 | ths | } |
654 | c570fd16 | ths | |
655 | c570fd16 | ths | void op_dsll32 (void) |
656 | c570fd16 | ths | { |
657 | c570fd16 | ths | T0 = T0 << (T1 + 32);
|
658 | c570fd16 | ths | RETURN(); |
659 | c570fd16 | ths | } |
660 | c570fd16 | ths | |
661 | c570fd16 | ths | void op_dsra (void) |
662 | c570fd16 | ths | { |
663 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
664 | c570fd16 | ths | RETURN(); |
665 | c570fd16 | ths | } |
666 | c570fd16 | ths | |
667 | c570fd16 | ths | void op_dsra32 (void) |
668 | c570fd16 | ths | { |
669 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
|
670 | c570fd16 | ths | RETURN(); |
671 | c570fd16 | ths | } |
672 | c570fd16 | ths | |
673 | c570fd16 | ths | void op_dsrl (void) |
674 | c570fd16 | ths | { |
675 | c570fd16 | ths | T0 = T0 >> T1; |
676 | c570fd16 | ths | RETURN(); |
677 | c570fd16 | ths | } |
678 | c570fd16 | ths | |
679 | c570fd16 | ths | void op_dsrl32 (void) |
680 | c570fd16 | ths | { |
681 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
|
682 | c570fd16 | ths | RETURN(); |
683 | c570fd16 | ths | } |
684 | c570fd16 | ths | |
685 | c570fd16 | ths | void op_drotr (void) |
686 | c570fd16 | ths | { |
687 | c570fd16 | ths | target_ulong tmp; |
688 | c570fd16 | ths | |
689 | c570fd16 | ths | if (T1) {
|
690 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
|
691 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
692 | 5a63bcb2 | ths | } |
693 | c570fd16 | ths | RETURN(); |
694 | c570fd16 | ths | } |
695 | c570fd16 | ths | |
696 | c570fd16 | ths | void op_drotr32 (void) |
697 | c570fd16 | ths | { |
698 | c570fd16 | ths | target_ulong tmp; |
699 | c570fd16 | ths | |
700 | c570fd16 | ths | if (T1) {
|
701 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
702 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
|
703 | 5a63bcb2 | ths | } |
704 | c570fd16 | ths | RETURN(); |
705 | c570fd16 | ths | } |
706 | c570fd16 | ths | |
707 | c570fd16 | ths | void op_dsllv (void) |
708 | c570fd16 | ths | { |
709 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
|
710 | c570fd16 | ths | RETURN(); |
711 | c570fd16 | ths | } |
712 | c570fd16 | ths | |
713 | c570fd16 | ths | void op_dsrav (void) |
714 | c570fd16 | ths | { |
715 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
|
716 | c570fd16 | ths | RETURN(); |
717 | c570fd16 | ths | } |
718 | c570fd16 | ths | |
719 | c570fd16 | ths | void op_dsrlv (void) |
720 | c570fd16 | ths | { |
721 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
|
722 | c570fd16 | ths | RETURN(); |
723 | c570fd16 | ths | } |
724 | c570fd16 | ths | |
725 | c570fd16 | ths | void op_drotrv (void) |
726 | c570fd16 | ths | { |
727 | c570fd16 | ths | target_ulong tmp; |
728 | c570fd16 | ths | |
729 | c570fd16 | ths | T0 &= 0x3F;
|
730 | c570fd16 | ths | if (T0) {
|
731 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
|
732 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
733 | c570fd16 | ths | } else
|
734 | c570fd16 | ths | T0 = T1; |
735 | c570fd16 | ths | RETURN(); |
736 | c570fd16 | ths | } |
737 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
738 | c570fd16 | ths | |
739 | c570fd16 | ths | void op_dclo (void) |
740 | c570fd16 | ths | { |
741 | c570fd16 | ths | int n;
|
742 | c570fd16 | ths | |
743 | c570fd16 | ths | if (T0 == ~((target_ulong)0)) { |
744 | c570fd16 | ths | T0 = 64;
|
745 | c570fd16 | ths | } else {
|
746 | c570fd16 | ths | for (n = 0; n < 64; n++) { |
747 | c570fd16 | ths | if (!(T0 & (1ULL << 63))) |
748 | c570fd16 | ths | break;
|
749 | c570fd16 | ths | T0 = T0 << 1;
|
750 | c570fd16 | ths | } |
751 | c570fd16 | ths | T0 = n; |
752 | c570fd16 | ths | } |
753 | c570fd16 | ths | RETURN(); |
754 | c570fd16 | ths | } |
755 | c570fd16 | ths | |
756 | c570fd16 | ths | void op_dclz (void) |
757 | c570fd16 | ths | { |
758 | c570fd16 | ths | int n;
|
759 | c570fd16 | ths | |
760 | c570fd16 | ths | if (T0 == 0) { |
761 | c570fd16 | ths | T0 = 64;
|
762 | c570fd16 | ths | } else {
|
763 | c570fd16 | ths | for (n = 0; n < 64; n++) { |
764 | c570fd16 | ths | if (T0 & (1ULL << 63)) |
765 | c570fd16 | ths | break;
|
766 | c570fd16 | ths | T0 = T0 << 1;
|
767 | c570fd16 | ths | } |
768 | c570fd16 | ths | T0 = n; |
769 | c570fd16 | ths | } |
770 | c570fd16 | ths | RETURN(); |
771 | c570fd16 | ths | } |
772 | c570fd16 | ths | #endif
|
773 | c570fd16 | ths | |
774 | c570fd16 | ths | /* 64 bits arithmetic */
|
775 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
776 | 6af0bf9c | bellard | void op_mult (void) |
777 | 6af0bf9c | bellard | { |
778 | 6af0bf9c | bellard | CALL_FROM_TB0(do_mult); |
779 | 6af0bf9c | bellard | RETURN(); |
780 | 6af0bf9c | bellard | } |
781 | 6af0bf9c | bellard | |
782 | 6af0bf9c | bellard | void op_multu (void) |
783 | 6af0bf9c | bellard | { |
784 | 6af0bf9c | bellard | CALL_FROM_TB0(do_multu); |
785 | 6af0bf9c | bellard | RETURN(); |
786 | 6af0bf9c | bellard | } |
787 | 6af0bf9c | bellard | |
788 | 6af0bf9c | bellard | void op_madd (void) |
789 | 6af0bf9c | bellard | { |
790 | 6af0bf9c | bellard | CALL_FROM_TB0(do_madd); |
791 | 6af0bf9c | bellard | RETURN(); |
792 | 6af0bf9c | bellard | } |
793 | 6af0bf9c | bellard | |
794 | 6af0bf9c | bellard | void op_maddu (void) |
795 | 6af0bf9c | bellard | { |
796 | 6af0bf9c | bellard | CALL_FROM_TB0(do_maddu); |
797 | 6af0bf9c | bellard | RETURN(); |
798 | 6af0bf9c | bellard | } |
799 | 6af0bf9c | bellard | |
800 | 6af0bf9c | bellard | void op_msub (void) |
801 | 6af0bf9c | bellard | { |
802 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msub); |
803 | 6af0bf9c | bellard | RETURN(); |
804 | 6af0bf9c | bellard | } |
805 | 6af0bf9c | bellard | |
806 | 6af0bf9c | bellard | void op_msubu (void) |
807 | 6af0bf9c | bellard | { |
808 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msubu); |
809 | 6af0bf9c | bellard | RETURN(); |
810 | 6af0bf9c | bellard | } |
811 | c570fd16 | ths | |
812 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
813 | c570fd16 | ths | |
814 | c570fd16 | ths | static inline uint64_t get_HILO (void) |
815 | c570fd16 | ths | { |
816 | c570fd16 | ths | return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO); |
817 | c570fd16 | ths | } |
818 | c570fd16 | ths | |
819 | c570fd16 | ths | static inline void set_HILO (uint64_t HILO) |
820 | c570fd16 | ths | { |
821 | 5dc4b744 | ths | env->LO = (int32_t)(HILO & 0xFFFFFFFF);
|
822 | 5dc4b744 | ths | env->HI = (int32_t)(HILO >> 32);
|
823 | c570fd16 | ths | } |
824 | c570fd16 | ths | |
825 | c570fd16 | ths | void op_mult (void) |
826 | c570fd16 | ths | { |
827 | c570fd16 | ths | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
828 | c570fd16 | ths | RETURN(); |
829 | c570fd16 | ths | } |
830 | c570fd16 | ths | |
831 | c570fd16 | ths | void op_multu (void) |
832 | c570fd16 | ths | { |
833 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
834 | c570fd16 | ths | RETURN(); |
835 | c570fd16 | ths | } |
836 | c570fd16 | ths | |
837 | c570fd16 | ths | void op_madd (void) |
838 | c570fd16 | ths | { |
839 | c570fd16 | ths | int64_t tmp; |
840 | c570fd16 | ths | |
841 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
842 | c570fd16 | ths | set_HILO((int64_t)get_HILO() + tmp); |
843 | c570fd16 | ths | RETURN(); |
844 | c570fd16 | ths | } |
845 | c570fd16 | ths | |
846 | c570fd16 | ths | void op_maddu (void) |
847 | c570fd16 | ths | { |
848 | c570fd16 | ths | uint64_t tmp; |
849 | c570fd16 | ths | |
850 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
851 | c570fd16 | ths | set_HILO(get_HILO() + tmp); |
852 | c570fd16 | ths | RETURN(); |
853 | c570fd16 | ths | } |
854 | c570fd16 | ths | |
855 | c570fd16 | ths | void op_msub (void) |
856 | c570fd16 | ths | { |
857 | c570fd16 | ths | int64_t tmp; |
858 | c570fd16 | ths | |
859 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
860 | c570fd16 | ths | set_HILO((int64_t)get_HILO() - tmp); |
861 | c570fd16 | ths | RETURN(); |
862 | c570fd16 | ths | } |
863 | c570fd16 | ths | |
864 | c570fd16 | ths | void op_msubu (void) |
865 | c570fd16 | ths | { |
866 | c570fd16 | ths | uint64_t tmp; |
867 | c570fd16 | ths | |
868 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
869 | c570fd16 | ths | set_HILO(get_HILO() - tmp); |
870 | c570fd16 | ths | RETURN(); |
871 | c570fd16 | ths | } |
872 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
873 | c570fd16 | ths | |
874 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
875 | c570fd16 | ths | void op_dmult (void) |
876 | c570fd16 | ths | { |
877 | c570fd16 | ths | CALL_FROM_TB0(do_dmult); |
878 | c570fd16 | ths | RETURN(); |
879 | c570fd16 | ths | } |
880 | c570fd16 | ths | |
881 | c570fd16 | ths | void op_dmultu (void) |
882 | c570fd16 | ths | { |
883 | c570fd16 | ths | CALL_FROM_TB0(do_dmultu); |
884 | c570fd16 | ths | RETURN(); |
885 | c570fd16 | ths | } |
886 | 6af0bf9c | bellard | #endif
|
887 | 6af0bf9c | bellard | |
888 | 6af0bf9c | bellard | /* Conditional moves */
|
889 | 6af0bf9c | bellard | void op_movn (void) |
890 | 6af0bf9c | bellard | { |
891 | 6af0bf9c | bellard | if (T1 != 0) |
892 | 6af0bf9c | bellard | env->gpr[PARAM1] = T0; |
893 | 6af0bf9c | bellard | RETURN(); |
894 | 6af0bf9c | bellard | } |
895 | 6af0bf9c | bellard | |
896 | 6af0bf9c | bellard | void op_movz (void) |
897 | 6af0bf9c | bellard | { |
898 | 6af0bf9c | bellard | if (T1 == 0) |
899 | 6af0bf9c | bellard | env->gpr[PARAM1] = T0; |
900 | 6af0bf9c | bellard | RETURN(); |
901 | 6af0bf9c | bellard | } |
902 | 6af0bf9c | bellard | |
903 | 7a387fff | ths | void op_movf (void) |
904 | 7a387fff | ths | { |
905 | 7a387fff | ths | if (!(env->fcr31 & PARAM1))
|
906 | 5a5012ec | ths | T0 = T1; |
907 | 7a387fff | ths | RETURN(); |
908 | 7a387fff | ths | } |
909 | 7a387fff | ths | |
910 | 7a387fff | ths | void op_movt (void) |
911 | 7a387fff | ths | { |
912 | 7a387fff | ths | if (env->fcr31 & PARAM1)
|
913 | 5a5012ec | ths | T0 = T1; |
914 | 7a387fff | ths | RETURN(); |
915 | 7a387fff | ths | } |
916 | 7a387fff | ths | |
917 | 6af0bf9c | bellard | /* Tests */
|
918 | 6af0bf9c | bellard | #define OP_COND(name, cond) \
|
919 | 6af0bf9c | bellard | void glue(op_, name) (void) \ |
920 | 6af0bf9c | bellard | { \ |
921 | 6af0bf9c | bellard | if (cond) { \
|
922 | 6af0bf9c | bellard | T0 = 1; \
|
923 | 6af0bf9c | bellard | } else { \
|
924 | 6af0bf9c | bellard | T0 = 0; \
|
925 | 6af0bf9c | bellard | } \ |
926 | 6af0bf9c | bellard | RETURN(); \ |
927 | 6af0bf9c | bellard | } |
928 | 6af0bf9c | bellard | |
929 | 6af0bf9c | bellard | OP_COND(eq, T0 == T1); |
930 | 6af0bf9c | bellard | OP_COND(ne, T0 != T1); |
931 | 6af0bf9c | bellard | OP_COND(ge, (int32_t)T0 >= (int32_t)T1); |
932 | 6af0bf9c | bellard | OP_COND(geu, T0 >= T1); |
933 | 6af0bf9c | bellard | OP_COND(lt, (int32_t)T0 < (int32_t)T1); |
934 | 6af0bf9c | bellard | OP_COND(ltu, T0 < T1); |
935 | 6af0bf9c | bellard | OP_COND(gez, (int32_t)T0 >= 0);
|
936 | 6af0bf9c | bellard | OP_COND(gtz, (int32_t)T0 > 0);
|
937 | 6af0bf9c | bellard | OP_COND(lez, (int32_t)T0 <= 0);
|
938 | 6af0bf9c | bellard | OP_COND(ltz, (int32_t)T0 < 0);
|
939 | 6af0bf9c | bellard | |
940 | 7a387fff | ths | /* Branches */
|
941 | 6af0bf9c | bellard | //#undef USE_DIRECT_JUMP
|
942 | c53be334 | bellard | |
943 | c53be334 | bellard | void OPPROTO op_goto_tb0(void) |
944 | c53be334 | bellard | { |
945 | c53be334 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
946 | 7a387fff | ths | RETURN(); |
947 | c53be334 | bellard | } |
948 | c53be334 | bellard | |
949 | c53be334 | bellard | void OPPROTO op_goto_tb1(void) |
950 | c53be334 | bellard | { |
951 | c53be334 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
952 | 7a387fff | ths | RETURN(); |
953 | c53be334 | bellard | } |
954 | 6af0bf9c | bellard | |
955 | 6af0bf9c | bellard | /* Branch to register */
|
956 | 6af0bf9c | bellard | void op_save_breg_target (void) |
957 | 6af0bf9c | bellard | { |
958 | 6af0bf9c | bellard | env->btarget = T2; |
959 | 7a387fff | ths | RETURN(); |
960 | 6af0bf9c | bellard | } |
961 | 6af0bf9c | bellard | |
962 | 6af0bf9c | bellard | void op_restore_breg_target (void) |
963 | 6af0bf9c | bellard | { |
964 | 6af0bf9c | bellard | T2 = env->btarget; |
965 | 7a387fff | ths | RETURN(); |
966 | 6af0bf9c | bellard | } |
967 | 6af0bf9c | bellard | |
968 | 6af0bf9c | bellard | void op_breg (void) |
969 | 6af0bf9c | bellard | { |
970 | 6af0bf9c | bellard | env->PC = T2; |
971 | 6af0bf9c | bellard | RETURN(); |
972 | 6af0bf9c | bellard | } |
973 | 6af0bf9c | bellard | |
974 | 6af0bf9c | bellard | void op_save_btarget (void) |
975 | 6af0bf9c | bellard | { |
976 | 6af0bf9c | bellard | env->btarget = PARAM1; |
977 | 6af0bf9c | bellard | RETURN(); |
978 | 6af0bf9c | bellard | } |
979 | 6af0bf9c | bellard | |
980 | 6af0bf9c | bellard | /* Conditional branch */
|
981 | 6af0bf9c | bellard | void op_set_bcond (void) |
982 | 6af0bf9c | bellard | { |
983 | 6af0bf9c | bellard | T2 = T0; |
984 | 6af0bf9c | bellard | RETURN(); |
985 | 6af0bf9c | bellard | } |
986 | 6af0bf9c | bellard | |
987 | 6af0bf9c | bellard | void op_save_bcond (void) |
988 | 6af0bf9c | bellard | { |
989 | 6af0bf9c | bellard | env->bcond = T2; |
990 | 6af0bf9c | bellard | RETURN(); |
991 | 6af0bf9c | bellard | } |
992 | 6af0bf9c | bellard | |
993 | 6af0bf9c | bellard | void op_restore_bcond (void) |
994 | 6af0bf9c | bellard | { |
995 | 6af0bf9c | bellard | T2 = env->bcond; |
996 | 6af0bf9c | bellard | RETURN(); |
997 | 6af0bf9c | bellard | } |
998 | 6af0bf9c | bellard | |
999 | c53be334 | bellard | void op_jnz_T2 (void) |
1000 | 6af0bf9c | bellard | { |
1001 | c53be334 | bellard | if (T2)
|
1002 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
1003 | 6af0bf9c | bellard | RETURN(); |
1004 | 6af0bf9c | bellard | } |
1005 | 6af0bf9c | bellard | |
1006 | 6af0bf9c | bellard | /* CP0 functions */
|
1007 | 873eb012 | ths | void op_mfc0_index (void) |
1008 | 6af0bf9c | bellard | { |
1009 | 9c2149c8 | ths | T0 = env->CP0_Index; |
1010 | 873eb012 | ths | RETURN(); |
1011 | 873eb012 | ths | } |
1012 | 873eb012 | ths | |
1013 | 873eb012 | ths | void op_mfc0_random (void) |
1014 | 873eb012 | ths | { |
1015 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_random); |
1016 | 873eb012 | ths | RETURN(); |
1017 | 873eb012 | ths | } |
1018 | 873eb012 | ths | |
1019 | 873eb012 | ths | void op_mfc0_entrylo0 (void) |
1020 | 873eb012 | ths | { |
1021 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo0; |
1022 | 873eb012 | ths | RETURN(); |
1023 | 873eb012 | ths | } |
1024 | 873eb012 | ths | |
1025 | 873eb012 | ths | void op_mfc0_entrylo1 (void) |
1026 | 873eb012 | ths | { |
1027 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo1; |
1028 | 873eb012 | ths | RETURN(); |
1029 | 873eb012 | ths | } |
1030 | 873eb012 | ths | |
1031 | 873eb012 | ths | void op_mfc0_context (void) |
1032 | 873eb012 | ths | { |
1033 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_Context; |
1034 | 873eb012 | ths | RETURN(); |
1035 | 873eb012 | ths | } |
1036 | 873eb012 | ths | |
1037 | 873eb012 | ths | void op_mfc0_pagemask (void) |
1038 | 873eb012 | ths | { |
1039 | 9c2149c8 | ths | T0 = env->CP0_PageMask; |
1040 | 873eb012 | ths | RETURN(); |
1041 | 873eb012 | ths | } |
1042 | 873eb012 | ths | |
1043 | 7a387fff | ths | void op_mfc0_pagegrain (void) |
1044 | 7a387fff | ths | { |
1045 | 9c2149c8 | ths | T0 = env->CP0_PageGrain; |
1046 | 7a387fff | ths | RETURN(); |
1047 | 7a387fff | ths | } |
1048 | 7a387fff | ths | |
1049 | 873eb012 | ths | void op_mfc0_wired (void) |
1050 | 873eb012 | ths | { |
1051 | 9c2149c8 | ths | T0 = env->CP0_Wired; |
1052 | 873eb012 | ths | RETURN(); |
1053 | 873eb012 | ths | } |
1054 | 873eb012 | ths | |
1055 | 7a387fff | ths | void op_mfc0_hwrena (void) |
1056 | 7a387fff | ths | { |
1057 | 9c2149c8 | ths | T0 = env->CP0_HWREna; |
1058 | 7a387fff | ths | RETURN(); |
1059 | 7a387fff | ths | } |
1060 | 7a387fff | ths | |
1061 | 873eb012 | ths | void op_mfc0_badvaddr (void) |
1062 | 873eb012 | ths | { |
1063 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_BadVAddr; |
1064 | 873eb012 | ths | RETURN(); |
1065 | 873eb012 | ths | } |
1066 | 873eb012 | ths | |
1067 | 873eb012 | ths | void op_mfc0_count (void) |
1068 | 873eb012 | ths | { |
1069 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_count); |
1070 | 873eb012 | ths | RETURN(); |
1071 | 873eb012 | ths | } |
1072 | 873eb012 | ths | |
1073 | 873eb012 | ths | void op_mfc0_entryhi (void) |
1074 | 873eb012 | ths | { |
1075 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryHi; |
1076 | 873eb012 | ths | RETURN(); |
1077 | 873eb012 | ths | } |
1078 | 873eb012 | ths | |
1079 | 873eb012 | ths | void op_mfc0_compare (void) |
1080 | 873eb012 | ths | { |
1081 | 9c2149c8 | ths | T0 = env->CP0_Compare; |
1082 | 873eb012 | ths | RETURN(); |
1083 | 873eb012 | ths | } |
1084 | 873eb012 | ths | |
1085 | 873eb012 | ths | void op_mfc0_status (void) |
1086 | 873eb012 | ths | { |
1087 | 9c2149c8 | ths | T0 = env->CP0_Status; |
1088 | 873eb012 | ths | RETURN(); |
1089 | 873eb012 | ths | } |
1090 | 873eb012 | ths | |
1091 | 7a387fff | ths | void op_mfc0_intctl (void) |
1092 | 7a387fff | ths | { |
1093 | 9c2149c8 | ths | T0 = env->CP0_IntCtl; |
1094 | 7a387fff | ths | RETURN(); |
1095 | 7a387fff | ths | } |
1096 | 7a387fff | ths | |
1097 | 7a387fff | ths | void op_mfc0_srsctl (void) |
1098 | 7a387fff | ths | { |
1099 | 9c2149c8 | ths | T0 = env->CP0_SRSCtl; |
1100 | 9c2149c8 | ths | RETURN(); |
1101 | 9c2149c8 | ths | } |
1102 | 9c2149c8 | ths | |
1103 | 9c2149c8 | ths | void op_mfc0_srsmap (void) |
1104 | 9c2149c8 | ths | { |
1105 | 9c2149c8 | ths | T0 = env->CP0_SRSMap; |
1106 | 7a387fff | ths | RETURN(); |
1107 | 7a387fff | ths | } |
1108 | 7a387fff | ths | |
1109 | 873eb012 | ths | void op_mfc0_cause (void) |
1110 | 873eb012 | ths | { |
1111 | 9c2149c8 | ths | T0 = env->CP0_Cause; |
1112 | 873eb012 | ths | RETURN(); |
1113 | 873eb012 | ths | } |
1114 | 873eb012 | ths | |
1115 | 873eb012 | ths | void op_mfc0_epc (void) |
1116 | 873eb012 | ths | { |
1117 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EPC; |
1118 | 873eb012 | ths | RETURN(); |
1119 | 873eb012 | ths | } |
1120 | 873eb012 | ths | |
1121 | 873eb012 | ths | void op_mfc0_prid (void) |
1122 | 873eb012 | ths | { |
1123 | 9c2149c8 | ths | T0 = env->CP0_PRid; |
1124 | 873eb012 | ths | RETURN(); |
1125 | 873eb012 | ths | } |
1126 | 873eb012 | ths | |
1127 | 7a387fff | ths | void op_mfc0_ebase (void) |
1128 | 7a387fff | ths | { |
1129 | b29a0341 | ths | T0 = env->CP0_EBase; |
1130 | 7a387fff | ths | RETURN(); |
1131 | 7a387fff | ths | } |
1132 | 7a387fff | ths | |
1133 | 873eb012 | ths | void op_mfc0_config0 (void) |
1134 | 873eb012 | ths | { |
1135 | 9c2149c8 | ths | T0 = env->CP0_Config0; |
1136 | 873eb012 | ths | RETURN(); |
1137 | 873eb012 | ths | } |
1138 | 873eb012 | ths | |
1139 | 873eb012 | ths | void op_mfc0_config1 (void) |
1140 | 873eb012 | ths | { |
1141 | 9c2149c8 | ths | T0 = env->CP0_Config1; |
1142 | 873eb012 | ths | RETURN(); |
1143 | 873eb012 | ths | } |
1144 | 873eb012 | ths | |
1145 | 7a387fff | ths | void op_mfc0_config2 (void) |
1146 | 7a387fff | ths | { |
1147 | 9c2149c8 | ths | T0 = env->CP0_Config2; |
1148 | 7a387fff | ths | RETURN(); |
1149 | 7a387fff | ths | } |
1150 | 7a387fff | ths | |
1151 | 7a387fff | ths | void op_mfc0_config3 (void) |
1152 | 7a387fff | ths | { |
1153 | 9c2149c8 | ths | T0 = env->CP0_Config3; |
1154 | 7a387fff | ths | RETURN(); |
1155 | 7a387fff | ths | } |
1156 | 7a387fff | ths | |
1157 | e397ee33 | ths | void op_mfc0_config6 (void) |
1158 | e397ee33 | ths | { |
1159 | e397ee33 | ths | T0 = env->CP0_Config6; |
1160 | e397ee33 | ths | RETURN(); |
1161 | e397ee33 | ths | } |
1162 | e397ee33 | ths | |
1163 | e397ee33 | ths | void op_mfc0_config7 (void) |
1164 | e397ee33 | ths | { |
1165 | e397ee33 | ths | T0 = env->CP0_Config7; |
1166 | e397ee33 | ths | RETURN(); |
1167 | e397ee33 | ths | } |
1168 | e397ee33 | ths | |
1169 | 873eb012 | ths | void op_mfc0_lladdr (void) |
1170 | 873eb012 | ths | { |
1171 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_LLAddr >> 4;
|
1172 | 873eb012 | ths | RETURN(); |
1173 | 873eb012 | ths | } |
1174 | 873eb012 | ths | |
1175 | 7a387fff | ths | void op_mfc0_watchlo0 (void) |
1176 | 873eb012 | ths | { |
1177 | 5dc4b744 | ths | T0 = (int32_t)env->CP0_WatchLo; |
1178 | 873eb012 | ths | RETURN(); |
1179 | 873eb012 | ths | } |
1180 | 873eb012 | ths | |
1181 | 7a387fff | ths | void op_mfc0_watchhi0 (void) |
1182 | 873eb012 | ths | { |
1183 | 9c2149c8 | ths | T0 = env->CP0_WatchHi; |
1184 | 873eb012 | ths | RETURN(); |
1185 | 873eb012 | ths | } |
1186 | 873eb012 | ths | |
1187 | 7a387fff | ths | void op_mfc0_xcontext (void) |
1188 | 7a387fff | ths | { |
1189 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_XContext; |
1190 | 7a387fff | ths | RETURN(); |
1191 | 7a387fff | ths | } |
1192 | 7a387fff | ths | |
1193 | 7a387fff | ths | void op_mfc0_framemask (void) |
1194 | 7a387fff | ths | { |
1195 | 7a387fff | ths | T0 = env->CP0_Framemask; |
1196 | 7a387fff | ths | RETURN(); |
1197 | 7a387fff | ths | } |
1198 | 7a387fff | ths | |
1199 | 873eb012 | ths | void op_mfc0_debug (void) |
1200 | 873eb012 | ths | { |
1201 | 9c2149c8 | ths | T0 = env->CP0_Debug; |
1202 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
1203 | 873eb012 | ths | T0 |= 1 << CP0DB_DM;
|
1204 | 873eb012 | ths | RETURN(); |
1205 | 873eb012 | ths | } |
1206 | 873eb012 | ths | |
1207 | 873eb012 | ths | void op_mfc0_depc (void) |
1208 | 873eb012 | ths | { |
1209 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_DEPC; |
1210 | 873eb012 | ths | RETURN(); |
1211 | 873eb012 | ths | } |
1212 | 873eb012 | ths | |
1213 | 7a387fff | ths | void op_mfc0_performance0 (void) |
1214 | 7a387fff | ths | { |
1215 | 9c2149c8 | ths | T0 = env->CP0_Performance0; |
1216 | 7a387fff | ths | RETURN(); |
1217 | 7a387fff | ths | } |
1218 | 7a387fff | ths | |
1219 | 873eb012 | ths | void op_mfc0_taglo (void) |
1220 | 873eb012 | ths | { |
1221 | 9c2149c8 | ths | T0 = env->CP0_TagLo; |
1222 | 873eb012 | ths | RETURN(); |
1223 | 873eb012 | ths | } |
1224 | 873eb012 | ths | |
1225 | 873eb012 | ths | void op_mfc0_datalo (void) |
1226 | 873eb012 | ths | { |
1227 | 9c2149c8 | ths | T0 = env->CP0_DataLo; |
1228 | 873eb012 | ths | RETURN(); |
1229 | 873eb012 | ths | } |
1230 | 873eb012 | ths | |
1231 | 7a387fff | ths | void op_mfc0_taghi (void) |
1232 | 7a387fff | ths | { |
1233 | 9c2149c8 | ths | T0 = env->CP0_TagHi; |
1234 | 7a387fff | ths | RETURN(); |
1235 | 7a387fff | ths | } |
1236 | 7a387fff | ths | |
1237 | 7a387fff | ths | void op_mfc0_datahi (void) |
1238 | 7a387fff | ths | { |
1239 | 9c2149c8 | ths | T0 = env->CP0_DataHi; |
1240 | 7a387fff | ths | RETURN(); |
1241 | 7a387fff | ths | } |
1242 | 7a387fff | ths | |
1243 | 873eb012 | ths | void op_mfc0_errorepc (void) |
1244 | 873eb012 | ths | { |
1245 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_ErrorEPC; |
1246 | 873eb012 | ths | RETURN(); |
1247 | 873eb012 | ths | } |
1248 | 873eb012 | ths | |
1249 | 873eb012 | ths | void op_mfc0_desave (void) |
1250 | 873eb012 | ths | { |
1251 | 9c2149c8 | ths | T0 = env->CP0_DESAVE; |
1252 | 6af0bf9c | bellard | RETURN(); |
1253 | 6af0bf9c | bellard | } |
1254 | 6af0bf9c | bellard | |
1255 | 8c0fdd85 | ths | void op_mtc0_index (void) |
1256 | 6af0bf9c | bellard | { |
1257 | fcb4a419 | ths | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
|
1258 | 8c0fdd85 | ths | RETURN(); |
1259 | 8c0fdd85 | ths | } |
1260 | 8c0fdd85 | ths | |
1261 | 8c0fdd85 | ths | void op_mtc0_entrylo0 (void) |
1262 | 8c0fdd85 | ths | { |
1263 | 7a387fff | ths | /* Large physaddr not implemented */
|
1264 | 7a387fff | ths | /* 1k pages not implemented */
|
1265 | 9c2149c8 | ths | env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
|
1266 | 8c0fdd85 | ths | RETURN(); |
1267 | 8c0fdd85 | ths | } |
1268 | 8c0fdd85 | ths | |
1269 | 8c0fdd85 | ths | void op_mtc0_entrylo1 (void) |
1270 | 8c0fdd85 | ths | { |
1271 | 7a387fff | ths | /* Large physaddr not implemented */
|
1272 | 7a387fff | ths | /* 1k pages not implemented */
|
1273 | 9c2149c8 | ths | env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
|
1274 | 8c0fdd85 | ths | RETURN(); |
1275 | 8c0fdd85 | ths | } |
1276 | 8c0fdd85 | ths | |
1277 | 8c0fdd85 | ths | void op_mtc0_context (void) |
1278 | 8c0fdd85 | ths | { |
1279 | 534ce69f | ths | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
1280 | 8c0fdd85 | ths | RETURN(); |
1281 | 8c0fdd85 | ths | } |
1282 | 8c0fdd85 | ths | |
1283 | 8c0fdd85 | ths | void op_mtc0_pagemask (void) |
1284 | 8c0fdd85 | ths | { |
1285 | 7a387fff | ths | /* 1k pages not implemented */
|
1286 | 7a387fff | ths | env->CP0_PageMask = T0 & 0x1FFFE000;
|
1287 | 7a387fff | ths | RETURN(); |
1288 | 7a387fff | ths | } |
1289 | 7a387fff | ths | |
1290 | 7a387fff | ths | void op_mtc0_pagegrain (void) |
1291 | 7a387fff | ths | { |
1292 | 7a387fff | ths | /* SmartMIPS not implemented */
|
1293 | 7a387fff | ths | /* Large physaddr not implemented */
|
1294 | 7a387fff | ths | /* 1k pages not implemented */
|
1295 | 7a387fff | ths | env->CP0_PageGrain = 0;
|
1296 | 8c0fdd85 | ths | RETURN(); |
1297 | 8c0fdd85 | ths | } |
1298 | 8c0fdd85 | ths | |
1299 | 8c0fdd85 | ths | void op_mtc0_wired (void) |
1300 | 8c0fdd85 | ths | { |
1301 | fcb4a419 | ths | env->CP0_Wired = T0 % env->nb_tlb; |
1302 | 7a387fff | ths | RETURN(); |
1303 | 7a387fff | ths | } |
1304 | 7a387fff | ths | |
1305 | 7a387fff | ths | void op_mtc0_hwrena (void) |
1306 | 7a387fff | ths | { |
1307 | 7a387fff | ths | env->CP0_HWREna = T0 & 0x0000000F;
|
1308 | 8c0fdd85 | ths | RETURN(); |
1309 | 8c0fdd85 | ths | } |
1310 | 8c0fdd85 | ths | |
1311 | 8c0fdd85 | ths | void op_mtc0_count (void) |
1312 | 8c0fdd85 | ths | { |
1313 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
1314 | 8c0fdd85 | ths | RETURN(); |
1315 | 8c0fdd85 | ths | } |
1316 | 8c0fdd85 | ths | |
1317 | 8c0fdd85 | ths | void op_mtc0_entryhi (void) |
1318 | 8c0fdd85 | ths | { |
1319 | 0feef828 | ths | target_ulong old, val; |
1320 | 8c0fdd85 | ths | |
1321 | 7a387fff | ths | /* 1k pages not implemented */
|
1322 | 7a387fff | ths | /* Ignore MIPS64 TLB for now */
|
1323 | 925fd0f2 | ths | val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
|
1324 | 8c0fdd85 | ths | old = env->CP0_EntryHi; |
1325 | 8c0fdd85 | ths | env->CP0_EntryHi = val; |
1326 | 8c0fdd85 | ths | /* If the ASID changes, flush qemu's TLB. */
|
1327 | 8c0fdd85 | ths | if ((old & 0xFF) != (val & 0xFF)) |
1328 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
1329 | 8c0fdd85 | ths | RETURN(); |
1330 | 8c0fdd85 | ths | } |
1331 | 8c0fdd85 | ths | |
1332 | 8c0fdd85 | ths | void op_mtc0_compare (void) |
1333 | 8c0fdd85 | ths | { |
1334 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
1335 | 8c0fdd85 | ths | RETURN(); |
1336 | 8c0fdd85 | ths | } |
1337 | 8c0fdd85 | ths | |
1338 | 8c0fdd85 | ths | void op_mtc0_status (void) |
1339 | 8c0fdd85 | ths | { |
1340 | 4de9b249 | ths | uint32_t val, old; |
1341 | 5a5012ec | ths | uint32_t mask = env->Status_rw_bitmask; |
1342 | 8c0fdd85 | ths | |
1343 | 5a5012ec | ths | /* No reverse endianness, no MDMX/DSP, no 64bit ops,
|
1344 | 24c7b0e3 | ths | no 64bit addressing implemented. */
|
1345 | 5a5012ec | ths | val = (int32_t)T0 & mask; |
1346 | 8c0fdd85 | ths | old = env->CP0_Status; |
1347 | f41c52f1 | ths | if (!(val & (1 << CP0St_EXL)) && |
1348 | f41c52f1 | ths | !(val & (1 << CP0St_ERL)) &&
|
1349 | f41c52f1 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
1350 | f41c52f1 | ths | (val & (1 << CP0St_UM)))
|
1351 | f41c52f1 | ths | env->hflags |= MIPS_HFLAG_UM; |
1352 | 5a5012ec | ths | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1353 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
1354 | f41c52f1 | ths | CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
1355 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
1356 | 8c0fdd85 | ths | RETURN(); |
1357 | 8c0fdd85 | ths | } |
1358 | 8c0fdd85 | ths | |
1359 | 7a387fff | ths | void op_mtc0_intctl (void) |
1360 | 7a387fff | ths | { |
1361 | c090a8f4 | ths | /* vectored interrupts not implemented, timer on int 7,
|
1362 | c090a8f4 | ths | no performance counters. */
|
1363 | c090a8f4 | ths | env->CP0_IntCtl |= T0 & 0x000002e0;
|
1364 | 7a387fff | ths | RETURN(); |
1365 | 7a387fff | ths | } |
1366 | 7a387fff | ths | |
1367 | 7a387fff | ths | void op_mtc0_srsctl (void) |
1368 | 7a387fff | ths | { |
1369 | 7a387fff | ths | /* shadow registers not implemented */
|
1370 | 7a387fff | ths | env->CP0_SRSCtl = 0;
|
1371 | 7a387fff | ths | RETURN(); |
1372 | 7a387fff | ths | } |
1373 | 7a387fff | ths | |
1374 | 9c2149c8 | ths | void op_mtc0_srsmap (void) |
1375 | 9c2149c8 | ths | { |
1376 | 9c2149c8 | ths | /* shadow registers not implemented */
|
1377 | 9c2149c8 | ths | env->CP0_SRSMap = 0;
|
1378 | 9c2149c8 | ths | RETURN(); |
1379 | 9c2149c8 | ths | } |
1380 | 9c2149c8 | ths | |
1381 | 8c0fdd85 | ths | void op_mtc0_cause (void) |
1382 | 8c0fdd85 | ths | { |
1383 | 39d51eb8 | ths | uint32_t mask = 0x00C00300;
|
1384 | 39d51eb8 | ths | |
1385 | 39d51eb8 | ths | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
1386 | 39d51eb8 | ths | mask |= 1 << CP0Ca_DC;
|
1387 | 39d51eb8 | ths | |
1388 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
1389 | 8c0fdd85 | ths | |
1390 | 4de9b249 | ths | /* Handle the software interrupt as an hardware one, as they
|
1391 | 4de9b249 | ths | are very similar */
|
1392 | 4de9b249 | ths | if (T0 & CP0Ca_IP_mask) {
|
1393 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
1394 | 8c0fdd85 | ths | } |
1395 | 8c0fdd85 | ths | RETURN(); |
1396 | 8c0fdd85 | ths | } |
1397 | 8c0fdd85 | ths | |
1398 | 8c0fdd85 | ths | void op_mtc0_epc (void) |
1399 | 8c0fdd85 | ths | { |
1400 | 9c2149c8 | ths | env->CP0_EPC = (int32_t)T0; |
1401 | 8c0fdd85 | ths | RETURN(); |
1402 | 8c0fdd85 | ths | } |
1403 | 8c0fdd85 | ths | |
1404 | 7a387fff | ths | void op_mtc0_ebase (void) |
1405 | 7a387fff | ths | { |
1406 | 7a387fff | ths | /* vectored interrupts not implemented */
|
1407 | 7a387fff | ths | /* Multi-CPU not implemented */
|
1408 | b29a0341 | ths | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
1409 | 7a387fff | ths | RETURN(); |
1410 | 7a387fff | ths | } |
1411 | 7a387fff | ths | |
1412 | 8c0fdd85 | ths | void op_mtc0_config0 (void) |
1413 | 8c0fdd85 | ths | { |
1414 | 8c0fdd85 | ths | #if defined(MIPS_USES_R4K_TLB)
|
1415 | 7a387fff | ths | /* Fixed mapping MMU not implemented */
|
1416 | 7a387fff | ths | env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); |
1417 | 8c0fdd85 | ths | #else
|
1418 | 7a387fff | ths | env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001); |
1419 | 8c0fdd85 | ths | #endif
|
1420 | 8c0fdd85 | ths | RETURN(); |
1421 | 8c0fdd85 | ths | } |
1422 | 8c0fdd85 | ths | |
1423 | 7a387fff | ths | void op_mtc0_config2 (void) |
1424 | 7a387fff | ths | { |
1425 | 7a387fff | ths | /* tertiary/secondary caches not implemented */
|
1426 | 7a387fff | ths | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1427 | 7a387fff | ths | RETURN(); |
1428 | 7a387fff | ths | } |
1429 | 7a387fff | ths | |
1430 | 7a387fff | ths | void op_mtc0_watchlo0 (void) |
1431 | 8c0fdd85 | ths | { |
1432 | 4e7a4a4e | ths | /* Watch exceptions for instructions, data loads, data stores
|
1433 | 4e7a4a4e | ths | not implemented. */
|
1434 | 4e7a4a4e | ths | env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
|
1435 | 8c0fdd85 | ths | RETURN(); |
1436 | 8c0fdd85 | ths | } |
1437 | 8c0fdd85 | ths | |
1438 | 7a387fff | ths | void op_mtc0_watchhi0 (void) |
1439 | 8c0fdd85 | ths | { |
1440 | 4e7a4a4e | ths | env->CP0_WatchHi = (T0 & 0x40FF0FF8);
|
1441 | 4e7a4a4e | ths | env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
|
1442 | 8c0fdd85 | ths | RETURN(); |
1443 | 8c0fdd85 | ths | } |
1444 | 8c0fdd85 | ths | |
1445 | 7a387fff | ths | void op_mtc0_framemask (void) |
1446 | 7a387fff | ths | { |
1447 | 7a387fff | ths | env->CP0_Framemask = T0; /* XXX */
|
1448 | 7a387fff | ths | RETURN(); |
1449 | 7a387fff | ths | } |
1450 | 7a387fff | ths | |
1451 | 8c0fdd85 | ths | void op_mtc0_debug (void) |
1452 | 8c0fdd85 | ths | { |
1453 | 8c0fdd85 | ths | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
1454 | 8c0fdd85 | ths | if (T0 & (1 << CP0DB_DM)) |
1455 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_DM; |
1456 | 8c0fdd85 | ths | else
|
1457 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_DM; |
1458 | 8c0fdd85 | ths | RETURN(); |
1459 | 8c0fdd85 | ths | } |
1460 | 8c0fdd85 | ths | |
1461 | 8c0fdd85 | ths | void op_mtc0_depc (void) |
1462 | 8c0fdd85 | ths | { |
1463 | 9c2149c8 | ths | env->CP0_DEPC = (int32_t)T0; |
1464 | 8c0fdd85 | ths | RETURN(); |
1465 | 8c0fdd85 | ths | } |
1466 | 8c0fdd85 | ths | |
1467 | 7a387fff | ths | void op_mtc0_performance0 (void) |
1468 | 7a387fff | ths | { |
1469 | 7a387fff | ths | env->CP0_Performance0 = T0; /* XXX */
|
1470 | 7a387fff | ths | RETURN(); |
1471 | 7a387fff | ths | } |
1472 | 7a387fff | ths | |
1473 | 8c0fdd85 | ths | void op_mtc0_taglo (void) |
1474 | 8c0fdd85 | ths | { |
1475 | 9c2149c8 | ths | env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
1476 | 8c0fdd85 | ths | RETURN(); |
1477 | 8c0fdd85 | ths | } |
1478 | 8c0fdd85 | ths | |
1479 | 7a387fff | ths | void op_mtc0_datalo (void) |
1480 | 7a387fff | ths | { |
1481 | 7a387fff | ths | env->CP0_DataLo = T0; /* XXX */
|
1482 | 7a387fff | ths | RETURN(); |
1483 | 7a387fff | ths | } |
1484 | 7a387fff | ths | |
1485 | 7a387fff | ths | void op_mtc0_taghi (void) |
1486 | 7a387fff | ths | { |
1487 | 7a387fff | ths | env->CP0_TagHi = T0; /* XXX */
|
1488 | 7a387fff | ths | RETURN(); |
1489 | 7a387fff | ths | } |
1490 | 7a387fff | ths | |
1491 | 7a387fff | ths | void op_mtc0_datahi (void) |
1492 | 7a387fff | ths | { |
1493 | 7a387fff | ths | env->CP0_DataHi = T0; /* XXX */
|
1494 | 7a387fff | ths | RETURN(); |
1495 | 7a387fff | ths | } |
1496 | 7a387fff | ths | |
1497 | 8c0fdd85 | ths | void op_mtc0_errorepc (void) |
1498 | 8c0fdd85 | ths | { |
1499 | 9c2149c8 | ths | env->CP0_ErrorEPC = (int32_t)T0; |
1500 | 8c0fdd85 | ths | RETURN(); |
1501 | 8c0fdd85 | ths | } |
1502 | 8c0fdd85 | ths | |
1503 | 8c0fdd85 | ths | void op_mtc0_desave (void) |
1504 | 8c0fdd85 | ths | { |
1505 | 8c0fdd85 | ths | env->CP0_DESAVE = T0; |
1506 | 6af0bf9c | bellard | RETURN(); |
1507 | 6af0bf9c | bellard | } |
1508 | 6af0bf9c | bellard | |
1509 | 534ce69f | ths | #ifdef TARGET_MIPS64
|
1510 | 9c2149c8 | ths | void op_dmfc0_entrylo0 (void) |
1511 | 9c2149c8 | ths | { |
1512 | 9c2149c8 | ths | T0 = env->CP0_EntryLo0; |
1513 | 9c2149c8 | ths | RETURN(); |
1514 | 9c2149c8 | ths | } |
1515 | 9c2149c8 | ths | |
1516 | 9c2149c8 | ths | void op_dmfc0_entrylo1 (void) |
1517 | 9c2149c8 | ths | { |
1518 | 9c2149c8 | ths | T0 = env->CP0_EntryLo1; |
1519 | 9c2149c8 | ths | RETURN(); |
1520 | 9c2149c8 | ths | } |
1521 | 9c2149c8 | ths | |
1522 | 9c2149c8 | ths | void op_dmfc0_context (void) |
1523 | 9c2149c8 | ths | { |
1524 | 9c2149c8 | ths | T0 = env->CP0_Context; |
1525 | 9c2149c8 | ths | RETURN(); |
1526 | 9c2149c8 | ths | } |
1527 | 9c2149c8 | ths | |
1528 | 9c2149c8 | ths | void op_dmfc0_badvaddr (void) |
1529 | 9c2149c8 | ths | { |
1530 | 9c2149c8 | ths | T0 = env->CP0_BadVAddr; |
1531 | 9c2149c8 | ths | RETURN(); |
1532 | 9c2149c8 | ths | } |
1533 | 9c2149c8 | ths | |
1534 | 9c2149c8 | ths | void op_dmfc0_entryhi (void) |
1535 | 9c2149c8 | ths | { |
1536 | 9c2149c8 | ths | T0 = env->CP0_EntryHi; |
1537 | 9c2149c8 | ths | RETURN(); |
1538 | 9c2149c8 | ths | } |
1539 | 9c2149c8 | ths | |
1540 | 9c2149c8 | ths | void op_dmfc0_epc (void) |
1541 | 9c2149c8 | ths | { |
1542 | 9c2149c8 | ths | T0 = env->CP0_EPC; |
1543 | 9c2149c8 | ths | RETURN(); |
1544 | 9c2149c8 | ths | } |
1545 | 9c2149c8 | ths | |
1546 | 9c2149c8 | ths | void op_dmfc0_lladdr (void) |
1547 | 9c2149c8 | ths | { |
1548 | 9c2149c8 | ths | T0 = env->CP0_LLAddr >> 4;
|
1549 | 9c2149c8 | ths | RETURN(); |
1550 | 9c2149c8 | ths | } |
1551 | 9c2149c8 | ths | |
1552 | 9c2149c8 | ths | void op_dmfc0_watchlo0 (void) |
1553 | 9c2149c8 | ths | { |
1554 | 9c2149c8 | ths | T0 = env->CP0_WatchLo; |
1555 | 9c2149c8 | ths | RETURN(); |
1556 | 9c2149c8 | ths | } |
1557 | 9c2149c8 | ths | |
1558 | 9c2149c8 | ths | void op_dmfc0_xcontext (void) |
1559 | 9c2149c8 | ths | { |
1560 | 9c2149c8 | ths | T0 = env->CP0_XContext; |
1561 | 9c2149c8 | ths | RETURN(); |
1562 | 9c2149c8 | ths | } |
1563 | 9c2149c8 | ths | |
1564 | 9c2149c8 | ths | void op_dmfc0_depc (void) |
1565 | 9c2149c8 | ths | { |
1566 | 9c2149c8 | ths | T0 = env->CP0_DEPC; |
1567 | 9c2149c8 | ths | RETURN(); |
1568 | 9c2149c8 | ths | } |
1569 | 9c2149c8 | ths | |
1570 | 9c2149c8 | ths | void op_dmfc0_errorepc (void) |
1571 | 9c2149c8 | ths | { |
1572 | 9c2149c8 | ths | T0 = env->CP0_ErrorEPC; |
1573 | 9c2149c8 | ths | RETURN(); |
1574 | 9c2149c8 | ths | } |
1575 | 9c2149c8 | ths | |
1576 | 9c2149c8 | ths | void op_dmtc0_entrylo0 (void) |
1577 | 9c2149c8 | ths | { |
1578 | 9c2149c8 | ths | /* Large physaddr not implemented */
|
1579 | 9c2149c8 | ths | /* 1k pages not implemented */
|
1580 | 9c2149c8 | ths | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
1581 | 9c2149c8 | ths | RETURN(); |
1582 | 9c2149c8 | ths | } |
1583 | 9c2149c8 | ths | |
1584 | 9c2149c8 | ths | void op_dmtc0_entrylo1 (void) |
1585 | 9c2149c8 | ths | { |
1586 | 9c2149c8 | ths | /* Large physaddr not implemented */
|
1587 | 9c2149c8 | ths | /* 1k pages not implemented */
|
1588 | 9c2149c8 | ths | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
1589 | 9c2149c8 | ths | RETURN(); |
1590 | 9c2149c8 | ths | } |
1591 | 9c2149c8 | ths | |
1592 | 9c2149c8 | ths | void op_dmtc0_context (void) |
1593 | 9c2149c8 | ths | { |
1594 | 534ce69f | ths | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
1595 | 9c2149c8 | ths | RETURN(); |
1596 | 9c2149c8 | ths | } |
1597 | 9c2149c8 | ths | |
1598 | 9c2149c8 | ths | void op_dmtc0_epc (void) |
1599 | 9c2149c8 | ths | { |
1600 | 9c2149c8 | ths | env->CP0_EPC = T0; |
1601 | 9c2149c8 | ths | RETURN(); |
1602 | 9c2149c8 | ths | } |
1603 | 9c2149c8 | ths | |
1604 | 9c2149c8 | ths | void op_dmtc0_watchlo0 (void) |
1605 | 9c2149c8 | ths | { |
1606 | 4e7a4a4e | ths | /* Watch exceptions for instructions, data loads, data stores
|
1607 | 4e7a4a4e | ths | not implemented. */
|
1608 | 4e7a4a4e | ths | env->CP0_WatchLo = T0 & ~0x7;
|
1609 | 9c2149c8 | ths | RETURN(); |
1610 | 9c2149c8 | ths | } |
1611 | 9c2149c8 | ths | |
1612 | 9c2149c8 | ths | void op_dmtc0_xcontext (void) |
1613 | 9c2149c8 | ths | { |
1614 | 534ce69f | ths | env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff); |
1615 | 9c2149c8 | ths | RETURN(); |
1616 | 9c2149c8 | ths | } |
1617 | 9c2149c8 | ths | |
1618 | 9c2149c8 | ths | void op_dmtc0_depc (void) |
1619 | 9c2149c8 | ths | { |
1620 | 9c2149c8 | ths | env->CP0_DEPC = T0; |
1621 | 9c2149c8 | ths | RETURN(); |
1622 | 9c2149c8 | ths | } |
1623 | 9c2149c8 | ths | |
1624 | 9c2149c8 | ths | void op_dmtc0_errorepc (void) |
1625 | 9c2149c8 | ths | { |
1626 | 9c2149c8 | ths | env->CP0_ErrorEPC = T0; |
1627 | 9c2149c8 | ths | RETURN(); |
1628 | 9c2149c8 | ths | } |
1629 | 534ce69f | ths | #endif /* TARGET_MIPS64 */ |
1630 | 9c2149c8 | ths | |
1631 | 5a5012ec | ths | /* CP1 functions */
|
1632 | 6ea83fed | bellard | #if 0
|
1633 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
1634 | 6ea83fed | bellard | #else
|
1635 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() do { } while(0) |
1636 | 6ea83fed | bellard | #endif
|
1637 | 6ea83fed | bellard | |
1638 | 24c7b0e3 | ths | void op_cp0_enabled(void) |
1639 | 24c7b0e3 | ths | { |
1640 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_CU0)) && |
1641 | 24c7b0e3 | ths | (env->hflags & MIPS_HFLAG_UM)) { |
1642 | 1579a72e | ths | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
|
1643 | 24c7b0e3 | ths | } |
1644 | 24c7b0e3 | ths | RETURN(); |
1645 | 24c7b0e3 | ths | } |
1646 | 24c7b0e3 | ths | |
1647 | 6ea83fed | bellard | void op_cp1_enabled(void) |
1648 | 6ea83fed | bellard | { |
1649 | 6ea83fed | bellard | if (!(env->CP0_Status & (1 << CP0St_CU1))) { |
1650 | 1579a72e | ths | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
|
1651 | 6ea83fed | bellard | } |
1652 | 6ea83fed | bellard | RETURN(); |
1653 | 6ea83fed | bellard | } |
1654 | 6ea83fed | bellard | |
1655 | 6ea83fed | bellard | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
1656 | 6ea83fed | bellard | unsigned int ieee_rm[] = { |
1657 | 6ea83fed | bellard | float_round_nearest_even, |
1658 | 6ea83fed | bellard | float_round_to_zero, |
1659 | 6ea83fed | bellard | float_round_up, |
1660 | 6ea83fed | bellard | float_round_down |
1661 | 6ea83fed | bellard | }; |
1662 | 6ea83fed | bellard | |
1663 | 6ea83fed | bellard | #define RESTORE_ROUNDING_MODE \
|
1664 | 6ea83fed | bellard | set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
|
1665 | 6ea83fed | bellard | |
1666 | 09c69c5b | ths | inline char ieee_ex_to_mips(char xcpt) |
1667 | 6ea83fed | bellard | { |
1668 | 09c69c5b | ths | return (xcpt & float_flag_inexact) >> 5 | |
1669 | 09c69c5b | ths | (xcpt & float_flag_underflow) >> 3 |
|
1670 | 09c69c5b | ths | (xcpt & float_flag_overflow) >> 1 |
|
1671 | 09c69c5b | ths | (xcpt & float_flag_divbyzero) << 1 |
|
1672 | 09c69c5b | ths | (xcpt & float_flag_invalid) << 4;
|
1673 | 5a5012ec | ths | } |
1674 | 6ea83fed | bellard | |
1675 | 09c69c5b | ths | inline char mips_ex_to_ieee(char xcpt) |
1676 | 5a5012ec | ths | { |
1677 | 09c69c5b | ths | return (xcpt & FP_INEXACT) << 5 | |
1678 | 09c69c5b | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
1679 | 09c69c5b | ths | (xcpt & FP_OVERFLOW) << 1 |
|
1680 | 09c69c5b | ths | (xcpt & FP_DIV0) >> 1 |
|
1681 | 09c69c5b | ths | (xcpt & FP_INVALID) >> 4;
|
1682 | 5a5012ec | ths | } |
1683 | 6ea83fed | bellard | |
1684 | 5a5012ec | ths | inline void update_fcr31(void) |
1685 | 5a5012ec | ths | { |
1686 | 5a5012ec | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fp_status));
|
1687 | 5a5012ec | ths | |
1688 | 5a5012ec | ths | SET_FP_CAUSE(env->fcr31, tmp); |
1689 | 5a5012ec | ths | if (GET_FP_ENABLE(env->fcr31) & tmp)
|
1690 | 5a5012ec | ths | CALL_FROM_TB1(do_raise_exception, EXCP_FPE); |
1691 | 5a5012ec | ths | else
|
1692 | 5a5012ec | ths | UPDATE_FP_FLAGS(env->fcr31, tmp); |
1693 | 5a5012ec | ths | } |
1694 | 5a5012ec | ths | |
1695 | 5a5012ec | ths | |
1696 | 5a5012ec | ths | void op_cfc1 (void) |
1697 | 5a5012ec | ths | { |
1698 | 5a5012ec | ths | switch (T1) {
|
1699 | 5a5012ec | ths | case 0: |
1700 | 5a5012ec | ths | T0 = (int32_t)env->fcr0; |
1701 | 5a5012ec | ths | break;
|
1702 | 5a5012ec | ths | case 25: |
1703 | 5a5012ec | ths | T0 = ((env->fcr31 >> 24) & 0xfe) | ((env->fcr31 >> 23) & 0x1); |
1704 | 5a5012ec | ths | break;
|
1705 | 5a5012ec | ths | case 26: |
1706 | 5a5012ec | ths | T0 = env->fcr31 & 0x0003f07c;
|
1707 | 5a5012ec | ths | break;
|
1708 | 5a5012ec | ths | case 28: |
1709 | 5a5012ec | ths | T0 = (env->fcr31 & 0x00000f83) | ((env->fcr31 >> 22) & 0x4); |
1710 | 5a5012ec | ths | break;
|
1711 | 5a5012ec | ths | default:
|
1712 | 5a5012ec | ths | T0 = (int32_t)env->fcr31; |
1713 | 5a5012ec | ths | break;
|
1714 | 5a5012ec | ths | } |
1715 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1716 | 5a5012ec | ths | RETURN(); |
1717 | 5a5012ec | ths | } |
1718 | 5a5012ec | ths | |
1719 | 5a5012ec | ths | void op_ctc1 (void) |
1720 | 5a5012ec | ths | { |
1721 | 5a5012ec | ths | switch(T1) {
|
1722 | 5a5012ec | ths | case 25: |
1723 | 5a5012ec | ths | if (T0 & 0xffffff00) |
1724 | 5a5012ec | ths | goto leave;
|
1725 | 5a5012ec | ths | env->fcr31 = (env->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
1726 | 5a5012ec | ths | ((T0 & 0x1) << 23); |
1727 | 5a5012ec | ths | break;
|
1728 | 5a5012ec | ths | case 26: |
1729 | 5a5012ec | ths | if (T0 & 0x007c0000) |
1730 | 5a5012ec | ths | goto leave;
|
1731 | 5a5012ec | ths | env->fcr31 = (env->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
1732 | 5a5012ec | ths | break;
|
1733 | 5a5012ec | ths | case 28: |
1734 | 5a5012ec | ths | if (T0 & 0x007c0000) |
1735 | 5a5012ec | ths | goto leave;
|
1736 | 5a5012ec | ths | env->fcr31 = (env->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
1737 | 5a5012ec | ths | ((T0 & 0x4) << 22); |
1738 | 5a5012ec | ths | break;
|
1739 | 5a5012ec | ths | case 31: |
1740 | 5a5012ec | ths | if (T0 & 0x007c0000) |
1741 | 5a5012ec | ths | goto leave;
|
1742 | 5a5012ec | ths | env->fcr31 = T0; |
1743 | 5a5012ec | ths | break;
|
1744 | 5a5012ec | ths | default:
|
1745 | 5a5012ec | ths | goto leave;
|
1746 | 6ea83fed | bellard | } |
1747 | 5a5012ec | ths | /* set rounding mode */
|
1748 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
1749 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1750 | 5a5012ec | ths | if ((GET_FP_ENABLE(env->fcr31) | 0x20) & GET_FP_CAUSE(env->fcr31)) |
1751 | 5a5012ec | ths | CALL_FROM_TB1(do_raise_exception, EXCP_FPE); |
1752 | 5a5012ec | ths | leave:
|
1753 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1754 | 6ea83fed | bellard | RETURN(); |
1755 | 6ea83fed | bellard | } |
1756 | 6ea83fed | bellard | |
1757 | 6ea83fed | bellard | void op_mfc1 (void) |
1758 | 6ea83fed | bellard | { |
1759 | 6ea83fed | bellard | T0 = WT0; |
1760 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1761 | 6ea83fed | bellard | RETURN(); |
1762 | 6ea83fed | bellard | } |
1763 | 6ea83fed | bellard | |
1764 | 6ea83fed | bellard | void op_mtc1 (void) |
1765 | 6ea83fed | bellard | { |
1766 | 6ea83fed | bellard | WT0 = T0; |
1767 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1768 | 6ea83fed | bellard | RETURN(); |
1769 | 6ea83fed | bellard | } |
1770 | 6ea83fed | bellard | |
1771 | 5a5012ec | ths | void op_dmfc1 (void) |
1772 | 5a5012ec | ths | { |
1773 | 5a5012ec | ths | T0 = DT0; |
1774 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1775 | 5a5012ec | ths | RETURN(); |
1776 | 5a5012ec | ths | } |
1777 | 5a5012ec | ths | |
1778 | 5a5012ec | ths | void op_dmtc1 (void) |
1779 | 5a5012ec | ths | { |
1780 | 5a5012ec | ths | DT0 = T0; |
1781 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1782 | 5a5012ec | ths | RETURN(); |
1783 | 5a5012ec | ths | } |
1784 | 5a5012ec | ths | |
1785 | 5a5012ec | ths | void op_mfhc1 (void) |
1786 | 5a5012ec | ths | { |
1787 | 5a5012ec | ths | T0 = WTH0; |
1788 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1789 | 5a5012ec | ths | RETURN(); |
1790 | 5a5012ec | ths | } |
1791 | 5a5012ec | ths | |
1792 | 5a5012ec | ths | void op_mthc1 (void) |
1793 | 5a5012ec | ths | { |
1794 | 5a5012ec | ths | WTH0 = T0; |
1795 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1796 | 5a5012ec | ths | RETURN(); |
1797 | 5a5012ec | ths | } |
1798 | 5a5012ec | ths | |
1799 | 6ea83fed | bellard | /* Float support.
|
1800 | 6ea83fed | bellard | Single precition routines have a "s" suffix, double precision a
|
1801 | 5a5012ec | ths | "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
|
1802 | 5a5012ec | ths | paired single lowwer "pl", paired single upper "pu". */
|
1803 | 6ea83fed | bellard | |
1804 | 6ea83fed | bellard | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
1805 | 6ea83fed | bellard | |
1806 | dd016883 | bellard | FLOAT_OP(cvtd, s) |
1807 | dd016883 | bellard | { |
1808 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1809 | 00a709c7 | ths | FDT2 = float32_to_float64(FST0, &env->fp_status); |
1810 | 5a5012ec | ths | update_fcr31(); |
1811 | dd016883 | bellard | DEBUG_FPU_STATE(); |
1812 | dd016883 | bellard | RETURN(); |
1813 | dd016883 | bellard | } |
1814 | 6ea83fed | bellard | FLOAT_OP(cvtd, w) |
1815 | 6ea83fed | bellard | { |
1816 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1817 | 6ea83fed | bellard | FDT2 = int32_to_float64(WT0, &env->fp_status); |
1818 | 5a5012ec | ths | update_fcr31(); |
1819 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1820 | 5a5012ec | ths | RETURN(); |
1821 | 5a5012ec | ths | } |
1822 | 5a5012ec | ths | FLOAT_OP(cvtd, l) |
1823 | 5a5012ec | ths | { |
1824 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1825 | 5a5012ec | ths | FDT2 = int64_to_float64(DT0, &env->fp_status); |
1826 | 5a5012ec | ths | update_fcr31(); |
1827 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1828 | 5a5012ec | ths | RETURN(); |
1829 | 5a5012ec | ths | } |
1830 | 5a5012ec | ths | FLOAT_OP(cvtl, d) |
1831 | 5a5012ec | ths | { |
1832 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1833 | 5a5012ec | ths | DT2 = float64_to_int64(FDT0, &env->fp_status); |
1834 | 5a5012ec | ths | update_fcr31(); |
1835 | 5a5012ec | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1836 | 5a5012ec | ths | DT2 = 0x7fffffffffffffffULL;
|
1837 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1838 | 5a5012ec | ths | RETURN(); |
1839 | 5a5012ec | ths | } |
1840 | 5a5012ec | ths | FLOAT_OP(cvtl, s) |
1841 | 5a5012ec | ths | { |
1842 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1843 | 5a5012ec | ths | DT2 = float32_to_int64(FST0, &env->fp_status); |
1844 | 5a5012ec | ths | update_fcr31(); |
1845 | 5a5012ec | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1846 | 5a5012ec | ths | DT2 = 0x7fffffffffffffffULL;
|
1847 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1848 | 5a5012ec | ths | RETURN(); |
1849 | 5a5012ec | ths | } |
1850 | 5a5012ec | ths | FLOAT_OP(cvtps, s) |
1851 | 5a5012ec | ths | { |
1852 | 5a5012ec | ths | WT2 = WT0; |
1853 | 5a5012ec | ths | WTH2 = WT1; |
1854 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1855 | 5a5012ec | ths | RETURN(); |
1856 | 5a5012ec | ths | } |
1857 | 5a5012ec | ths | FLOAT_OP(cvtps, pw) |
1858 | 5a5012ec | ths | { |
1859 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1860 | 5a5012ec | ths | FST2 = int32_to_float32(WT0, &env->fp_status); |
1861 | 5a5012ec | ths | FSTH2 = int32_to_float32(WTH0, &env->fp_status); |
1862 | 5a5012ec | ths | update_fcr31(); |
1863 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1864 | 5a5012ec | ths | RETURN(); |
1865 | 5a5012ec | ths | } |
1866 | 5a5012ec | ths | FLOAT_OP(cvtpw, ps) |
1867 | 5a5012ec | ths | { |
1868 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1869 | 5a5012ec | ths | WT2 = float32_to_int32(FST0, &env->fp_status); |
1870 | 5a5012ec | ths | WTH2 = float32_to_int32(FSTH0, &env->fp_status); |
1871 | 5a5012ec | ths | update_fcr31(); |
1872 | 5a5012ec | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1873 | 5a5012ec | ths | WT2 = 0x7fffffff;
|
1874 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1875 | 6ea83fed | bellard | RETURN(); |
1876 | 6ea83fed | bellard | } |
1877 | dd016883 | bellard | FLOAT_OP(cvts, d) |
1878 | dd016883 | bellard | { |
1879 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1880 | 417f38f0 | pbrook | FST2 = float64_to_float32(FDT0, &env->fp_status); |
1881 | 5a5012ec | ths | update_fcr31(); |
1882 | dd016883 | bellard | DEBUG_FPU_STATE(); |
1883 | dd016883 | bellard | RETURN(); |
1884 | dd016883 | bellard | } |
1885 | 6ea83fed | bellard | FLOAT_OP(cvts, w) |
1886 | 6ea83fed | bellard | { |
1887 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1888 | 6ea83fed | bellard | FST2 = int32_to_float32(WT0, &env->fp_status); |
1889 | 5a5012ec | ths | update_fcr31(); |
1890 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1891 | 5a5012ec | ths | RETURN(); |
1892 | 5a5012ec | ths | } |
1893 | 5a5012ec | ths | FLOAT_OP(cvts, l) |
1894 | 5a5012ec | ths | { |
1895 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1896 | 5a5012ec | ths | FST2 = int64_to_float32(DT0, &env->fp_status); |
1897 | 5a5012ec | ths | update_fcr31(); |
1898 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1899 | 5a5012ec | ths | RETURN(); |
1900 | 5a5012ec | ths | } |
1901 | 5a5012ec | ths | FLOAT_OP(cvts, pl) |
1902 | 5a5012ec | ths | { |
1903 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1904 | 5a5012ec | ths | WT2 = WT0; |
1905 | 5a5012ec | ths | update_fcr31(); |
1906 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1907 | 5a5012ec | ths | RETURN(); |
1908 | 5a5012ec | ths | } |
1909 | 5a5012ec | ths | FLOAT_OP(cvts, pu) |
1910 | 5a5012ec | ths | { |
1911 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1912 | 5a5012ec | ths | WT2 = WTH0; |
1913 | 5a5012ec | ths | update_fcr31(); |
1914 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1915 | 6ea83fed | bellard | RETURN(); |
1916 | 6ea83fed | bellard | } |
1917 | 6ea83fed | bellard | FLOAT_OP(cvtw, s) |
1918 | 6ea83fed | bellard | { |
1919 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1920 | 6ea83fed | bellard | WT2 = float32_to_int32(FST0, &env->fp_status); |
1921 | 5a5012ec | ths | update_fcr31(); |
1922 | 5a5012ec | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1923 | 5a5012ec | ths | WT2 = 0x7fffffff;
|
1924 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1925 | 6ea83fed | bellard | RETURN(); |
1926 | 6ea83fed | bellard | } |
1927 | 6ea83fed | bellard | FLOAT_OP(cvtw, d) |
1928 | 6ea83fed | bellard | { |
1929 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status);
|
1930 | 6ea83fed | bellard | WT2 = float64_to_int32(FDT0, &env->fp_status); |
1931 | 5a5012ec | ths | update_fcr31(); |
1932 | 5a5012ec | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1933 | 5a5012ec | ths | WT2 = 0x7fffffff;
|
1934 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1935 | 5a5012ec | ths | RETURN(); |
1936 | 5a5012ec | ths | } |
1937 | 5a5012ec | ths | |
1938 | 5a5012ec | ths | FLOAT_OP(pll, ps) |
1939 | 5a5012ec | ths | { |
1940 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WT1;
|
1941 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1942 | 5a5012ec | ths | RETURN(); |
1943 | 5a5012ec | ths | } |
1944 | 5a5012ec | ths | FLOAT_OP(plu, ps) |
1945 | 5a5012ec | ths | { |
1946 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WTH1;
|
1947 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1948 | 5a5012ec | ths | RETURN(); |
1949 | 5a5012ec | ths | } |
1950 | 5a5012ec | ths | FLOAT_OP(pul, ps) |
1951 | 5a5012ec | ths | { |
1952 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WT1;
|
1953 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1954 | 5a5012ec | ths | RETURN(); |
1955 | 5a5012ec | ths | } |
1956 | 5a5012ec | ths | FLOAT_OP(puu, ps) |
1957 | 5a5012ec | ths | { |
1958 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WTH1;
|
1959 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1960 | 6ea83fed | bellard | RETURN(); |
1961 | 6ea83fed | bellard | } |
1962 | 6ea83fed | bellard | |
1963 | 5a5012ec | ths | FLOAT_OP(roundl, d) |
1964 | 5a5012ec | ths | { |
1965 | 5a5012ec | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1966 | 5a5012ec | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
1967 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
1968 | 5a1e8ffb | ths | update_fcr31(); |
1969 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1970 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
1971 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1972 | 5a5012ec | ths | RETURN(); |
1973 | 5a5012ec | ths | } |
1974 | 5a5012ec | ths | FLOAT_OP(roundl, s) |
1975 | 5a5012ec | ths | { |
1976 | 5a5012ec | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1977 | 5a5012ec | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
1978 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
1979 | 5a1e8ffb | ths | update_fcr31(); |
1980 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1981 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
1982 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
1983 | 5a5012ec | ths | RETURN(); |
1984 | 5a5012ec | ths | } |
1985 | 6ea83fed | bellard | FLOAT_OP(roundw, d) |
1986 | 6ea83fed | bellard | { |
1987 | 6ea83fed | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1988 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
1989 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1990 | 5a1e8ffb | ths | update_fcr31(); |
1991 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1992 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
1993 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1994 | 6ea83fed | bellard | RETURN(); |
1995 | 6ea83fed | bellard | } |
1996 | 6ea83fed | bellard | FLOAT_OP(roundw, s) |
1997 | 6ea83fed | bellard | { |
1998 | 6ea83fed | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1999 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
2000 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
2001 | 5a1e8ffb | ths | update_fcr31(); |
2002 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2003 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2004 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2005 | 6ea83fed | bellard | RETURN(); |
2006 | 6ea83fed | bellard | } |
2007 | 6ea83fed | bellard | |
2008 | 5a5012ec | ths | FLOAT_OP(truncl, d) |
2009 | 5a5012ec | ths | { |
2010 | 5a5012ec | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status); |
2011 | 5a1e8ffb | ths | update_fcr31(); |
2012 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2013 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2014 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2015 | 5a5012ec | ths | RETURN(); |
2016 | 5a5012ec | ths | } |
2017 | 5a5012ec | ths | FLOAT_OP(truncl, s) |
2018 | 5a5012ec | ths | { |
2019 | 5a5012ec | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status); |
2020 | 5a1e8ffb | ths | update_fcr31(); |
2021 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2022 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2023 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2024 | 5a5012ec | ths | RETURN(); |
2025 | 5a5012ec | ths | } |
2026 | 6ea83fed | bellard | FLOAT_OP(truncw, d) |
2027 | 6ea83fed | bellard | { |
2028 | 6ea83fed | bellard | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
2029 | 5a1e8ffb | ths | update_fcr31(); |
2030 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2031 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2032 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2033 | 6ea83fed | bellard | RETURN(); |
2034 | 6ea83fed | bellard | } |
2035 | 6ea83fed | bellard | FLOAT_OP(truncw, s) |
2036 | 6ea83fed | bellard | { |
2037 | 6ea83fed | bellard | WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
2038 | 5a1e8ffb | ths | update_fcr31(); |
2039 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2040 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2041 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2042 | 6ea83fed | bellard | RETURN(); |
2043 | 6ea83fed | bellard | } |
2044 | 6ea83fed | bellard | |
2045 | 5a5012ec | ths | FLOAT_OP(ceill, d) |
2046 | 5a5012ec | ths | { |
2047 | 5a5012ec | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
2048 | 5a5012ec | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
2049 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
2050 | 5a1e8ffb | ths | update_fcr31(); |
2051 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2052 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2053 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2054 | 5a5012ec | ths | RETURN(); |
2055 | 5a5012ec | ths | } |
2056 | 5a5012ec | ths | FLOAT_OP(ceill, s) |
2057 | 5a5012ec | ths | { |
2058 | 5a5012ec | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
2059 | 5a5012ec | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
2060 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
2061 | 5a1e8ffb | ths | update_fcr31(); |
2062 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2063 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2064 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2065 | 5a5012ec | ths | RETURN(); |
2066 | 5a5012ec | ths | } |
2067 | 6ea83fed | bellard | FLOAT_OP(ceilw, d) |
2068 | 6ea83fed | bellard | { |
2069 | 6ea83fed | bellard | set_float_rounding_mode(float_round_up, &env->fp_status); |
2070 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
2071 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
2072 | 5a1e8ffb | ths | update_fcr31(); |
2073 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2074 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2075 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2076 | 6ea83fed | bellard | RETURN(); |
2077 | 6ea83fed | bellard | } |
2078 | 6ea83fed | bellard | FLOAT_OP(ceilw, s) |
2079 | 6ea83fed | bellard | { |
2080 | 6ea83fed | bellard | set_float_rounding_mode(float_round_up, &env->fp_status); |
2081 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
2082 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
2083 | 5a1e8ffb | ths | update_fcr31(); |
2084 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2085 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2086 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2087 | 6ea83fed | bellard | RETURN(); |
2088 | 6ea83fed | bellard | } |
2089 | 6ea83fed | bellard | |
2090 | 5a5012ec | ths | FLOAT_OP(floorl, d) |
2091 | 5a5012ec | ths | { |
2092 | 5a5012ec | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
2093 | 5a5012ec | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
2094 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
2095 | 5a1e8ffb | ths | update_fcr31(); |
2096 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2097 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2098 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2099 | 5a5012ec | ths | RETURN(); |
2100 | 5a5012ec | ths | } |
2101 | 5a5012ec | ths | FLOAT_OP(floorl, s) |
2102 | 5a5012ec | ths | { |
2103 | 5a5012ec | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
2104 | 5a5012ec | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
2105 | 5a5012ec | ths | RESTORE_ROUNDING_MODE; |
2106 | 5a1e8ffb | ths | update_fcr31(); |
2107 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2108 | 5a1e8ffb | ths | DT2 = 0x7fffffffffffffffULL;
|
2109 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2110 | 5a5012ec | ths | RETURN(); |
2111 | 5a5012ec | ths | } |
2112 | 6ea83fed | bellard | FLOAT_OP(floorw, d) |
2113 | 6ea83fed | bellard | { |
2114 | 6ea83fed | bellard | set_float_rounding_mode(float_round_down, &env->fp_status); |
2115 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
2116 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
2117 | 5a1e8ffb | ths | update_fcr31(); |
2118 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2119 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2120 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2121 | 6ea83fed | bellard | RETURN(); |
2122 | 6ea83fed | bellard | } |
2123 | 6ea83fed | bellard | FLOAT_OP(floorw, s) |
2124 | 6ea83fed | bellard | { |
2125 | 6ea83fed | bellard | set_float_rounding_mode(float_round_down, &env->fp_status); |
2126 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
2127 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
2128 | 5a1e8ffb | ths | update_fcr31(); |
2129 | 5a1e8ffb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2130 | 5a1e8ffb | ths | WT2 = 0x7fffffff;
|
2131 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2132 | 6ea83fed | bellard | RETURN(); |
2133 | 6ea83fed | bellard | } |
2134 | 6ea83fed | bellard | |
2135 | 5a5012ec | ths | FLOAT_OP(movf, d) |
2136 | 5a5012ec | ths | { |
2137 | 5a5012ec | ths | if (!(env->fcr31 & PARAM1))
|
2138 | 5a5012ec | ths | DT2 = DT0; |
2139 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2140 | 5a5012ec | ths | RETURN(); |
2141 | 5a5012ec | ths | } |
2142 | 5a5012ec | ths | FLOAT_OP(movf, s) |
2143 | 5a5012ec | ths | { |
2144 | 5a5012ec | ths | if (!(env->fcr31 & PARAM1))
|
2145 | 5a5012ec | ths | WT2 = WT0; |
2146 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2147 | 5a5012ec | ths | RETURN(); |
2148 | 5a5012ec | ths | } |
2149 | 5a5012ec | ths | FLOAT_OP(movf, ps) |
2150 | 5a5012ec | ths | { |
2151 | 5a5012ec | ths | if (!(env->fcr31 & PARAM1)) {
|
2152 | 5a5012ec | ths | WT2 = WT0; |
2153 | 5a5012ec | ths | WTH2 = WTH0; |
2154 | 5a5012ec | ths | } |
2155 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2156 | 5a5012ec | ths | RETURN(); |
2157 | 5a5012ec | ths | } |
2158 | 5a5012ec | ths | FLOAT_OP(movt, d) |
2159 | 5a5012ec | ths | { |
2160 | 5a5012ec | ths | if (env->fcr31 & PARAM1)
|
2161 | 5a5012ec | ths | DT2 = DT0; |
2162 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2163 | 5a5012ec | ths | RETURN(); |
2164 | 5a5012ec | ths | } |
2165 | 5a5012ec | ths | FLOAT_OP(movt, s) |
2166 | 5a5012ec | ths | { |
2167 | 5a5012ec | ths | if (env->fcr31 & PARAM1)
|
2168 | 5a5012ec | ths | WT2 = WT0; |
2169 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2170 | 5a5012ec | ths | RETURN(); |
2171 | 5a5012ec | ths | } |
2172 | 5a5012ec | ths | FLOAT_OP(movt, ps) |
2173 | 5a5012ec | ths | { |
2174 | 5a5012ec | ths | if (env->fcr31 & PARAM1) {
|
2175 | 5a5012ec | ths | WT2 = WT0; |
2176 | 5a5012ec | ths | WTH2 = WTH0; |
2177 | 5a5012ec | ths | } |
2178 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2179 | 5a5012ec | ths | RETURN(); |
2180 | 5a5012ec | ths | } |
2181 | 5a5012ec | ths | FLOAT_OP(movz, d) |
2182 | 5a5012ec | ths | { |
2183 | 5a5012ec | ths | if (!T0)
|
2184 | 5a5012ec | ths | DT2 = DT0; |
2185 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2186 | 5a5012ec | ths | RETURN(); |
2187 | 5a5012ec | ths | } |
2188 | 5a5012ec | ths | FLOAT_OP(movz, s) |
2189 | 5a5012ec | ths | { |
2190 | 5a5012ec | ths | if (!T0)
|
2191 | 5a5012ec | ths | WT2 = WT0; |
2192 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2193 | 5a5012ec | ths | RETURN(); |
2194 | 5a5012ec | ths | } |
2195 | 5a5012ec | ths | FLOAT_OP(movz, ps) |
2196 | 5a5012ec | ths | { |
2197 | 5a5012ec | ths | if (!T0) {
|
2198 | 5a5012ec | ths | WT2 = WT0; |
2199 | 5a5012ec | ths | WTH2 = WTH0; |
2200 | 5a5012ec | ths | } |
2201 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2202 | 5a5012ec | ths | RETURN(); |
2203 | 5a5012ec | ths | } |
2204 | 5a5012ec | ths | FLOAT_OP(movn, d) |
2205 | 5a5012ec | ths | { |
2206 | 5a5012ec | ths | if (T0)
|
2207 | 5a5012ec | ths | DT2 = DT0; |
2208 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2209 | 5a5012ec | ths | RETURN(); |
2210 | 5a5012ec | ths | } |
2211 | 5a5012ec | ths | FLOAT_OP(movn, s) |
2212 | 5a5012ec | ths | { |
2213 | 5a5012ec | ths | if (T0)
|
2214 | 5a5012ec | ths | WT2 = WT0; |
2215 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2216 | 5a5012ec | ths | RETURN(); |
2217 | 5a5012ec | ths | } |
2218 | 5a5012ec | ths | FLOAT_OP(movn, ps) |
2219 | 5a5012ec | ths | { |
2220 | 5a5012ec | ths | if (T0) {
|
2221 | 5a5012ec | ths | WT2 = WT0; |
2222 | 5a5012ec | ths | WTH2 = WTH0; |
2223 | 5a5012ec | ths | } |
2224 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2225 | 5a5012ec | ths | RETURN(); |
2226 | 5a5012ec | ths | } |
2227 | 5a5012ec | ths | |
2228 | 6ea83fed | bellard | /* binary operations */
|
2229 | 6ea83fed | bellard | #define FLOAT_BINOP(name) \
|
2230 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2231 | 6ea83fed | bellard | { \ |
2232 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status); \
|
2233 | 6ea83fed | bellard | FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ |
2234 | 5a5012ec | ths | update_fcr31(); \ |
2235 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2236 | fbcc6828 | ths | RETURN(); \ |
2237 | 6ea83fed | bellard | } \ |
2238 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2239 | 6ea83fed | bellard | { \ |
2240 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status); \
|
2241 | 6ea83fed | bellard | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
2242 | 5a5012ec | ths | update_fcr31(); \ |
2243 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2244 | fbcc6828 | ths | RETURN(); \ |
2245 | 5a5012ec | ths | } \ |
2246 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2247 | 5a5012ec | ths | { \ |
2248 | 5a5012ec | ths | set_float_exception_flags(0, &env->fp_status); \
|
2249 | 5a5012ec | ths | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
2250 | 5a5012ec | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \ |
2251 | 5a5012ec | ths | update_fcr31(); \ |
2252 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2253 | fbcc6828 | ths | RETURN(); \ |
2254 | 6ea83fed | bellard | } |
2255 | 6ea83fed | bellard | FLOAT_BINOP(add) |
2256 | 6ea83fed | bellard | FLOAT_BINOP(sub) |
2257 | 6ea83fed | bellard | FLOAT_BINOP(mul) |
2258 | 6ea83fed | bellard | FLOAT_BINOP(div) |
2259 | 6ea83fed | bellard | #undef FLOAT_BINOP
|
2260 | 6ea83fed | bellard | |
2261 | fbcc6828 | ths | FLOAT_OP(addr, ps) |
2262 | fbcc6828 | ths | { |
2263 | fbcc6828 | ths | set_float_exception_flags(0, &env->fp_status);
|
2264 | fbcc6828 | ths | FST2 = float32_add (FST0, FSTH0, &env->fp_status); |
2265 | fbcc6828 | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fp_status); |
2266 | fbcc6828 | ths | update_fcr31(); |
2267 | fbcc6828 | ths | DEBUG_FPU_STATE(); |
2268 | fbcc6828 | ths | RETURN(); |
2269 | fbcc6828 | ths | } |
2270 | fbcc6828 | ths | |
2271 | 5a5012ec | ths | /* ternary operations */
|
2272 | 5a5012ec | ths | #define FLOAT_TERNOP(name1, name2) \
|
2273 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, d) \ |
2274 | 5a5012ec | ths | { \ |
2275 | 5a5012ec | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \ |
2276 | 5a5012ec | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \ |
2277 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2278 | fbcc6828 | ths | RETURN(); \ |
2279 | 5a5012ec | ths | } \ |
2280 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, s) \ |
2281 | 5a5012ec | ths | { \ |
2282 | 5a5012ec | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2283 | 5a5012ec | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2284 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2285 | fbcc6828 | ths | RETURN(); \ |
2286 | 5a5012ec | ths | } \ |
2287 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, ps) \ |
2288 | 5a5012ec | ths | { \ |
2289 | 5a5012ec | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2290 | 5a5012ec | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \ |
2291 | 5a5012ec | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2292 | 5a5012ec | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \ |
2293 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2294 | fbcc6828 | ths | RETURN(); \ |
2295 | 5a5012ec | ths | } |
2296 | 5a5012ec | ths | FLOAT_TERNOP(mul, add) |
2297 | 5a5012ec | ths | FLOAT_TERNOP(mul, sub) |
2298 | 5a5012ec | ths | #undef FLOAT_TERNOP
|
2299 | 5a5012ec | ths | |
2300 | fbcc6828 | ths | /* negated ternary operations */
|
2301 | fbcc6828 | ths | #define FLOAT_NTERNOP(name1, name2) \
|
2302 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, d) \ |
2303 | fbcc6828 | ths | { \ |
2304 | fbcc6828 | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \ |
2305 | fbcc6828 | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \ |
2306 | fbcc6828 | ths | FDT2 ^= 1ULL << 63; \ |
2307 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2308 | fbcc6828 | ths | RETURN(); \ |
2309 | fbcc6828 | ths | } \ |
2310 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, s) \ |
2311 | fbcc6828 | ths | { \ |
2312 | fbcc6828 | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2313 | fbcc6828 | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2314 | fbcc6828 | ths | FST2 ^= 1 << 31; \ |
2315 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2316 | fbcc6828 | ths | RETURN(); \ |
2317 | fbcc6828 | ths | } \ |
2318 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, ps) \ |
2319 | fbcc6828 | ths | { \ |
2320 | fbcc6828 | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2321 | fbcc6828 | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \ |
2322 | fbcc6828 | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2323 | fbcc6828 | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \ |
2324 | fbcc6828 | ths | FST2 ^= 1 << 31; \ |
2325 | fbcc6828 | ths | FSTH2 ^= 1 << 31; \ |
2326 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2327 | fbcc6828 | ths | RETURN(); \ |
2328 | fbcc6828 | ths | } |
2329 | fbcc6828 | ths | FLOAT_NTERNOP(mul, add) |
2330 | fbcc6828 | ths | FLOAT_NTERNOP(mul, sub) |
2331 | fbcc6828 | ths | #undef FLOAT_NTERNOP
|
2332 | fbcc6828 | ths | |
2333 | 6ea83fed | bellard | /* unary operations, modifying fp status */
|
2334 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2335 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2336 | 6ea83fed | bellard | { \ |
2337 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0, &env->fp_status); \ |
2338 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2339 | fbcc6828 | ths | RETURN(); \ |
2340 | 6ea83fed | bellard | } \ |
2341 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2342 | 6ea83fed | bellard | { \ |
2343 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0, &env->fp_status); \ |
2344 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2345 | fbcc6828 | ths | RETURN(); \ |
2346 | 5a5012ec | ths | } \ |
2347 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2348 | 5a5012ec | ths | { \ |
2349 | 5a5012ec | ths | FST2 = float32_ ## name(FST0, &env->fp_status); \ |
2350 | 5a5012ec | ths | FSTH2 = float32_ ## name(FSTH0, &env->fp_status); \ |
2351 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2352 | fbcc6828 | ths | RETURN(); \ |
2353 | 6ea83fed | bellard | } |
2354 | 6ea83fed | bellard | FLOAT_UNOP(sqrt) |
2355 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2356 | 6ea83fed | bellard | |
2357 | 6ea83fed | bellard | /* unary operations, not modifying fp status */
|
2358 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2359 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2360 | 6ea83fed | bellard | { \ |
2361 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0); \ |
2362 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2363 | fbcc6828 | ths | RETURN(); \ |
2364 | 6ea83fed | bellard | } \ |
2365 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2366 | 6ea83fed | bellard | { \ |
2367 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0); \ |
2368 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2369 | fbcc6828 | ths | RETURN(); \ |
2370 | 5a5012ec | ths | } \ |
2371 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2372 | 5a5012ec | ths | { \ |
2373 | 5a5012ec | ths | FST2 = float32_ ## name(FST0); \ |
2374 | 5a5012ec | ths | FSTH2 = float32_ ## name(FSTH0); \ |
2375 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2376 | fbcc6828 | ths | RETURN(); \ |
2377 | 6ea83fed | bellard | } |
2378 | 6ea83fed | bellard | FLOAT_UNOP(abs) |
2379 | 6ea83fed | bellard | FLOAT_UNOP(chs) |
2380 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2381 | 6ea83fed | bellard | |
2382 | 6ea83fed | bellard | FLOAT_OP(mov, d) |
2383 | 6ea83fed | bellard | { |
2384 | 6ea83fed | bellard | FDT2 = FDT0; |
2385 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2386 | 6ea83fed | bellard | RETURN(); |
2387 | 6ea83fed | bellard | } |
2388 | 6ea83fed | bellard | FLOAT_OP(mov, s) |
2389 | 6ea83fed | bellard | { |
2390 | 6ea83fed | bellard | FST2 = FST0; |
2391 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2392 | 6ea83fed | bellard | RETURN(); |
2393 | 6ea83fed | bellard | } |
2394 | 5a5012ec | ths | FLOAT_OP(mov, ps) |
2395 | 5a5012ec | ths | { |
2396 | 5a5012ec | ths | FST2 = FST0; |
2397 | 5a5012ec | ths | FSTH2 = FSTH0; |
2398 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2399 | 5a5012ec | ths | RETURN(); |
2400 | 5a5012ec | ths | } |
2401 | 5a5012ec | ths | FLOAT_OP(alnv, ps) |
2402 | 5a5012ec | ths | { |
2403 | 5a5012ec | ths | switch (T0 & 0x7) { |
2404 | 5a5012ec | ths | case 0: |
2405 | 5a5012ec | ths | FST2 = FST0; |
2406 | 5a5012ec | ths | FSTH2 = FSTH0; |
2407 | 5a5012ec | ths | break;
|
2408 | 5a5012ec | ths | case 4: |
2409 | 5a5012ec | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
2410 | 5a5012ec | ths | FSTH2 = FST0; |
2411 | 5a5012ec | ths | FST2 = FSTH1; |
2412 | 5a5012ec | ths | #else
|
2413 | 5a5012ec | ths | FSTH2 = FST1; |
2414 | 5a5012ec | ths | FST2 = FSTH0; |
2415 | 5a5012ec | ths | #endif
|
2416 | 5a5012ec | ths | break;
|
2417 | 5a5012ec | ths | default: /* unpredictable */ |
2418 | 5a5012ec | ths | break;
|
2419 | 5a5012ec | ths | } |
2420 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2421 | 5a5012ec | ths | RETURN(); |
2422 | 5a5012ec | ths | } |
2423 | 6ea83fed | bellard | |
2424 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
2425 | 6ea83fed | bellard | #define clear_invalid() do { \ |
2426 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status); \
|
2427 | 6ea83fed | bellard | flags &= ~float_flag_invalid; \ |
2428 | 6ea83fed | bellard | set_float_exception_flags(flags, &env->fp_status); \ |
2429 | 6ea83fed | bellard | } while(0) |
2430 | 6ea83fed | bellard | #else
|
2431 | 6ea83fed | bellard | #define clear_invalid() do { } while(0) |
2432 | 6ea83fed | bellard | #endif
|
2433 | 6ea83fed | bellard | |
2434 | 6ea83fed | bellard | extern void dump_fpu_s(CPUState *env); |
2435 | 6ea83fed | bellard | |
2436 | 5a5012ec | ths | #define FOP_COND_D(op, cond) \
|
2437 | 5a5012ec | ths | void op_cmp_d_ ## op (void) \ |
2438 | 6ea83fed | bellard | { \ |
2439 | 5a5012ec | ths | int c = cond; \
|
2440 | 5a5012ec | ths | update_fcr31(); \ |
2441 | 5a5012ec | ths | if (c) \
|
2442 | 5a5012ec | ths | SET_FP_COND(PARAM1, env); \ |
2443 | 6ea83fed | bellard | else \
|
2444 | 5a5012ec | ths | CLEAR_FP_COND(PARAM1, env); \ |
2445 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2446 | 6ea83fed | bellard | RETURN(); \ |
2447 | 5a1e8ffb | ths | } \ |
2448 | 5a1e8ffb | ths | void op_cmpabs_d_ ## op (void) \ |
2449 | 5a1e8ffb | ths | { \ |
2450 | 5a1e8ffb | ths | int c; \
|
2451 | 5a1e8ffb | ths | FDT0 &= ~(1ULL << 63); \ |
2452 | 5a1e8ffb | ths | FDT1 &= ~(1ULL << 63); \ |
2453 | 5a1e8ffb | ths | c = cond; \ |
2454 | 5a1e8ffb | ths | update_fcr31(); \ |
2455 | 5a1e8ffb | ths | if (c) \
|
2456 | 5a1e8ffb | ths | SET_FP_COND(PARAM1, env); \ |
2457 | 5a1e8ffb | ths | else \
|
2458 | 5a1e8ffb | ths | CLEAR_FP_COND(PARAM1, env); \ |
2459 | 5a1e8ffb | ths | DEBUG_FPU_STATE(); \ |
2460 | 5a1e8ffb | ths | RETURN(); \ |
2461 | 6ea83fed | bellard | } |
2462 | 6ea83fed | bellard | |
2463 | 5a5012ec | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
2464 | 6ea83fed | bellard | { |
2465 | 5a5012ec | ths | if (float64_is_signaling_nan(a) ||
|
2466 | 5a5012ec | ths | float64_is_signaling_nan(b) || |
2467 | 5a5012ec | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
2468 | 6ea83fed | bellard | float_raise(float_flag_invalid, status); |
2469 | 6ea83fed | bellard | return 1; |
2470 | 5a5012ec | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
2471 | 5a5012ec | ths | return 1; |
2472 | 5a5012ec | ths | } else {
|
2473 | 6ea83fed | bellard | return 0; |
2474 | 6ea83fed | bellard | } |
2475 | 6ea83fed | bellard | } |
2476 | 6ea83fed | bellard | |
2477 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
2478 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2479 | 5a5012ec | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fp_status), 0)) |
2480 | 5a5012ec | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fp_status))
|
2481 | 5a5012ec | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
2482 | 5a5012ec | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
2483 | 5a5012ec | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
2484 | 5a5012ec | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
2485 | 5a5012ec | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
2486 | 5a5012ec | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
2487 | 5a5012ec | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
2488 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2489 | 5a5012ec | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fp_status), 0)) |
2490 | 5a5012ec | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fp_status))
|
2491 | 5a5012ec | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
2492 | 5a5012ec | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
2493 | 5a5012ec | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
2494 | 5a5012ec | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
2495 | 5a5012ec | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
2496 | 5a5012ec | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
2497 | 5a5012ec | ths | |
2498 | 5a5012ec | ths | #define FOP_COND_S(op, cond) \
|
2499 | 5a5012ec | ths | void op_cmp_s_ ## op (void) \ |
2500 | 5a5012ec | ths | { \ |
2501 | 5a5012ec | ths | int c = cond; \
|
2502 | 5a5012ec | ths | update_fcr31(); \ |
2503 | 5a5012ec | ths | if (c) \
|
2504 | 5a5012ec | ths | SET_FP_COND(PARAM1, env); \ |
2505 | 5a5012ec | ths | else \
|
2506 | 5a5012ec | ths | CLEAR_FP_COND(PARAM1, env); \ |
2507 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2508 | 5a5012ec | ths | RETURN(); \ |
2509 | 5a1e8ffb | ths | } \ |
2510 | 5a1e8ffb | ths | void op_cmpabs_s_ ## op (void) \ |
2511 | 5a1e8ffb | ths | { \ |
2512 | 5a1e8ffb | ths | int c; \
|
2513 | 5a1e8ffb | ths | FST0 &= ~(1 << 31); \ |
2514 | 5a1e8ffb | ths | FST1 &= ~(1 << 31); \ |
2515 | 5a1e8ffb | ths | c = cond; \ |
2516 | 5a1e8ffb | ths | update_fcr31(); \ |
2517 | 5a1e8ffb | ths | if (c) \
|
2518 | 5a1e8ffb | ths | SET_FP_COND(PARAM1, env); \ |
2519 | 5a1e8ffb | ths | else \
|
2520 | 5a1e8ffb | ths | CLEAR_FP_COND(PARAM1, env); \ |
2521 | 5a1e8ffb | ths | DEBUG_FPU_STATE(); \ |
2522 | 5a1e8ffb | ths | RETURN(); \ |
2523 | 5a5012ec | ths | } |
2524 | 5a5012ec | ths | |
2525 | 5a5012ec | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
2526 | 5a5012ec | ths | { |
2527 | 5a5012ec | ths | extern flag float32_is_nan(float32 a);
|
2528 | 5a5012ec | ths | if (float32_is_signaling_nan(a) ||
|
2529 | 5a5012ec | ths | float32_is_signaling_nan(b) || |
2530 | 5a5012ec | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
2531 | 6ea83fed | bellard | float_raise(float_flag_invalid, status); |
2532 | 6ea83fed | bellard | return 1; |
2533 | 5a5012ec | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
2534 | 5a5012ec | ths | return 1; |
2535 | 5a5012ec | ths | } else {
|
2536 | 6ea83fed | bellard | return 0; |
2537 | 6ea83fed | bellard | } |
2538 | 6ea83fed | bellard | } |
2539 | 6ea83fed | bellard | |
2540 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
2541 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2542 | 5a5012ec | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0)) |
2543 | 5a5012ec | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fp_status))
|
2544 | 5a5012ec | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
2545 | 5a5012ec | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
2546 | 5a5012ec | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
2547 | 5a5012ec | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
2548 | 5a5012ec | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
2549 | 5a5012ec | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
2550 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
2551 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2552 | 5a5012ec | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0)) |
2553 | 5a5012ec | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status))
|
2554 | 5a5012ec | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
2555 | 5a5012ec | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
2556 | 5a5012ec | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
2557 | 5a5012ec | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
2558 | 5a5012ec | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
2559 | 5a5012ec | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
2560 | 5a5012ec | ths | |
2561 | 5a5012ec | ths | #define FOP_COND_PS(op, condl, condh) \
|
2562 | 5a5012ec | ths | void op_cmp_ps_ ## op (void) \ |
2563 | 5a5012ec | ths | { \ |
2564 | 5a5012ec | ths | int cl = condl; \
|
2565 | 5a5012ec | ths | int ch = condh; \
|
2566 | 5a5012ec | ths | update_fcr31(); \ |
2567 | 5a5012ec | ths | if (cl) \
|
2568 | 5a5012ec | ths | SET_FP_COND(PARAM1, env); \ |
2569 | 5a5012ec | ths | else \
|
2570 | 5a5012ec | ths | CLEAR_FP_COND(PARAM1, env); \ |
2571 | 5a5012ec | ths | if (ch) \
|
2572 | 5a5012ec | ths | SET_FP_COND(PARAM1 + 1, env); \
|
2573 | 5a5012ec | ths | else \
|
2574 | 5a5012ec | ths | CLEAR_FP_COND(PARAM1 + 1, env); \
|
2575 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2576 | 5a5012ec | ths | RETURN(); \ |
2577 | 5a1e8ffb | ths | } \ |
2578 | 5a1e8ffb | ths | void op_cmpabs_ps_ ## op (void) \ |
2579 | 5a1e8ffb | ths | { \ |
2580 | 5a1e8ffb | ths | int cl, ch; \
|
2581 | 5a1e8ffb | ths | FST0 &= ~(1 << 31); \ |
2582 | 5a1e8ffb | ths | FSTH0 &= ~(1 << 31); \ |
2583 | 5a1e8ffb | ths | FST1 &= ~(1 << 31); \ |
2584 | 5a1e8ffb | ths | FSTH1 &= ~(1 << 31); \ |
2585 | 5a1e8ffb | ths | cl = condl; \ |
2586 | 5a1e8ffb | ths | ch = condh; \ |
2587 | 5a1e8ffb | ths | update_fcr31(); \ |
2588 | 5a1e8ffb | ths | if (cl) \
|
2589 | 5a1e8ffb | ths | SET_FP_COND(PARAM1, env); \ |
2590 | 5a1e8ffb | ths | else \
|
2591 | 5a1e8ffb | ths | CLEAR_FP_COND(PARAM1, env); \ |
2592 | 5a1e8ffb | ths | if (ch) \
|
2593 | 5a1e8ffb | ths | SET_FP_COND(PARAM1 + 1, env); \
|
2594 | 5a1e8ffb | ths | else \
|
2595 | 5a1e8ffb | ths | CLEAR_FP_COND(PARAM1 + 1, env); \
|
2596 | 5a1e8ffb | ths | DEBUG_FPU_STATE(); \ |
2597 | 5a1e8ffb | ths | RETURN(); \ |
2598 | 5a5012ec | ths | } |
2599 | 5a5012ec | ths | |
2600 | 5a5012ec | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
2601 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2602 | 5a5012ec | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0), |
2603 | 5a5012ec | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status), 0)) |
2604 | 5a5012ec | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fp_status),
|
2605 | 5a5012ec | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status))
|
2606 | 5a5012ec | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status),
|
2607 | 5a5012ec | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
|
2608 | 5a5012ec | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status),
|
2609 | 5a5012ec | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status))
|
2610 | 5a5012ec | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status),
|
2611 | 5a5012ec | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
|
2612 | 5a5012ec | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status),
|
2613 | 5a5012ec | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status))
|
2614 | 5a5012ec | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status),
|
2615 | 5a5012ec | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
|
2616 | 5a5012ec | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status),
|
2617 | 5a5012ec | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status))
|
2618 | 5a5012ec | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
2619 | 5a5012ec | ths | * but float*_is_unordered() is still called. */
|
2620 | 5a5012ec | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0), |
2621 | 5a5012ec | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status), 0)) |
2622 | 5a5012ec | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status),
|
2623 | 5a5012ec | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status))
|
2624 | 5a5012ec | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status),
|
2625 | 5a5012ec | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
|
2626 | 5a5012ec | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status),
|
2627 | 5a5012ec | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status))
|
2628 | 5a5012ec | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status),
|
2629 | 5a5012ec | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
|
2630 | 5a5012ec | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status),
|
2631 | 5a5012ec | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status))
|
2632 | 5a5012ec | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status),
|
2633 | 5a5012ec | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
|
2634 | 5a5012ec | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status),
|
2635 | 5a5012ec | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status))
|
2636 | 6ea83fed | bellard | |
2637 | 6ea83fed | bellard | void op_bc1f (void) |
2638 | 6ea83fed | bellard | { |
2639 | 5a5012ec | ths | T0 = !IS_FP_COND_SET(PARAM1, env); |
2640 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2641 | 5a5012ec | ths | RETURN(); |
2642 | 5a5012ec | ths | } |
2643 | 5a5012ec | ths | void op_bc1fany2 (void) |
2644 | 5a5012ec | ths | { |
2645 | 5a5012ec | ths | T0 = (!IS_FP_COND_SET(PARAM1, env) || |
2646 | 5a5012ec | ths | !IS_FP_COND_SET(PARAM1 + 1, env));
|
2647 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2648 | 5a5012ec | ths | RETURN(); |
2649 | 5a5012ec | ths | } |
2650 | 5a5012ec | ths | void op_bc1fany4 (void) |
2651 | 5a5012ec | ths | { |
2652 | 5a5012ec | ths | T0 = (!IS_FP_COND_SET(PARAM1, env) || |
2653 | 5a5012ec | ths | !IS_FP_COND_SET(PARAM1 + 1, env) ||
|
2654 | 5a5012ec | ths | !IS_FP_COND_SET(PARAM1 + 2, env) ||
|
2655 | 5a5012ec | ths | !IS_FP_COND_SET(PARAM1 + 3, env));
|
2656 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2657 | 6ea83fed | bellard | RETURN(); |
2658 | 6ea83fed | bellard | } |
2659 | 6ea83fed | bellard | |
2660 | 6ea83fed | bellard | void op_bc1t (void) |
2661 | 6ea83fed | bellard | { |
2662 | 5a5012ec | ths | T0 = IS_FP_COND_SET(PARAM1, env); |
2663 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2664 | 5a5012ec | ths | RETURN(); |
2665 | 5a5012ec | ths | } |
2666 | 5a5012ec | ths | void op_bc1tany2 (void) |
2667 | 5a5012ec | ths | { |
2668 | 5a5012ec | ths | T0 = (IS_FP_COND_SET(PARAM1, env) || |
2669 | 5a5012ec | ths | IS_FP_COND_SET(PARAM1 + 1, env));
|
2670 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2671 | 5a5012ec | ths | RETURN(); |
2672 | 5a5012ec | ths | } |
2673 | 5a5012ec | ths | void op_bc1tany4 (void) |
2674 | 5a5012ec | ths | { |
2675 | 5a5012ec | ths | T0 = (IS_FP_COND_SET(PARAM1, env) || |
2676 | 5a5012ec | ths | IS_FP_COND_SET(PARAM1 + 1, env) ||
|
2677 | 5a5012ec | ths | IS_FP_COND_SET(PARAM1 + 2, env) ||
|
2678 | 5a5012ec | ths | IS_FP_COND_SET(PARAM1 + 3, env));
|
2679 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2680 | 6ea83fed | bellard | RETURN(); |
2681 | 6ea83fed | bellard | } |
2682 | 6ea83fed | bellard | |
2683 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
2684 | 6af0bf9c | bellard | void op_tlbwi (void) |
2685 | 6af0bf9c | bellard | { |
2686 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbwi); |
2687 | 6af0bf9c | bellard | RETURN(); |
2688 | 6af0bf9c | bellard | } |
2689 | 6af0bf9c | bellard | |
2690 | 6af0bf9c | bellard | void op_tlbwr (void) |
2691 | 6af0bf9c | bellard | { |
2692 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbwr); |
2693 | 6af0bf9c | bellard | RETURN(); |
2694 | 6af0bf9c | bellard | } |
2695 | 6af0bf9c | bellard | |
2696 | 6af0bf9c | bellard | void op_tlbp (void) |
2697 | 6af0bf9c | bellard | { |
2698 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbp); |
2699 | 6af0bf9c | bellard | RETURN(); |
2700 | 6af0bf9c | bellard | } |
2701 | 6af0bf9c | bellard | |
2702 | 6af0bf9c | bellard | void op_tlbr (void) |
2703 | 6af0bf9c | bellard | { |
2704 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbr); |
2705 | 6af0bf9c | bellard | RETURN(); |
2706 | 6af0bf9c | bellard | } |
2707 | 6af0bf9c | bellard | #endif
|
2708 | 6af0bf9c | bellard | |
2709 | 6af0bf9c | bellard | /* Specials */
|
2710 | 6f5b89a0 | ths | #if defined (CONFIG_USER_ONLY)
|
2711 | 6f5b89a0 | ths | void op_tls_value (void) |
2712 | 6f5b89a0 | ths | { |
2713 | 5a5012ec | ths | T0 = env->tls_value; |
2714 | 6f5b89a0 | ths | } |
2715 | 6f5b89a0 | ths | #endif
|
2716 | 6f5b89a0 | ths | |
2717 | 6af0bf9c | bellard | void op_pmon (void) |
2718 | 6af0bf9c | bellard | { |
2719 | 6af0bf9c | bellard | CALL_FROM_TB1(do_pmon, PARAM1); |
2720 | 7a387fff | ths | RETURN(); |
2721 | 7a387fff | ths | } |
2722 | 7a387fff | ths | |
2723 | 7a387fff | ths | void op_di (void) |
2724 | 7a387fff | ths | { |
2725 | 7a387fff | ths | T0 = env->CP0_Status; |
2726 | 4de9b249 | ths | env->CP0_Status = T0 & ~(1 << CP0St_IE);
|
2727 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
2728 | 7a387fff | ths | RETURN(); |
2729 | 7a387fff | ths | } |
2730 | 7a387fff | ths | |
2731 | 7a387fff | ths | void op_ei (void) |
2732 | 7a387fff | ths | { |
2733 | 7a387fff | ths | T0 = env->CP0_Status; |
2734 | 4de9b249 | ths | env->CP0_Status = T0 | (1 << CP0St_IE);
|
2735 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
2736 | 7a387fff | ths | RETURN(); |
2737 | 6af0bf9c | bellard | } |
2738 | 6af0bf9c | bellard | |
2739 | 6af0bf9c | bellard | void op_trap (void) |
2740 | 6af0bf9c | bellard | { |
2741 | 6af0bf9c | bellard | if (T0) {
|
2742 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
2743 | 6af0bf9c | bellard | } |
2744 | 6af0bf9c | bellard | RETURN(); |
2745 | 6af0bf9c | bellard | } |
2746 | 6af0bf9c | bellard | |
2747 | 4ad40f36 | bellard | void op_debug (void) |
2748 | 4ad40f36 | bellard | { |
2749 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
2750 | 7a387fff | ths | RETURN(); |
2751 | 4ad40f36 | bellard | } |
2752 | 4ad40f36 | bellard | |
2753 | 6af0bf9c | bellard | void op_set_lladdr (void) |
2754 | 6af0bf9c | bellard | { |
2755 | 6af0bf9c | bellard | env->CP0_LLAddr = T2; |
2756 | 7a387fff | ths | RETURN(); |
2757 | 6af0bf9c | bellard | } |
2758 | 6af0bf9c | bellard | |
2759 | f41c52f1 | ths | void debug_pre_eret (void); |
2760 | f41c52f1 | ths | void debug_post_eret (void); |
2761 | 6af0bf9c | bellard | void op_eret (void) |
2762 | 6af0bf9c | bellard | { |
2763 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
2764 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
2765 | 24c7b0e3 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
2766 | 6af0bf9c | bellard | env->PC = env->CP0_ErrorEPC; |
2767 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_ERL);
|
2768 | 51e11d9e | bellard | } else {
|
2769 | 6af0bf9c | bellard | env->PC = env->CP0_EPC; |
2770 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_EXL);
|
2771 | 51e11d9e | bellard | } |
2772 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2773 | 24c7b0e3 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2774 | 24c7b0e3 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
2775 | 24c7b0e3 | ths | (env->CP0_Status & (1 << CP0St_UM)))
|
2776 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_UM; |
2777 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
2778 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
2779 | 6af0bf9c | bellard | env->CP0_LLAddr = 1;
|
2780 | 7a387fff | ths | RETURN(); |
2781 | 6af0bf9c | bellard | } |
2782 | 6af0bf9c | bellard | |
2783 | 6af0bf9c | bellard | void op_deret (void) |
2784 | 6af0bf9c | bellard | { |
2785 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
2786 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
2787 | 6af0bf9c | bellard | env->PC = env->CP0_DEPC; |
2788 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_DM; |
2789 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2790 | 24c7b0e3 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2791 | 24c7b0e3 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
2792 | 24c7b0e3 | ths | (env->CP0_Status & (1 << CP0St_UM)))
|
2793 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_UM; |
2794 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
2795 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
2796 | 24c7b0e3 | ths | env->CP0_LLAddr = 1;
|
2797 | 7a387fff | ths | RETURN(); |
2798 | 7a387fff | ths | } |
2799 | 7a387fff | ths | |
2800 | 7a387fff | ths | void op_rdhwr_cpunum(void) |
2801 | 7a387fff | ths | { |
2802 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2803 | 97428a4d | ths | (env->CP0_HWREna & (1 << 0)) || |
2804 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
2805 | 1579a72e | ths | T0 = env->CP0_EBase & 0x3ff;
|
2806 | 7a387fff | ths | else
|
2807 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2808 | 7a387fff | ths | RETURN(); |
2809 | 7a387fff | ths | } |
2810 | 7a387fff | ths | |
2811 | 7a387fff | ths | void op_rdhwr_synci_step(void) |
2812 | 7a387fff | ths | { |
2813 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2814 | 97428a4d | ths | (env->CP0_HWREna & (1 << 1)) || |
2815 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
2816 | 1579a72e | ths | T0 = env->SYNCI_Step; |
2817 | 7a387fff | ths | else
|
2818 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2819 | 7a387fff | ths | RETURN(); |
2820 | 7a387fff | ths | } |
2821 | 7a387fff | ths | |
2822 | 7a387fff | ths | void op_rdhwr_cc(void) |
2823 | 7a387fff | ths | { |
2824 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2825 | 97428a4d | ths | (env->CP0_HWREna & (1 << 2)) || |
2826 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
2827 | 1579a72e | ths | T0 = env->CP0_Count; |
2828 | 7a387fff | ths | else
|
2829 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2830 | 7a387fff | ths | RETURN(); |
2831 | 7a387fff | ths | } |
2832 | 7a387fff | ths | |
2833 | 7a387fff | ths | void op_rdhwr_ccres(void) |
2834 | 7a387fff | ths | { |
2835 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2836 | 97428a4d | ths | (env->CP0_HWREna & (1 << 3)) || |
2837 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
2838 | 1579a72e | ths | T0 = env->CCRes; |
2839 | 7a387fff | ths | else
|
2840 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2841 | 1579a72e | ths | RETURN(); |
2842 | 1579a72e | ths | } |
2843 | 1579a72e | ths | |
2844 | 6af0bf9c | bellard | void op_save_state (void) |
2845 | 6af0bf9c | bellard | { |
2846 | 6af0bf9c | bellard | env->hflags = PARAM1; |
2847 | 6af0bf9c | bellard | RETURN(); |
2848 | 6af0bf9c | bellard | } |
2849 | 6af0bf9c | bellard | |
2850 | 6af0bf9c | bellard | void op_save_pc (void) |
2851 | 6af0bf9c | bellard | { |
2852 | 6af0bf9c | bellard | env->PC = PARAM1; |
2853 | 6af0bf9c | bellard | RETURN(); |
2854 | 6af0bf9c | bellard | } |
2855 | 6af0bf9c | bellard | |
2856 | 5a5012ec | ths | void op_save_fp_status (void) |
2857 | 5a5012ec | ths | { |
2858 | 5a5012ec | ths | union fps {
|
2859 | 5a5012ec | ths | uint32_t i; |
2860 | 5a5012ec | ths | float_status f; |
2861 | 5a5012ec | ths | } fps; |
2862 | 5a5012ec | ths | fps.i = PARAM1; |
2863 | 5a5012ec | ths | env->fp_status = fps.f; |
2864 | 5a5012ec | ths | RETURN(); |
2865 | 5a5012ec | ths | } |
2866 | 5a5012ec | ths | |
2867 | 16c00cb2 | ths | void op_interrupt_restart (void) |
2868 | 16c00cb2 | ths | { |
2869 | 16c00cb2 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2870 | 16c00cb2 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2871 | 16c00cb2 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
2872 | 16c00cb2 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
|
2873 | 16c00cb2 | ths | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
2874 | 16c00cb2 | ths | env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
|
2875 | 16c00cb2 | ths | CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); |
2876 | 16c00cb2 | ths | } |
2877 | 16c00cb2 | ths | RETURN(); |
2878 | 16c00cb2 | ths | } |
2879 | 16c00cb2 | ths | |
2880 | 6af0bf9c | bellard | void op_raise_exception (void) |
2881 | 6af0bf9c | bellard | { |
2882 | 6af0bf9c | bellard | CALL_FROM_TB1(do_raise_exception, PARAM1); |
2883 | 6af0bf9c | bellard | RETURN(); |
2884 | 6af0bf9c | bellard | } |
2885 | 6af0bf9c | bellard | |
2886 | 6af0bf9c | bellard | void op_raise_exception_err (void) |
2887 | 6af0bf9c | bellard | { |
2888 | 6af0bf9c | bellard | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
2889 | 6af0bf9c | bellard | RETURN(); |
2890 | 6af0bf9c | bellard | } |
2891 | 6af0bf9c | bellard | |
2892 | 6af0bf9c | bellard | void op_exit_tb (void) |
2893 | 6af0bf9c | bellard | { |
2894 | 6af0bf9c | bellard | EXIT_TB(); |
2895 | 7a387fff | ths | RETURN(); |
2896 | 6af0bf9c | bellard | } |
2897 | 6af0bf9c | bellard | |
2898 | 4ad40f36 | bellard | void op_wait (void) |
2899 | 4ad40f36 | bellard | { |
2900 | 4ad40f36 | bellard | env->halted = 1;
|
2901 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
2902 | 7a387fff | ths | RETURN(); |
2903 | 7a387fff | ths | } |
2904 | 7a387fff | ths | |
2905 | 7a387fff | ths | /* Bitfield operations. */
|
2906 | 7a387fff | ths | void op_ext(void) |
2907 | 7a387fff | ths | { |
2908 | 7a387fff | ths | unsigned int pos = PARAM1; |
2909 | 7a387fff | ths | unsigned int size = PARAM2; |
2910 | 7a387fff | ths | |
2911 | f757d6ff | ths | T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
2912 | 7a387fff | ths | RETURN(); |
2913 | 7a387fff | ths | } |
2914 | 7a387fff | ths | |
2915 | 7a387fff | ths | void op_ins(void) |
2916 | 7a387fff | ths | { |
2917 | 7a387fff | ths | unsigned int pos = PARAM1; |
2918 | 7a387fff | ths | unsigned int size = PARAM2; |
2919 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
2920 | 7a387fff | ths | |
2921 | 171b31e7 | ths | T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask); |
2922 | 7a387fff | ths | RETURN(); |
2923 | 7a387fff | ths | } |
2924 | 7a387fff | ths | |
2925 | 7a387fff | ths | void op_wsbh(void) |
2926 | 7a387fff | ths | { |
2927 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
2928 | 7a387fff | ths | RETURN(); |
2929 | 7a387fff | ths | } |
2930 | 7a387fff | ths | |
2931 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
2932 | c570fd16 | ths | void op_dext(void) |
2933 | c570fd16 | ths | { |
2934 | c570fd16 | ths | unsigned int pos = PARAM1; |
2935 | c570fd16 | ths | unsigned int size = PARAM2; |
2936 | c570fd16 | ths | |
2937 | f757d6ff | ths | T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
2938 | c570fd16 | ths | RETURN(); |
2939 | c570fd16 | ths | } |
2940 | c570fd16 | ths | |
2941 | c570fd16 | ths | void op_dins(void) |
2942 | c570fd16 | ths | { |
2943 | c570fd16 | ths | unsigned int pos = PARAM1; |
2944 | c570fd16 | ths | unsigned int size = PARAM2; |
2945 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
2946 | c570fd16 | ths | |
2947 | 171b31e7 | ths | T0 = (T0 & ~mask) | ((T1 << pos) & mask); |
2948 | c570fd16 | ths | RETURN(); |
2949 | c570fd16 | ths | } |
2950 | c570fd16 | ths | |
2951 | 7a387fff | ths | void op_dsbh(void) |
2952 | 7a387fff | ths | { |
2953 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
2954 | 7a387fff | ths | RETURN(); |
2955 | 7a387fff | ths | } |
2956 | 7a387fff | ths | |
2957 | 7a387fff | ths | void op_dshd(void) |
2958 | 7a387fff | ths | { |
2959 | 7a387fff | ths | T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
2960 | 7a387fff | ths | RETURN(); |
2961 | 7a387fff | ths | } |
2962 | c570fd16 | ths | #endif
|
2963 | 7a387fff | ths | |
2964 | 7a387fff | ths | void op_seb(void) |
2965 | 7a387fff | ths | { |
2966 | 7a387fff | ths | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
2967 | 7a387fff | ths | RETURN(); |
2968 | 7a387fff | ths | } |
2969 | 7a387fff | ths | |
2970 | 7a387fff | ths | void op_seh(void) |
2971 | 7a387fff | ths | { |
2972 | 7a387fff | ths | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
2973 | 7a387fff | ths | RETURN(); |
2974 | 4ad40f36 | bellard | } |