Revision 5a1e8ffb target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 490 | 490 |
FGEN32(gen_op_load_fpr_WTH2, gen_op_load_fpr_WTH2_fpr); |
| 491 | 491 |
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr); |
| 492 | 492 |
|
| 493 |
#define FOP_CONDS(fmt) \
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| 494 |
static GenOpFunc1 * cond_ ## fmt ## _table[16] = { \
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| 495 |
gen_op_cmp_ ## fmt ## _f, \
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| 496 |
gen_op_cmp_ ## fmt ## _un, \
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| 497 |
gen_op_cmp_ ## fmt ## _eq, \
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| 498 |
gen_op_cmp_ ## fmt ## _ueq, \
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| 499 |
gen_op_cmp_ ## fmt ## _olt, \
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| 500 |
gen_op_cmp_ ## fmt ## _ult, \
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| 501 |
gen_op_cmp_ ## fmt ## _ole, \
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| 502 |
gen_op_cmp_ ## fmt ## _ule, \
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| 503 |
gen_op_cmp_ ## fmt ## _sf, \
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| 504 |
gen_op_cmp_ ## fmt ## _ngle, \
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| 505 |
gen_op_cmp_ ## fmt ## _seq, \
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| 506 |
gen_op_cmp_ ## fmt ## _ngl, \
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| 507 |
gen_op_cmp_ ## fmt ## _lt, \
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| 508 |
gen_op_cmp_ ## fmt ## _nge, \
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| 509 |
gen_op_cmp_ ## fmt ## _le, \
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| 510 |
gen_op_cmp_ ## fmt ## _ngt, \
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| 493 |
#define FOP_CONDS(type, fmt) \
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| 494 |
static GenOpFunc1 * cond ## type ## _ ## fmt ## _table[16] = { \
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| 495 |
gen_op_cmp ## type ## _ ## fmt ## _f, \
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| 496 |
gen_op_cmp ## type ## _ ## fmt ## _un, \
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| 497 |
gen_op_cmp ## type ## _ ## fmt ## _eq, \
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| 498 |
gen_op_cmp ## type ## _ ## fmt ## _ueq, \
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| 499 |
gen_op_cmp ## type ## _ ## fmt ## _olt, \
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| 500 |
gen_op_cmp ## type ## _ ## fmt ## _ult, \
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| 501 |
gen_op_cmp ## type ## _ ## fmt ## _ole, \
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| 502 |
gen_op_cmp ## type ## _ ## fmt ## _ule, \
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| 503 |
gen_op_cmp ## type ## _ ## fmt ## _sf, \
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| 504 |
gen_op_cmp ## type ## _ ## fmt ## _ngle, \
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| 505 |
gen_op_cmp ## type ## _ ## fmt ## _seq, \
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| 506 |
gen_op_cmp ## type ## _ ## fmt ## _ngl, \
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| 507 |
gen_op_cmp ## type ## _ ## fmt ## _lt, \
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| 508 |
gen_op_cmp ## type ## _ ## fmt ## _nge, \
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gen_op_cmp ## type ## _ ## fmt ## _le, \
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| 510 |
gen_op_cmp ## type ## _ ## fmt ## _ngt, \
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| 511 | 511 |
}; \ |
| 512 |
static inline void gen_cmp_ ## fmt(int n, long cc) \
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static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
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| 513 | 513 |
{ \
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| 514 |
cond_ ## fmt ## _table[n](cc); \
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| 514 |
cond ## type ## _ ## fmt ## _table[n](cc); \
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| 515 | 515 |
} |
| 516 | 516 |
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| 517 |
FOP_CONDS(d) |
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| 518 |
FOP_CONDS(s) |
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| 519 |
FOP_CONDS(ps) |
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| 517 |
FOP_CONDS(, d) |
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| 518 |
FOP_CONDS(abs, d) |
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| 519 |
FOP_CONDS(, s) |
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| 520 |
FOP_CONDS(abs, s) |
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| 521 |
FOP_CONDS(, ps) |
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| 522 |
FOP_CONDS(abs, ps) |
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| 520 | 523 |
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| 521 | 524 |
typedef struct DisasContext {
|
| 522 | 525 |
struct TranslationBlock *tb; |
| ... | ... | |
| 4453 | 4456 |
"c.le", |
| 4454 | 4457 |
"c.ngt", |
| 4455 | 4458 |
}; |
| 4456 |
int binary = 0; |
|
| 4459 |
const char *condnames_abs[] = {
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| 4460 |
"cabs.f", |
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| 4461 |
"cabs.un", |
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| 4462 |
"cabs.eq", |
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| 4463 |
"cabs.ueq", |
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| 4464 |
"cabs.olt", |
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| 4465 |
"cabs.ult", |
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| 4466 |
"cabs.ole", |
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| 4467 |
"cabs.ule", |
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| 4468 |
"cabs.sf", |
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| 4469 |
"cabs.ngle", |
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| 4470 |
"cabs.seq", |
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| 4471 |
"cabs.ngl", |
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| 4472 |
"cabs.lt", |
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| 4473 |
"cabs.nge", |
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| 4474 |
"cabs.le", |
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| 4475 |
"cabs.ngt", |
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| 4476 |
}; |
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| 4477 |
enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
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| 4457 | 4478 |
uint32_t func = ctx->opcode & 0x3f; |
| 4458 | 4479 |
|
| 4459 | 4480 |
switch (ctx->opcode & FOP(0x3f, 0x1f)) {
|
| ... | ... | |
| 4463 | 4484 |
gen_op_float_add_s(); |
| 4464 | 4485 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4465 | 4486 |
opn = "add.s"; |
| 4466 |
binary = 1;
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| 4487 |
optype = BINOP;
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| 4467 | 4488 |
break; |
| 4468 | 4489 |
case FOP(1, 16): |
| 4469 | 4490 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| ... | ... | |
| 4471 | 4492 |
gen_op_float_sub_s(); |
| 4472 | 4493 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4473 | 4494 |
opn = "sub.s"; |
| 4474 |
binary = 1;
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| 4495 |
optype = BINOP;
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| 4475 | 4496 |
break; |
| 4476 | 4497 |
case FOP(2, 16): |
| 4477 | 4498 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| ... | ... | |
| 4479 | 4500 |
gen_op_float_mul_s(); |
| 4480 | 4501 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4481 | 4502 |
opn = "mul.s"; |
| 4482 |
binary = 1;
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| 4503 |
optype = BINOP;
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|
| 4483 | 4504 |
break; |
| 4484 | 4505 |
case FOP(3, 16): |
| 4485 | 4506 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| ... | ... | |
| 4487 | 4508 |
gen_op_float_div_s(); |
| 4488 | 4509 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4489 | 4510 |
opn = "div.s"; |
| 4490 |
binary = 1;
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| 4511 |
optype = BINOP;
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| 4491 | 4512 |
break; |
| 4492 | 4513 |
case FOP(4, 16): |
| 4493 | 4514 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| ... | ... | |
| 4635 | 4656 |
case FOP(63, 16): |
| 4636 | 4657 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4637 | 4658 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| 4638 |
gen_cmp_s(func-48, cc); |
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| 4639 |
opn = condnames[func-48]; |
|
| 4659 |
if (ctx->opcode & (1 << 6)) {
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| 4660 |
gen_cmpabs_s(func-48, cc); |
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| 4661 |
opn = condnames_abs[func-48]; |
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| 4662 |
} else {
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| 4663 |
gen_cmp_s(func-48, cc); |
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| 4664 |
opn = condnames[func-48]; |
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| 4665 |
} |
|
| 4640 | 4666 |
break; |
| 4641 | 4667 |
case FOP(0, 17): |
| 4642 | 4668 |
CHECK_FR(ctx, fs | ft | fd); |
| ... | ... | |
| 4645 | 4671 |
gen_op_float_add_d(); |
| 4646 | 4672 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4647 | 4673 |
opn = "add.d"; |
| 4648 |
binary = 1;
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| 4674 |
optype = BINOP;
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| 4649 | 4675 |
break; |
| 4650 | 4676 |
case FOP(1, 17): |
| 4651 | 4677 |
CHECK_FR(ctx, fs | ft | fd); |
| ... | ... | |
| 4654 | 4680 |
gen_op_float_sub_d(); |
| 4655 | 4681 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4656 | 4682 |
opn = "sub.d"; |
| 4657 |
binary = 1;
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| 4683 |
optype = BINOP;
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| 4658 | 4684 |
break; |
| 4659 | 4685 |
case FOP(2, 17): |
| 4660 | 4686 |
CHECK_FR(ctx, fs | ft | fd); |
| ... | ... | |
| 4663 | 4689 |
gen_op_float_mul_d(); |
| 4664 | 4690 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4665 | 4691 |
opn = "mul.d"; |
| 4666 |
binary = 1;
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| 4692 |
optype = BINOP;
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| 4667 | 4693 |
break; |
| 4668 | 4694 |
case FOP(3, 17): |
| 4669 | 4695 |
CHECK_FR(ctx, fs | ft | fd); |
| ... | ... | |
| 4672 | 4698 |
gen_op_float_div_d(); |
| 4673 | 4699 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4674 | 4700 |
opn = "div.d"; |
| 4675 |
binary = 1;
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| 4701 |
optype = BINOP;
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|
| 4676 | 4702 |
break; |
| 4677 | 4703 |
case FOP(4, 17): |
| 4678 | 4704 |
CHECK_FR(ctx, fs | fd); |
| ... | ... | |
| 4801 | 4827 |
CHECK_FR(ctx, fs | ft); |
| 4802 | 4828 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4803 | 4829 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4804 |
gen_cmp_d(func-48, cc); |
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| 4805 |
opn = condnames[func-48]; |
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| 4830 |
if (ctx->opcode & (1 << 6)) {
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| 4831 |
gen_cmpabs_d(func-48, cc); |
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| 4832 |
opn = condnames_abs[func-48]; |
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| 4833 |
} else {
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| 4834 |
gen_cmp_d(func-48, cc); |
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| 4835 |
opn = condnames[func-48]; |
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| 4836 |
} |
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| 4806 | 4837 |
break; |
| 4807 | 4838 |
case FOP(32, 17): |
| 4808 | 4839 |
CHECK_FR(ctx, fs); |
| ... | ... | |
| 5042 | 5073 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5043 | 5074 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| 5044 | 5075 |
GEN_LOAD_FREG_FTN(WTH1, ft); |
| 5045 |
gen_cmp_ps(func-48, cc); |
|
| 5046 |
opn = condnames[func-48]; |
|
| 5076 |
if (ctx->opcode & (1 << 6)) {
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| 5077 |
gen_cmpabs_ps(func-48, cc); |
|
| 5078 |
opn = condnames_abs[func-48]; |
|
| 5079 |
} else {
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|
| 5080 |
gen_cmp_ps(func-48, cc); |
|
| 5081 |
opn = condnames[func-48]; |
|
| 5082 |
} |
|
| 5047 | 5083 |
break; |
| 5048 | 5084 |
default: |
| 5049 | 5085 |
MIPS_INVAL(opn); |
| 5050 | 5086 |
generate_exception (ctx, EXCP_RI); |
| 5051 | 5087 |
return; |
| 5052 | 5088 |
} |
| 5053 |
if (binary) |
|
| 5089 |
switch (optype) {
|
|
| 5090 |
case BINOP: |
|
| 5054 | 5091 |
MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
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| 5055 |
else |
|
| 5092 |
break; |
|
| 5093 |
case CMPOP: |
|
| 5094 |
MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]);
|
|
| 5095 |
break; |
|
| 5096 |
default: |
|
| 5056 | 5097 |
MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
|
| 5098 |
break; |
|
| 5099 |
} |
|
| 5057 | 5100 |
} |
| 5058 | 5101 |
|
| 5059 | 5102 |
/* Coprocessor 3 (FPU) */ |
Also available in: Unified diff