root / target-mips / helper.c @ 5a1e8ffb
History | View | Annotate | Download (16 kB)
1 |
/*
|
---|---|
2 |
* MIPS emulation helpers for qemu.
|
3 |
*
|
4 |
* Copyright (c) 2004-2005 Jocelyn Mayer
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, write to the Free Software
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 |
*/
|
20 |
#include <stdarg.h> |
21 |
#include <stdlib.h> |
22 |
#include <stdio.h> |
23 |
#include <string.h> |
24 |
#include <inttypes.h> |
25 |
#include <signal.h> |
26 |
#include <assert.h> |
27 |
|
28 |
#include "cpu.h" |
29 |
#include "exec-all.h" |
30 |
|
31 |
enum {
|
32 |
TLBRET_DIRTY = -4,
|
33 |
TLBRET_INVALID = -3,
|
34 |
TLBRET_NOMATCH = -2,
|
35 |
TLBRET_BADADDR = -1,
|
36 |
TLBRET_MATCH = 0
|
37 |
}; |
38 |
|
39 |
/* MIPS32 4K MMU emulation */
|
40 |
#ifdef MIPS_USES_R4K_TLB
|
41 |
static int map_address (CPUState *env, target_ulong *physical, int *prot, |
42 |
target_ulong address, int rw, int access_type) |
43 |
{ |
44 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
45 |
int i;
|
46 |
|
47 |
for (i = 0; i < env->tlb_in_use; i++) { |
48 |
tlb_t *tlb = &env->tlb[i]; |
49 |
/* 1k pages are not supported. */
|
50 |
target_ulong mask = tlb->PageMask | 0x1FFF;
|
51 |
target_ulong tag = address & ~mask; |
52 |
int n;
|
53 |
|
54 |
/* Check ASID, virtual page number & size */
|
55 |
if ((tlb->G == 1 || tlb->ASID == ASID) && |
56 |
tlb->VPN == tag) { |
57 |
/* TLB match */
|
58 |
n = !!(address & mask & ~(mask >> 1));
|
59 |
/* Check access rights */
|
60 |
if (!(n ? tlb->V1 : tlb->V0))
|
61 |
return TLBRET_INVALID;
|
62 |
if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
63 |
*physical = tlb->PFN[n] | (address & (mask >> 1));
|
64 |
*prot = PAGE_READ; |
65 |
if (n ? tlb->D1 : tlb->D0)
|
66 |
*prot |= PAGE_WRITE; |
67 |
return TLBRET_MATCH;
|
68 |
} |
69 |
return TLBRET_DIRTY;
|
70 |
} |
71 |
} |
72 |
return TLBRET_NOMATCH;
|
73 |
} |
74 |
#endif
|
75 |
|
76 |
static int get_physical_address (CPUState *env, target_ulong *physical, |
77 |
int *prot, target_ulong address,
|
78 |
int rw, int access_type) |
79 |
{ |
80 |
/* User mode can only access useg/xuseg */
|
81 |
int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
|
82 |
#ifdef TARGET_MIPS64
|
83 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
84 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
85 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
86 |
#endif
|
87 |
int ret = TLBRET_MATCH;
|
88 |
|
89 |
#if 0
|
90 |
if (logfile) {
|
91 |
fprintf(logfile, "user mode %d h %08x\n",
|
92 |
user_mode, env->hflags);
|
93 |
}
|
94 |
#endif
|
95 |
|
96 |
#ifdef TARGET_MIPS64
|
97 |
if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) |
98 |
return TLBRET_BADADDR;
|
99 |
#else
|
100 |
if (user_mode && address > 0x7FFFFFFFUL) |
101 |
return TLBRET_BADADDR;
|
102 |
#endif
|
103 |
|
104 |
if (address <= (int32_t)0x7FFFFFFFUL) { |
105 |
/* useg */
|
106 |
if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) { |
107 |
#ifdef MIPS_USES_R4K_TLB
|
108 |
ret = map_address(env, physical, prot, address, rw, access_type); |
109 |
#else
|
110 |
*physical = address + 0x40000000UL;
|
111 |
*prot = PAGE_READ | PAGE_WRITE; |
112 |
#endif
|
113 |
} else {
|
114 |
*physical = address; |
115 |
*prot = PAGE_READ | PAGE_WRITE; |
116 |
} |
117 |
#ifdef TARGET_MIPS64
|
118 |
/*
|
119 |
XXX: Assuming :
|
120 |
- PABITS = 36 (correct for MIPS64R1)
|
121 |
- SEGBITS = 40
|
122 |
*/
|
123 |
} else if (address < 0x3FFFFFFFFFFFFFFFULL) { |
124 |
/* xuseg */
|
125 |
if (UX && address < 0x000000FFFFFFFFFFULL) { |
126 |
ret = map_address(env, physical, prot, address, rw, access_type); |
127 |
} else {
|
128 |
ret = TLBRET_BADADDR; |
129 |
} |
130 |
} else if (address < 0x7FFFFFFFFFFFFFFFULL) { |
131 |
/* xsseg */
|
132 |
if (SX && address < 0x400000FFFFFFFFFFULL) { |
133 |
ret = map_address(env, physical, prot, address, rw, access_type); |
134 |
} else {
|
135 |
ret = TLBRET_BADADDR; |
136 |
} |
137 |
} else if (address < 0xBFFFFFFFFFFFFFFFULL) { |
138 |
/* xkphys */
|
139 |
/* XXX: check supervisor mode */
|
140 |
if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) |
141 |
{ |
142 |
*physical = address & 0X000000FFFFFFFFFFULL;
|
143 |
*prot = PAGE_READ | PAGE_WRITE; |
144 |
} else {
|
145 |
ret = TLBRET_BADADDR; |
146 |
} |
147 |
} else if (address < 0xFFFFFFFF7FFFFFFFULL) { |
148 |
/* xkseg */
|
149 |
/* XXX: check supervisor mode */
|
150 |
if (KX && address < 0xC00000FF7FFFFFFFULL) { |
151 |
ret = map_address(env, physical, prot, address, rw, access_type); |
152 |
} else {
|
153 |
ret = TLBRET_BADADDR; |
154 |
} |
155 |
#endif
|
156 |
} else if (address < (int32_t)0xA0000000UL) { |
157 |
/* kseg0 */
|
158 |
/* XXX: check supervisor mode */
|
159 |
*physical = address - (int32_t)0x80000000UL;
|
160 |
*prot = PAGE_READ | PAGE_WRITE; |
161 |
} else if (address < (int32_t)0xC0000000UL) { |
162 |
/* kseg1 */
|
163 |
/* XXX: check supervisor mode */
|
164 |
*physical = address - (int32_t)0xA0000000UL;
|
165 |
*prot = PAGE_READ | PAGE_WRITE; |
166 |
} else if (address < (int32_t)0xE0000000UL) { |
167 |
/* kseg2 */
|
168 |
#ifdef MIPS_USES_R4K_TLB
|
169 |
ret = map_address(env, physical, prot, address, rw, access_type); |
170 |
#else
|
171 |
*physical = address & 0xFFFFFFFF;
|
172 |
*prot = PAGE_READ | PAGE_WRITE; |
173 |
#endif
|
174 |
} else {
|
175 |
/* kseg3 */
|
176 |
/* XXX: check supervisor mode */
|
177 |
/* XXX: debug segment is not emulated */
|
178 |
#ifdef MIPS_USES_R4K_TLB
|
179 |
ret = map_address(env, physical, prot, address, rw, access_type); |
180 |
#else
|
181 |
*physical = address & 0xFFFFFFFF;
|
182 |
*prot = PAGE_READ | PAGE_WRITE; |
183 |
#endif
|
184 |
} |
185 |
#if 0
|
186 |
if (logfile) {
|
187 |
fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
|
188 |
address, rw, access_type, *physical, *prot, ret);
|
189 |
}
|
190 |
#endif
|
191 |
|
192 |
return ret;
|
193 |
} |
194 |
|
195 |
#if defined(CONFIG_USER_ONLY)
|
196 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
197 |
{ |
198 |
return addr;
|
199 |
} |
200 |
#else
|
201 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
202 |
{ |
203 |
target_ulong phys_addr; |
204 |
int prot;
|
205 |
|
206 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
207 |
return -1; |
208 |
return phys_addr;
|
209 |
} |
210 |
|
211 |
void cpu_mips_init_mmu (CPUState *env)
|
212 |
{ |
213 |
} |
214 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
215 |
|
216 |
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
217 |
int is_user, int is_softmmu) |
218 |
{ |
219 |
target_ulong physical; |
220 |
int prot;
|
221 |
int exception = 0, error_code = 0; |
222 |
int access_type;
|
223 |
int ret = 0; |
224 |
|
225 |
if (logfile) {
|
226 |
#if 0
|
227 |
cpu_dump_state(env, logfile, fprintf, 0);
|
228 |
#endif
|
229 |
fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
230 |
__func__, env->PC, address, rw, is_user, is_softmmu); |
231 |
} |
232 |
|
233 |
rw &= 1;
|
234 |
|
235 |
/* data access */
|
236 |
/* XXX: put correct access by using cpu_restore_state()
|
237 |
correctly */
|
238 |
access_type = ACCESS_INT; |
239 |
if (env->user_mode_only) {
|
240 |
/* user mode only emulation */
|
241 |
ret = TLBRET_NOMATCH; |
242 |
goto do_fault;
|
243 |
} |
244 |
ret = get_physical_address(env, &physical, &prot, |
245 |
address, rw, access_type); |
246 |
if (logfile) {
|
247 |
fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
248 |
__func__, address, ret, physical, prot); |
249 |
} |
250 |
if (ret == TLBRET_MATCH) {
|
251 |
ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
252 |
physical & TARGET_PAGE_MASK, prot, |
253 |
is_user, is_softmmu); |
254 |
} else if (ret < 0) { |
255 |
do_fault:
|
256 |
switch (ret) {
|
257 |
default:
|
258 |
case TLBRET_BADADDR:
|
259 |
/* Reference to kernel address from user mode or supervisor mode */
|
260 |
/* Reference to supervisor address from user mode */
|
261 |
if (rw)
|
262 |
exception = EXCP_AdES; |
263 |
else
|
264 |
exception = EXCP_AdEL; |
265 |
break;
|
266 |
case TLBRET_NOMATCH:
|
267 |
/* No TLB match for a mapped address */
|
268 |
if (rw)
|
269 |
exception = EXCP_TLBS; |
270 |
else
|
271 |
exception = EXCP_TLBL; |
272 |
error_code = 1;
|
273 |
break;
|
274 |
case TLBRET_INVALID:
|
275 |
/* TLB match with no valid bit */
|
276 |
if (rw)
|
277 |
exception = EXCP_TLBS; |
278 |
else
|
279 |
exception = EXCP_TLBL; |
280 |
break;
|
281 |
case TLBRET_DIRTY:
|
282 |
/* TLB match but 'D' bit is cleared */
|
283 |
exception = EXCP_LTLBL; |
284 |
break;
|
285 |
|
286 |
} |
287 |
/* Raise exception */
|
288 |
env->CP0_BadVAddr = address; |
289 |
env->CP0_Context = (env->CP0_Context & 0xff800000) |
|
290 |
((address >> 9) & 0x007ffff0); |
291 |
env->CP0_EntryHi = |
292 |
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
293 |
env->exception_index = exception; |
294 |
env->error_code = error_code; |
295 |
ret = 1;
|
296 |
} |
297 |
|
298 |
return ret;
|
299 |
} |
300 |
|
301 |
#if defined(CONFIG_USER_ONLY)
|
302 |
void do_interrupt (CPUState *env)
|
303 |
{ |
304 |
env->exception_index = EXCP_NONE; |
305 |
} |
306 |
#else
|
307 |
void do_interrupt (CPUState *env)
|
308 |
{ |
309 |
target_ulong offset; |
310 |
int cause = -1; |
311 |
|
312 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
313 |
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
314 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
315 |
} |
316 |
if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
317 |
(env->hflags & MIPS_HFLAG_DM)) |
318 |
env->exception_index = EXCP_DINT; |
319 |
offset = 0x180;
|
320 |
switch (env->exception_index) {
|
321 |
case EXCP_DSS:
|
322 |
env->CP0_Debug |= 1 << CP0DB_DSS;
|
323 |
/* Debug single step cannot be raised inside a delay slot and
|
324 |
* resume will always occur on the next instruction
|
325 |
* (but we assume the pc has always been updated during
|
326 |
* code translation).
|
327 |
*/
|
328 |
env->CP0_DEPC = env->PC; |
329 |
goto enter_debug_mode;
|
330 |
case EXCP_DINT:
|
331 |
env->CP0_Debug |= 1 << CP0DB_DINT;
|
332 |
goto set_DEPC;
|
333 |
case EXCP_DIB:
|
334 |
env->CP0_Debug |= 1 << CP0DB_DIB;
|
335 |
goto set_DEPC;
|
336 |
case EXCP_DBp:
|
337 |
env->CP0_Debug |= 1 << CP0DB_DBp;
|
338 |
goto set_DEPC;
|
339 |
case EXCP_DDBS:
|
340 |
env->CP0_Debug |= 1 << CP0DB_DDBS;
|
341 |
goto set_DEPC;
|
342 |
case EXCP_DDBL:
|
343 |
env->CP0_Debug |= 1 << CP0DB_DDBL;
|
344 |
set_DEPC:
|
345 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
346 |
/* If the exception was raised from a delay slot,
|
347 |
come back to the jump. */
|
348 |
env->CP0_DEPC = env->PC - 4;
|
349 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
350 |
} else {
|
351 |
env->CP0_DEPC = env->PC; |
352 |
} |
353 |
enter_debug_mode:
|
354 |
env->hflags |= MIPS_HFLAG_DM; |
355 |
env->hflags &= ~MIPS_HFLAG_UM; |
356 |
/* EJTAG probe trap enable is not implemented... */
|
357 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
358 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
359 |
env->PC = (int32_t)0xBFC00480;
|
360 |
break;
|
361 |
case EXCP_RESET:
|
362 |
cpu_reset(env); |
363 |
break;
|
364 |
case EXCP_SRESET:
|
365 |
env->CP0_Status |= (1 << CP0St_SR);
|
366 |
env->CP0_WatchLo = 0;
|
367 |
goto set_error_EPC;
|
368 |
case EXCP_NMI:
|
369 |
env->CP0_Status |= (1 << CP0St_NMI);
|
370 |
set_error_EPC:
|
371 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
372 |
/* If the exception was raised from a delay slot,
|
373 |
come back to the jump. */
|
374 |
env->CP0_ErrorEPC = env->PC - 4;
|
375 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
376 |
} else {
|
377 |
env->CP0_ErrorEPC = env->PC; |
378 |
} |
379 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
380 |
env->hflags &= ~MIPS_HFLAG_UM; |
381 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
382 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
383 |
env->PC = (int32_t)0xBFC00000;
|
384 |
break;
|
385 |
case EXCP_MCHECK:
|
386 |
cause = 24;
|
387 |
goto set_EPC;
|
388 |
case EXCP_EXT_INTERRUPT:
|
389 |
cause = 0;
|
390 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
391 |
offset = 0x200;
|
392 |
goto set_EPC;
|
393 |
case EXCP_DWATCH:
|
394 |
cause = 23;
|
395 |
/* XXX: TODO: manage defered watch exceptions */
|
396 |
goto set_EPC;
|
397 |
case EXCP_AdEL:
|
398 |
cause = 4;
|
399 |
goto set_EPC;
|
400 |
case EXCP_AdES:
|
401 |
cause = 5;
|
402 |
goto set_EPC;
|
403 |
case EXCP_TLBL:
|
404 |
cause = 2;
|
405 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) |
406 |
offset = 0x000;
|
407 |
goto set_EPC;
|
408 |
case EXCP_IBE:
|
409 |
cause = 6;
|
410 |
goto set_EPC;
|
411 |
case EXCP_DBE:
|
412 |
cause = 7;
|
413 |
goto set_EPC;
|
414 |
case EXCP_SYSCALL:
|
415 |
cause = 8;
|
416 |
goto set_EPC;
|
417 |
case EXCP_BREAK:
|
418 |
cause = 9;
|
419 |
goto set_EPC;
|
420 |
case EXCP_RI:
|
421 |
cause = 10;
|
422 |
goto set_EPC;
|
423 |
case EXCP_CpU:
|
424 |
cause = 11;
|
425 |
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
426 |
(env->error_code << CP0Ca_CE); |
427 |
goto set_EPC;
|
428 |
case EXCP_OVERFLOW:
|
429 |
cause = 12;
|
430 |
goto set_EPC;
|
431 |
case EXCP_TRAP:
|
432 |
cause = 13;
|
433 |
goto set_EPC;
|
434 |
case EXCP_FPE:
|
435 |
cause = 15;
|
436 |
goto set_EPC;
|
437 |
case EXCP_LTLBL:
|
438 |
cause = 1;
|
439 |
goto set_EPC;
|
440 |
case EXCP_TLBS:
|
441 |
cause = 3;
|
442 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) |
443 |
offset = 0x000;
|
444 |
set_EPC:
|
445 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
446 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
447 |
/* If the exception was raised from a delay slot,
|
448 |
come back to the jump. */
|
449 |
env->CP0_EPC = env->PC - 4;
|
450 |
env->CP0_Cause |= (1 << CP0Ca_BD);
|
451 |
} else {
|
452 |
env->CP0_EPC = env->PC; |
453 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
454 |
} |
455 |
env->CP0_Status |= (1 << CP0St_EXL);
|
456 |
env->hflags &= ~MIPS_HFLAG_UM; |
457 |
} |
458 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
459 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
460 |
env->PC = (int32_t)0xBFC00200;
|
461 |
} else {
|
462 |
env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
463 |
} |
464 |
env->PC += offset; |
465 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
466 |
break;
|
467 |
default:
|
468 |
if (logfile) {
|
469 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
470 |
env->exception_index); |
471 |
} |
472 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
473 |
exit(1);
|
474 |
} |
475 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
476 |
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
477 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
478 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
479 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
480 |
env->CP0_DEPC); |
481 |
} |
482 |
env->exception_index = EXCP_NONE; |
483 |
} |
484 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
485 |
|
486 |
void invalidate_tlb (CPUState *env, int idx, int use_extra) |
487 |
{ |
488 |
tlb_t *tlb; |
489 |
target_ulong addr; |
490 |
target_ulong end; |
491 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
492 |
target_ulong mask; |
493 |
|
494 |
tlb = &env->tlb[idx]; |
495 |
/* The qemu TLB is flushed then the ASID changes, so no need to
|
496 |
flush these entries again. */
|
497 |
if (tlb->G == 0 && tlb->ASID != ASID) { |
498 |
return;
|
499 |
} |
500 |
|
501 |
if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
|
502 |
/* For tlbwr, we can shadow the discarded entry into
|
503 |
a new (fake) TLB entry, as long as the guest can not
|
504 |
tell that it's there. */
|
505 |
env->tlb[env->tlb_in_use] = *tlb; |
506 |
env->tlb_in_use++; |
507 |
return;
|
508 |
} |
509 |
|
510 |
/* 1k pages are not supported. */
|
511 |
mask = tlb->PageMask | 0x1FFF;
|
512 |
if (tlb->V0) {
|
513 |
addr = tlb->VPN; |
514 |
end = addr | (mask >> 1);
|
515 |
while (addr < end) {
|
516 |
tlb_flush_page (env, addr); |
517 |
addr += TARGET_PAGE_SIZE; |
518 |
} |
519 |
} |
520 |
if (tlb->V1) {
|
521 |
addr = tlb->VPN | ((mask >> 1) + 1); |
522 |
addr = tlb->VPN + TARGET_PAGE_SIZE; |
523 |
end = addr | mask; |
524 |
while (addr < end) {
|
525 |
tlb_flush_page (env, addr); |
526 |
addr += TARGET_PAGE_SIZE; |
527 |
} |
528 |
} |
529 |
} |