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1 | 42a623c7 | Blue Swirl | /*
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2 | 42a623c7 | Blue Swirl | * User emulator execution
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3 | 42a623c7 | Blue Swirl | *
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4 | 42a623c7 | Blue Swirl | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 42a623c7 | Blue Swirl | *
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6 | 42a623c7 | Blue Swirl | * This library is free software; you can redistribute it and/or
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7 | 42a623c7 | Blue Swirl | * modify it under the terms of the GNU Lesser General Public
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8 | 42a623c7 | Blue Swirl | * License as published by the Free Software Foundation; either
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9 | 42a623c7 | Blue Swirl | * version 2 of the License, or (at your option) any later version.
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10 | 42a623c7 | Blue Swirl | *
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11 | 42a623c7 | Blue Swirl | * This library is distributed in the hope that it will be useful,
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12 | 42a623c7 | Blue Swirl | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 42a623c7 | Blue Swirl | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 42a623c7 | Blue Swirl | * Lesser General Public License for more details.
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15 | 42a623c7 | Blue Swirl | *
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16 | 42a623c7 | Blue Swirl | * You should have received a copy of the GNU Lesser General Public
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17 | 42a623c7 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 42a623c7 | Blue Swirl | */
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19 | 42a623c7 | Blue Swirl | #include "config.h" |
20 | 3e457172 | Blue Swirl | #include "cpu.h" |
21 | 76cad711 | Paolo Bonzini | #include "disas/disas.h" |
22 | 42a623c7 | Blue Swirl | #include "tcg.h" |
23 | 42a623c7 | Blue Swirl | |
24 | 42a623c7 | Blue Swirl | #undef EAX
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25 | 42a623c7 | Blue Swirl | #undef ECX
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26 | 42a623c7 | Blue Swirl | #undef EDX
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27 | 42a623c7 | Blue Swirl | #undef EBX
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28 | 42a623c7 | Blue Swirl | #undef ESP
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29 | 42a623c7 | Blue Swirl | #undef EBP
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30 | 42a623c7 | Blue Swirl | #undef ESI
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31 | 42a623c7 | Blue Swirl | #undef EDI
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32 | 42a623c7 | Blue Swirl | #undef EIP
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33 | 42a623c7 | Blue Swirl | #include <signal.h> |
34 | 42a623c7 | Blue Swirl | #ifdef __linux__
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35 | 42a623c7 | Blue Swirl | #include <sys/ucontext.h> |
36 | 42a623c7 | Blue Swirl | #endif
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37 | 42a623c7 | Blue Swirl | |
38 | 42a623c7 | Blue Swirl | //#define DEBUG_SIGNAL
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39 | 42a623c7 | Blue Swirl | |
40 | 9349b4f9 | Andreas Färber | static void exception_action(CPUArchState *env1) |
41 | 1162c041 | Blue Swirl | { |
42 | 42a623c7 | Blue Swirl | #if defined(TARGET_I386)
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43 | 77b2bc2c | Blue Swirl | raise_exception_err(env1, env1->exception_index, env1->error_code); |
44 | 42a623c7 | Blue Swirl | #else
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45 | 1162c041 | Blue Swirl | cpu_loop_exit(env1); |
46 | 42a623c7 | Blue Swirl | #endif
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47 | 1162c041 | Blue Swirl | } |
48 | 42a623c7 | Blue Swirl | |
49 | 42a623c7 | Blue Swirl | /* exit the current TB from a signal handler. The host registers are
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50 | 42a623c7 | Blue Swirl | restored in a state compatible with the CPU emulator
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51 | 42a623c7 | Blue Swirl | */
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52 | 9349b4f9 | Andreas Färber | void cpu_resume_from_signal(CPUArchState *env1, void *puc) |
53 | 42a623c7 | Blue Swirl | { |
54 | 42a623c7 | Blue Swirl | #ifdef __linux__
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55 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
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56 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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57 | 42a623c7 | Blue Swirl | struct sigcontext *uc = puc;
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58 | 42a623c7 | Blue Swirl | #endif
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59 | 42a623c7 | Blue Swirl | |
60 | 42a623c7 | Blue Swirl | if (puc) {
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61 | 42a623c7 | Blue Swirl | /* XXX: use siglongjmp ? */
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62 | 42a623c7 | Blue Swirl | #ifdef __linux__
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63 | 42a623c7 | Blue Swirl | #ifdef __ia64
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64 | 42a623c7 | Blue Swirl | sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
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65 | 42a623c7 | Blue Swirl | #else
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66 | 42a623c7 | Blue Swirl | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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67 | 42a623c7 | Blue Swirl | #endif
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68 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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69 | 42a623c7 | Blue Swirl | sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
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70 | 42a623c7 | Blue Swirl | #endif
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71 | 42a623c7 | Blue Swirl | } |
72 | 1846ec2c | Blue Swirl | env1->exception_index = -1;
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73 | 6ab7e546 | Peter Maydell | siglongjmp(env1->jmp_env, 1);
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74 | 42a623c7 | Blue Swirl | } |
75 | 42a623c7 | Blue Swirl | |
76 | 42a623c7 | Blue Swirl | /* 'pc' is the host PC at which the exception was raised. 'address' is
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77 | 42a623c7 | Blue Swirl | the effective address of the memory exception. 'is_write' is 1 if a
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78 | 42a623c7 | Blue Swirl | write caused the exception and otherwise 0'. 'old_set' is the
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79 | 42a623c7 | Blue Swirl | signal set which should be restored */
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80 | 20503968 | Blue Swirl | static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, |
81 | 42a623c7 | Blue Swirl | int is_write, sigset_t *old_set,
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82 | 42a623c7 | Blue Swirl | void *puc)
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83 | 42a623c7 | Blue Swirl | { |
84 | 42a623c7 | Blue Swirl | int ret;
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85 | 42a623c7 | Blue Swirl | |
86 | 42a623c7 | Blue Swirl | #if defined(DEBUG_SIGNAL)
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87 | 42a623c7 | Blue Swirl | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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88 | 42a623c7 | Blue Swirl | pc, address, is_write, *(unsigned long *)old_set); |
89 | 42a623c7 | Blue Swirl | #endif
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90 | 42a623c7 | Blue Swirl | /* XXX: locking issue */
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91 | c5954819 | Peter Maydell | if (is_write && h2g_valid(address)
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92 | c5954819 | Peter Maydell | && page_unprotect(h2g(address), pc, puc)) { |
93 | 42a623c7 | Blue Swirl | return 1; |
94 | 42a623c7 | Blue Swirl | } |
95 | 42a623c7 | Blue Swirl | |
96 | 42a623c7 | Blue Swirl | /* see if it is an MMU fault */
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97 | 1846ec2c | Blue Swirl | ret = cpu_handle_mmu_fault(cpu_single_env, address, is_write, |
98 | 1846ec2c | Blue Swirl | MMU_USER_IDX); |
99 | 42a623c7 | Blue Swirl | if (ret < 0) { |
100 | 42a623c7 | Blue Swirl | return 0; /* not an MMU fault */ |
101 | 42a623c7 | Blue Swirl | } |
102 | 42a623c7 | Blue Swirl | if (ret == 0) { |
103 | 42a623c7 | Blue Swirl | return 1; /* the MMU fault was handled without causing real CPU fault */ |
104 | 42a623c7 | Blue Swirl | } |
105 | 42a623c7 | Blue Swirl | /* now we have a real cpu fault */
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106 | a8a826a3 | Blue Swirl | cpu_restore_state(cpu_single_env, pc); |
107 | 42a623c7 | Blue Swirl | |
108 | 42a623c7 | Blue Swirl | /* we restore the process signal mask as the sigreturn should
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109 | 42a623c7 | Blue Swirl | do it (XXX: use sigsetjmp) */
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110 | 42a623c7 | Blue Swirl | sigprocmask(SIG_SETMASK, old_set, NULL);
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111 | 1846ec2c | Blue Swirl | exception_action(cpu_single_env); |
112 | 42a623c7 | Blue Swirl | |
113 | 42a623c7 | Blue Swirl | /* never comes here */
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114 | 42a623c7 | Blue Swirl | return 1; |
115 | 42a623c7 | Blue Swirl | } |
116 | 42a623c7 | Blue Swirl | |
117 | 42a623c7 | Blue Swirl | #if defined(__i386__)
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118 | 42a623c7 | Blue Swirl | |
119 | 42a623c7 | Blue Swirl | #if defined(__APPLE__)
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120 | 42a623c7 | Blue Swirl | #include <sys/ucontext.h> |
121 | 42a623c7 | Blue Swirl | |
122 | 42a623c7 | Blue Swirl | #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip)) |
123 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
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124 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext->es.err)
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125 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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126 | 42a623c7 | Blue Swirl | #elif defined(__NetBSD__)
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127 | 42a623c7 | Blue Swirl | #include <ucontext.h> |
128 | 42a623c7 | Blue Swirl | |
129 | 42a623c7 | Blue Swirl | #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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130 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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131 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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132 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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133 | 42a623c7 | Blue Swirl | #elif defined(__FreeBSD__) || defined(__DragonFly__)
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134 | 42a623c7 | Blue Swirl | #include <ucontext.h> |
135 | 42a623c7 | Blue Swirl | |
136 | 42a623c7 | Blue Swirl | #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) |
137 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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138 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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139 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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140 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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141 | 42a623c7 | Blue Swirl | #define EIP_sig(context) ((context)->sc_eip)
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142 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->sc_trapno)
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143 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->sc_err)
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144 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->sc_mask)
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145 | 42a623c7 | Blue Swirl | #else
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146 | 42a623c7 | Blue Swirl | #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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147 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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148 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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149 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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150 | 42a623c7 | Blue Swirl | #endif
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151 | 42a623c7 | Blue Swirl | |
152 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
153 | 42a623c7 | Blue Swirl | void *puc)
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154 | 42a623c7 | Blue Swirl | { |
155 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
156 | 42a623c7 | Blue Swirl | #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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157 | 42a623c7 | Blue Swirl | ucontext_t *uc = puc; |
158 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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159 | 42a623c7 | Blue Swirl | struct sigcontext *uc = puc;
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160 | 42a623c7 | Blue Swirl | #else
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161 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
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162 | 42a623c7 | Blue Swirl | #endif
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163 | 42a623c7 | Blue Swirl | unsigned long pc; |
164 | 42a623c7 | Blue Swirl | int trapno;
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165 | 42a623c7 | Blue Swirl | |
166 | 42a623c7 | Blue Swirl | #ifndef REG_EIP
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167 | 42a623c7 | Blue Swirl | /* for glibc 2.1 */
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168 | 42a623c7 | Blue Swirl | #define REG_EIP EIP
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169 | 42a623c7 | Blue Swirl | #define REG_ERR ERR
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170 | 42a623c7 | Blue Swirl | #define REG_TRAPNO TRAPNO
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171 | 42a623c7 | Blue Swirl | #endif
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172 | 42a623c7 | Blue Swirl | pc = EIP_sig(uc); |
173 | 42a623c7 | Blue Swirl | trapno = TRAP_sig(uc); |
174 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
175 | 42a623c7 | Blue Swirl | trapno == 0xe ?
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176 | 42a623c7 | Blue Swirl | (ERROR_sig(uc) >> 1) & 1 : 0, |
177 | 42a623c7 | Blue Swirl | &MASK_sig(uc), puc); |
178 | 42a623c7 | Blue Swirl | } |
179 | 42a623c7 | Blue Swirl | |
180 | 42a623c7 | Blue Swirl | #elif defined(__x86_64__)
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181 | 42a623c7 | Blue Swirl | |
182 | 42a623c7 | Blue Swirl | #ifdef __NetBSD__
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183 | 42a623c7 | Blue Swirl | #define PC_sig(context) _UC_MACHINE_PC(context)
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184 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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185 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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186 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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187 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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188 | 42a623c7 | Blue Swirl | #define PC_sig(context) ((context)->sc_rip)
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189 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->sc_trapno)
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190 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->sc_err)
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191 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->sc_mask)
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192 | 42a623c7 | Blue Swirl | #elif defined(__FreeBSD__) || defined(__DragonFly__)
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193 | 42a623c7 | Blue Swirl | #include <ucontext.h> |
194 | 42a623c7 | Blue Swirl | |
195 | 42a623c7 | Blue Swirl | #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) |
196 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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197 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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198 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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199 | 42a623c7 | Blue Swirl | #else
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200 | 42a623c7 | Blue Swirl | #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
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201 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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202 | 42a623c7 | Blue Swirl | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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203 | 42a623c7 | Blue Swirl | #define MASK_sig(context) ((context)->uc_sigmask)
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204 | 42a623c7 | Blue Swirl | #endif
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205 | 42a623c7 | Blue Swirl | |
206 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
207 | 42a623c7 | Blue Swirl | void *puc)
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208 | 42a623c7 | Blue Swirl | { |
209 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
210 | 42a623c7 | Blue Swirl | unsigned long pc; |
211 | 42a623c7 | Blue Swirl | #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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212 | 42a623c7 | Blue Swirl | ucontext_t *uc = puc; |
213 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
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214 | 42a623c7 | Blue Swirl | struct sigcontext *uc = puc;
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215 | 42a623c7 | Blue Swirl | #else
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216 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
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217 | 42a623c7 | Blue Swirl | #endif
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218 | 42a623c7 | Blue Swirl | |
219 | 42a623c7 | Blue Swirl | pc = PC_sig(uc); |
220 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
221 | 42a623c7 | Blue Swirl | TRAP_sig(uc) == 0xe ?
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222 | 42a623c7 | Blue Swirl | (ERROR_sig(uc) >> 1) & 1 : 0, |
223 | 42a623c7 | Blue Swirl | &MASK_sig(uc), puc); |
224 | 42a623c7 | Blue Swirl | } |
225 | 42a623c7 | Blue Swirl | |
226 | 42a623c7 | Blue Swirl | #elif defined(_ARCH_PPC)
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227 | 42a623c7 | Blue Swirl | |
228 | 42a623c7 | Blue Swirl | /***********************************************************************
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229 | 42a623c7 | Blue Swirl | * signal context platform-specific definitions
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230 | 42a623c7 | Blue Swirl | * From Wine
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231 | 42a623c7 | Blue Swirl | */
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232 | 42a623c7 | Blue Swirl | #ifdef linux
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233 | 42a623c7 | Blue Swirl | /* All Registers access - only for local access */
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234 | 42a623c7 | Blue Swirl | #define REG_sig(reg_name, context) \
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235 | 42a623c7 | Blue Swirl | ((context)->uc_mcontext.regs->reg_name) |
236 | 42a623c7 | Blue Swirl | /* Gpr Registers access */
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237 | 42a623c7 | Blue Swirl | #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
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238 | 42a623c7 | Blue Swirl | /* Program counter */
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239 | 42a623c7 | Blue Swirl | #define IAR_sig(context) REG_sig(nip, context)
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240 | 42a623c7 | Blue Swirl | /* Machine State Register (Supervisor) */
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241 | 42a623c7 | Blue Swirl | #define MSR_sig(context) REG_sig(msr, context)
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242 | 42a623c7 | Blue Swirl | /* Count register */
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243 | 42a623c7 | Blue Swirl | #define CTR_sig(context) REG_sig(ctr, context)
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244 | 42a623c7 | Blue Swirl | /* User's integer exception register */
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245 | 42a623c7 | Blue Swirl | #define XER_sig(context) REG_sig(xer, context)
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246 | 42a623c7 | Blue Swirl | /* Link register */
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247 | 42a623c7 | Blue Swirl | #define LR_sig(context) REG_sig(link, context)
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248 | 42a623c7 | Blue Swirl | /* Condition register */
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249 | 42a623c7 | Blue Swirl | #define CR_sig(context) REG_sig(ccr, context)
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250 | 42a623c7 | Blue Swirl | |
251 | 42a623c7 | Blue Swirl | /* Float Registers access */
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252 | 42a623c7 | Blue Swirl | #define FLOAT_sig(reg_num, context) \
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253 | 42a623c7 | Blue Swirl | (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) |
254 | 42a623c7 | Blue Swirl | #define FPSCR_sig(context) \
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255 | 42a623c7 | Blue Swirl | (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) |
256 | 42a623c7 | Blue Swirl | /* Exception Registers access */
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257 | 42a623c7 | Blue Swirl | #define DAR_sig(context) REG_sig(dar, context)
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258 | 42a623c7 | Blue Swirl | #define DSISR_sig(context) REG_sig(dsisr, context)
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259 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) REG_sig(trap, context)
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260 | 42a623c7 | Blue Swirl | #endif /* linux */ |
261 | 42a623c7 | Blue Swirl | |
262 | 42a623c7 | Blue Swirl | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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263 | 42a623c7 | Blue Swirl | #include <ucontext.h> |
264 | 42a623c7 | Blue Swirl | #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
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265 | 42a623c7 | Blue Swirl | #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
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266 | 42a623c7 | Blue Swirl | #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
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267 | 42a623c7 | Blue Swirl | #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
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268 | 42a623c7 | Blue Swirl | #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
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269 | 42a623c7 | Blue Swirl | #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
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270 | 42a623c7 | Blue Swirl | /* Exception Registers access */
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271 | 42a623c7 | Blue Swirl | #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
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272 | 42a623c7 | Blue Swirl | #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
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273 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
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274 | 42a623c7 | Blue Swirl | #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ |
275 | 42a623c7 | Blue Swirl | |
276 | 42a623c7 | Blue Swirl | #ifdef __APPLE__
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277 | 42a623c7 | Blue Swirl | #include <sys/ucontext.h> |
278 | 42a623c7 | Blue Swirl | typedef struct ucontext SIGCONTEXT; |
279 | 42a623c7 | Blue Swirl | /* All Registers access - only for local access */
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280 | 42a623c7 | Blue Swirl | #define REG_sig(reg_name, context) \
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281 | 42a623c7 | Blue Swirl | ((context)->uc_mcontext->ss.reg_name) |
282 | 42a623c7 | Blue Swirl | #define FLOATREG_sig(reg_name, context) \
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283 | 42a623c7 | Blue Swirl | ((context)->uc_mcontext->fs.reg_name) |
284 | 42a623c7 | Blue Swirl | #define EXCEPREG_sig(reg_name, context) \
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285 | 42a623c7 | Blue Swirl | ((context)->uc_mcontext->es.reg_name) |
286 | 42a623c7 | Blue Swirl | #define VECREG_sig(reg_name, context) \
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287 | 42a623c7 | Blue Swirl | ((context)->uc_mcontext->vs.reg_name) |
288 | 42a623c7 | Blue Swirl | /* Gpr Registers access */
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289 | 42a623c7 | Blue Swirl | #define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
290 | 42a623c7 | Blue Swirl | /* Program counter */
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291 | 42a623c7 | Blue Swirl | #define IAR_sig(context) REG_sig(srr0, context)
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292 | 42a623c7 | Blue Swirl | /* Machine State Register (Supervisor) */
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293 | 42a623c7 | Blue Swirl | #define MSR_sig(context) REG_sig(srr1, context)
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294 | 42a623c7 | Blue Swirl | #define CTR_sig(context) REG_sig(ctr, context)
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295 | 42a623c7 | Blue Swirl | /* Link register */
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296 | 42a623c7 | Blue Swirl | #define XER_sig(context) REG_sig(xer, context)
|
297 | 42a623c7 | Blue Swirl | /* User's integer exception register */
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298 | 42a623c7 | Blue Swirl | #define LR_sig(context) REG_sig(lr, context)
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299 | 42a623c7 | Blue Swirl | /* Condition register */
|
300 | 42a623c7 | Blue Swirl | #define CR_sig(context) REG_sig(cr, context)
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301 | 42a623c7 | Blue Swirl | /* Float Registers access */
|
302 | 42a623c7 | Blue Swirl | #define FLOAT_sig(reg_num, context) \
|
303 | 42a623c7 | Blue Swirl | FLOATREG_sig(fpregs[reg_num], context) |
304 | 42a623c7 | Blue Swirl | #define FPSCR_sig(context) \
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305 | 42a623c7 | Blue Swirl | ((double)FLOATREG_sig(fpscr, context))
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306 | 42a623c7 | Blue Swirl | /* Exception Registers access */
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307 | 42a623c7 | Blue Swirl | /* Fault registers for coredump */
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308 | 42a623c7 | Blue Swirl | #define DAR_sig(context) EXCEPREG_sig(dar, context)
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309 | 42a623c7 | Blue Swirl | #define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
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310 | 42a623c7 | Blue Swirl | /* number of powerpc exception taken */
|
311 | 42a623c7 | Blue Swirl | #define TRAP_sig(context) EXCEPREG_sig(exception, context)
|
312 | 42a623c7 | Blue Swirl | #endif /* __APPLE__ */ |
313 | 42a623c7 | Blue Swirl | |
314 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
315 | 42a623c7 | Blue Swirl | void *puc)
|
316 | 42a623c7 | Blue Swirl | { |
317 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
318 | 42a623c7 | Blue Swirl | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
319 | 42a623c7 | Blue Swirl | ucontext_t *uc = puc; |
320 | 42a623c7 | Blue Swirl | #else
|
321 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
322 | 42a623c7 | Blue Swirl | #endif
|
323 | 42a623c7 | Blue Swirl | unsigned long pc; |
324 | 42a623c7 | Blue Swirl | int is_write;
|
325 | 42a623c7 | Blue Swirl | |
326 | 42a623c7 | Blue Swirl | pc = IAR_sig(uc); |
327 | 42a623c7 | Blue Swirl | is_write = 0;
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328 | 42a623c7 | Blue Swirl | #if 0
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329 | 42a623c7 | Blue Swirl | /* ppc 4xx case */
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330 | 42a623c7 | Blue Swirl | if (DSISR_sig(uc) & 0x00800000) {
|
331 | 42a623c7 | Blue Swirl | is_write = 1;
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332 | 42a623c7 | Blue Swirl | }
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333 | 42a623c7 | Blue Swirl | #else
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334 | 42a623c7 | Blue Swirl | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { |
335 | 42a623c7 | Blue Swirl | is_write = 1;
|
336 | 42a623c7 | Blue Swirl | } |
337 | 42a623c7 | Blue Swirl | #endif
|
338 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
339 | 42a623c7 | Blue Swirl | is_write, &uc->uc_sigmask, puc); |
340 | 42a623c7 | Blue Swirl | } |
341 | 42a623c7 | Blue Swirl | |
342 | 42a623c7 | Blue Swirl | #elif defined(__alpha__)
|
343 | 42a623c7 | Blue Swirl | |
344 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
345 | 42a623c7 | Blue Swirl | void *puc)
|
346 | 42a623c7 | Blue Swirl | { |
347 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
348 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
349 | 42a623c7 | Blue Swirl | uint32_t *pc = uc->uc_mcontext.sc_pc; |
350 | 42a623c7 | Blue Swirl | uint32_t insn = *pc; |
351 | 42a623c7 | Blue Swirl | int is_write = 0; |
352 | 42a623c7 | Blue Swirl | |
353 | 42a623c7 | Blue Swirl | /* XXX: need kernel patch to get write flag faster */
|
354 | 42a623c7 | Blue Swirl | switch (insn >> 26) { |
355 | 42a623c7 | Blue Swirl | case 0x0d: /* stw */ |
356 | 42a623c7 | Blue Swirl | case 0x0e: /* stb */ |
357 | 42a623c7 | Blue Swirl | case 0x0f: /* stq_u */ |
358 | 42a623c7 | Blue Swirl | case 0x24: /* stf */ |
359 | 42a623c7 | Blue Swirl | case 0x25: /* stg */ |
360 | 42a623c7 | Blue Swirl | case 0x26: /* sts */ |
361 | 42a623c7 | Blue Swirl | case 0x27: /* stt */ |
362 | 42a623c7 | Blue Swirl | case 0x2c: /* stl */ |
363 | 42a623c7 | Blue Swirl | case 0x2d: /* stq */ |
364 | 42a623c7 | Blue Swirl | case 0x2e: /* stl_c */ |
365 | 42a623c7 | Blue Swirl | case 0x2f: /* stq_c */ |
366 | 42a623c7 | Blue Swirl | is_write = 1;
|
367 | 42a623c7 | Blue Swirl | } |
368 | 42a623c7 | Blue Swirl | |
369 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
370 | 42a623c7 | Blue Swirl | is_write, &uc->uc_sigmask, puc); |
371 | 42a623c7 | Blue Swirl | } |
372 | 42a623c7 | Blue Swirl | #elif defined(__sparc__)
|
373 | 42a623c7 | Blue Swirl | |
374 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
375 | 42a623c7 | Blue Swirl | void *puc)
|
376 | 42a623c7 | Blue Swirl | { |
377 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
378 | 42a623c7 | Blue Swirl | int is_write;
|
379 | 42a623c7 | Blue Swirl | uint32_t insn; |
380 | 42a623c7 | Blue Swirl | #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
|
381 | 42a623c7 | Blue Swirl | uint32_t *regs = (uint32_t *)(info + 1);
|
382 | 42a623c7 | Blue Swirl | void *sigmask = (regs + 20); |
383 | 42a623c7 | Blue Swirl | /* XXX: is there a standard glibc define ? */
|
384 | 42a623c7 | Blue Swirl | unsigned long pc = regs[1]; |
385 | 42a623c7 | Blue Swirl | #else
|
386 | 42a623c7 | Blue Swirl | #ifdef __linux__
|
387 | 42a623c7 | Blue Swirl | struct sigcontext *sc = puc;
|
388 | 42a623c7 | Blue Swirl | unsigned long pc = sc->sigc_regs.tpc; |
389 | 42a623c7 | Blue Swirl | void *sigmask = (void *)sc->sigc_mask; |
390 | 42a623c7 | Blue Swirl | #elif defined(__OpenBSD__)
|
391 | 42a623c7 | Blue Swirl | struct sigcontext *uc = puc;
|
392 | 42a623c7 | Blue Swirl | unsigned long pc = uc->sc_pc; |
393 | 42a623c7 | Blue Swirl | void *sigmask = (void *)(long)uc->sc_mask; |
394 | 42a623c7 | Blue Swirl | #endif
|
395 | 42a623c7 | Blue Swirl | #endif
|
396 | 42a623c7 | Blue Swirl | |
397 | 42a623c7 | Blue Swirl | /* XXX: need kernel patch to get write flag faster */
|
398 | 42a623c7 | Blue Swirl | is_write = 0;
|
399 | 42a623c7 | Blue Swirl | insn = *(uint32_t *)pc; |
400 | 42a623c7 | Blue Swirl | if ((insn >> 30) == 3) { |
401 | 42a623c7 | Blue Swirl | switch ((insn >> 19) & 0x3f) { |
402 | 42a623c7 | Blue Swirl | case 0x05: /* stb */ |
403 | 42a623c7 | Blue Swirl | case 0x15: /* stba */ |
404 | 42a623c7 | Blue Swirl | case 0x06: /* sth */ |
405 | 42a623c7 | Blue Swirl | case 0x16: /* stha */ |
406 | 42a623c7 | Blue Swirl | case 0x04: /* st */ |
407 | 42a623c7 | Blue Swirl | case 0x14: /* sta */ |
408 | 42a623c7 | Blue Swirl | case 0x07: /* std */ |
409 | 42a623c7 | Blue Swirl | case 0x17: /* stda */ |
410 | 42a623c7 | Blue Swirl | case 0x0e: /* stx */ |
411 | 42a623c7 | Blue Swirl | case 0x1e: /* stxa */ |
412 | 42a623c7 | Blue Swirl | case 0x24: /* stf */ |
413 | 42a623c7 | Blue Swirl | case 0x34: /* stfa */ |
414 | 42a623c7 | Blue Swirl | case 0x27: /* stdf */ |
415 | 42a623c7 | Blue Swirl | case 0x37: /* stdfa */ |
416 | 42a623c7 | Blue Swirl | case 0x26: /* stqf */ |
417 | 42a623c7 | Blue Swirl | case 0x36: /* stqfa */ |
418 | 42a623c7 | Blue Swirl | case 0x25: /* stfsr */ |
419 | 42a623c7 | Blue Swirl | case 0x3c: /* casa */ |
420 | 42a623c7 | Blue Swirl | case 0x3e: /* casxa */ |
421 | 42a623c7 | Blue Swirl | is_write = 1;
|
422 | 42a623c7 | Blue Swirl | break;
|
423 | 42a623c7 | Blue Swirl | } |
424 | 42a623c7 | Blue Swirl | } |
425 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
426 | 42a623c7 | Blue Swirl | is_write, sigmask, NULL);
|
427 | 42a623c7 | Blue Swirl | } |
428 | 42a623c7 | Blue Swirl | |
429 | 42a623c7 | Blue Swirl | #elif defined(__arm__)
|
430 | 42a623c7 | Blue Swirl | |
431 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
432 | 42a623c7 | Blue Swirl | void *puc)
|
433 | 42a623c7 | Blue Swirl | { |
434 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
435 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
436 | 42a623c7 | Blue Swirl | unsigned long pc; |
437 | 42a623c7 | Blue Swirl | int is_write;
|
438 | 42a623c7 | Blue Swirl | |
439 | e12cdb1b | John Spencer | #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
440 | 42a623c7 | Blue Swirl | pc = uc->uc_mcontext.gregs[R15]; |
441 | 42a623c7 | Blue Swirl | #else
|
442 | 42a623c7 | Blue Swirl | pc = uc->uc_mcontext.arm_pc; |
443 | 42a623c7 | Blue Swirl | #endif
|
444 | 42a623c7 | Blue Swirl | /* XXX: compute is_write */
|
445 | 42a623c7 | Blue Swirl | is_write = 0;
|
446 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
447 | 42a623c7 | Blue Swirl | is_write, |
448 | 42a623c7 | Blue Swirl | &uc->uc_sigmask, puc); |
449 | 42a623c7 | Blue Swirl | } |
450 | 42a623c7 | Blue Swirl | |
451 | 42a623c7 | Blue Swirl | #elif defined(__mc68000)
|
452 | 42a623c7 | Blue Swirl | |
453 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
454 | 42a623c7 | Blue Swirl | void *puc)
|
455 | 42a623c7 | Blue Swirl | { |
456 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
457 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
458 | 42a623c7 | Blue Swirl | unsigned long pc; |
459 | 42a623c7 | Blue Swirl | int is_write;
|
460 | 42a623c7 | Blue Swirl | |
461 | 42a623c7 | Blue Swirl | pc = uc->uc_mcontext.gregs[16];
|
462 | 42a623c7 | Blue Swirl | /* XXX: compute is_write */
|
463 | 42a623c7 | Blue Swirl | is_write = 0;
|
464 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
465 | 42a623c7 | Blue Swirl | is_write, |
466 | 42a623c7 | Blue Swirl | &uc->uc_sigmask, puc); |
467 | 42a623c7 | Blue Swirl | } |
468 | 42a623c7 | Blue Swirl | |
469 | 42a623c7 | Blue Swirl | #elif defined(__ia64)
|
470 | 42a623c7 | Blue Swirl | |
471 | 42a623c7 | Blue Swirl | #ifndef __ISR_VALID
|
472 | 42a623c7 | Blue Swirl | /* This ought to be in <bits/siginfo.h>... */
|
473 | 42a623c7 | Blue Swirl | # define __ISR_VALID 1 |
474 | 42a623c7 | Blue Swirl | #endif
|
475 | 42a623c7 | Blue Swirl | |
476 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
477 | 42a623c7 | Blue Swirl | { |
478 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
479 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
480 | 42a623c7 | Blue Swirl | unsigned long ip; |
481 | 42a623c7 | Blue Swirl | int is_write = 0; |
482 | 42a623c7 | Blue Swirl | |
483 | 42a623c7 | Blue Swirl | ip = uc->uc_mcontext.sc_ip; |
484 | 42a623c7 | Blue Swirl | switch (host_signum) {
|
485 | 42a623c7 | Blue Swirl | case SIGILL:
|
486 | 42a623c7 | Blue Swirl | case SIGFPE:
|
487 | 42a623c7 | Blue Swirl | case SIGSEGV:
|
488 | 42a623c7 | Blue Swirl | case SIGBUS:
|
489 | 42a623c7 | Blue Swirl | case SIGTRAP:
|
490 | 42a623c7 | Blue Swirl | if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
|
491 | 42a623c7 | Blue Swirl | /* ISR.W (write-access) is bit 33: */
|
492 | 42a623c7 | Blue Swirl | is_write = (info->si_isr >> 33) & 1; |
493 | 42a623c7 | Blue Swirl | } |
494 | 42a623c7 | Blue Swirl | break;
|
495 | 42a623c7 | Blue Swirl | |
496 | 42a623c7 | Blue Swirl | default:
|
497 | 42a623c7 | Blue Swirl | break;
|
498 | 42a623c7 | Blue Swirl | } |
499 | 42a623c7 | Blue Swirl | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
500 | 42a623c7 | Blue Swirl | is_write, |
501 | 42a623c7 | Blue Swirl | (sigset_t *)&uc->uc_sigmask, puc); |
502 | 42a623c7 | Blue Swirl | } |
503 | 42a623c7 | Blue Swirl | |
504 | 42a623c7 | Blue Swirl | #elif defined(__s390__)
|
505 | 42a623c7 | Blue Swirl | |
506 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
507 | 42a623c7 | Blue Swirl | void *puc)
|
508 | 42a623c7 | Blue Swirl | { |
509 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
510 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
511 | 42a623c7 | Blue Swirl | unsigned long pc; |
512 | 42a623c7 | Blue Swirl | uint16_t *pinsn; |
513 | 42a623c7 | Blue Swirl | int is_write = 0; |
514 | 42a623c7 | Blue Swirl | |
515 | 42a623c7 | Blue Swirl | pc = uc->uc_mcontext.psw.addr; |
516 | 42a623c7 | Blue Swirl | |
517 | 42a623c7 | Blue Swirl | /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
|
518 | 42a623c7 | Blue Swirl | of the normal 2 arguments. The 3rd argument contains the "int_code"
|
519 | 42a623c7 | Blue Swirl | from the hardware which does in fact contain the is_write value.
|
520 | 42a623c7 | Blue Swirl | The rt signal handler, as far as I can tell, does not give this value
|
521 | 42a623c7 | Blue Swirl | at all. Not that we could get to it from here even if it were. */
|
522 | 42a623c7 | Blue Swirl | /* ??? This is not even close to complete, since it ignores all
|
523 | 42a623c7 | Blue Swirl | of the read-modify-write instructions. */
|
524 | 42a623c7 | Blue Swirl | pinsn = (uint16_t *)pc; |
525 | 42a623c7 | Blue Swirl | switch (pinsn[0] >> 8) { |
526 | 42a623c7 | Blue Swirl | case 0x50: /* ST */ |
527 | 42a623c7 | Blue Swirl | case 0x42: /* STC */ |
528 | 42a623c7 | Blue Swirl | case 0x40: /* STH */ |
529 | 42a623c7 | Blue Swirl | is_write = 1;
|
530 | 42a623c7 | Blue Swirl | break;
|
531 | 42a623c7 | Blue Swirl | case 0xc4: /* RIL format insns */ |
532 | 42a623c7 | Blue Swirl | switch (pinsn[0] & 0xf) { |
533 | 42a623c7 | Blue Swirl | case 0xf: /* STRL */ |
534 | 42a623c7 | Blue Swirl | case 0xb: /* STGRL */ |
535 | 42a623c7 | Blue Swirl | case 0x7: /* STHRL */ |
536 | 42a623c7 | Blue Swirl | is_write = 1;
|
537 | 42a623c7 | Blue Swirl | } |
538 | 42a623c7 | Blue Swirl | break;
|
539 | 42a623c7 | Blue Swirl | case 0xe3: /* RXY format insns */ |
540 | 42a623c7 | Blue Swirl | switch (pinsn[2] & 0xff) { |
541 | 42a623c7 | Blue Swirl | case 0x50: /* STY */ |
542 | 42a623c7 | Blue Swirl | case 0x24: /* STG */ |
543 | 42a623c7 | Blue Swirl | case 0x72: /* STCY */ |
544 | 42a623c7 | Blue Swirl | case 0x70: /* STHY */ |
545 | 42a623c7 | Blue Swirl | case 0x8e: /* STPQ */ |
546 | 42a623c7 | Blue Swirl | case 0x3f: /* STRVH */ |
547 | 42a623c7 | Blue Swirl | case 0x3e: /* STRV */ |
548 | 42a623c7 | Blue Swirl | case 0x2f: /* STRVG */ |
549 | 42a623c7 | Blue Swirl | is_write = 1;
|
550 | 42a623c7 | Blue Swirl | } |
551 | 42a623c7 | Blue Swirl | break;
|
552 | 42a623c7 | Blue Swirl | } |
553 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
554 | 42a623c7 | Blue Swirl | is_write, &uc->uc_sigmask, puc); |
555 | 42a623c7 | Blue Swirl | } |
556 | 42a623c7 | Blue Swirl | |
557 | 42a623c7 | Blue Swirl | #elif defined(__mips__)
|
558 | 42a623c7 | Blue Swirl | |
559 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
560 | 42a623c7 | Blue Swirl | void *puc)
|
561 | 42a623c7 | Blue Swirl | { |
562 | 42a623c7 | Blue Swirl | siginfo_t *info = pinfo; |
563 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
564 | 42a623c7 | Blue Swirl | greg_t pc = uc->uc_mcontext.pc; |
565 | 42a623c7 | Blue Swirl | int is_write;
|
566 | 42a623c7 | Blue Swirl | |
567 | 42a623c7 | Blue Swirl | /* XXX: compute is_write */
|
568 | 42a623c7 | Blue Swirl | is_write = 0;
|
569 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
570 | 42a623c7 | Blue Swirl | is_write, &uc->uc_sigmask, puc); |
571 | 42a623c7 | Blue Swirl | } |
572 | 42a623c7 | Blue Swirl | |
573 | 42a623c7 | Blue Swirl | #elif defined(__hppa__)
|
574 | 42a623c7 | Blue Swirl | |
575 | 42a623c7 | Blue Swirl | int cpu_signal_handler(int host_signum, void *pinfo, |
576 | 42a623c7 | Blue Swirl | void *puc)
|
577 | 42a623c7 | Blue Swirl | { |
578 | 02d2bd5d | Richard W.M. Jones | siginfo_t *info = pinfo; |
579 | 42a623c7 | Blue Swirl | struct ucontext *uc = puc;
|
580 | 42a623c7 | Blue Swirl | unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; |
581 | 42a623c7 | Blue Swirl | uint32_t insn = *(uint32_t *)pc; |
582 | 42a623c7 | Blue Swirl | int is_write = 0; |
583 | 42a623c7 | Blue Swirl | |
584 | 42a623c7 | Blue Swirl | /* XXX: need kernel patch to get write flag faster. */
|
585 | 42a623c7 | Blue Swirl | switch (insn >> 26) { |
586 | 42a623c7 | Blue Swirl | case 0x1a: /* STW */ |
587 | 42a623c7 | Blue Swirl | case 0x19: /* STH */ |
588 | 42a623c7 | Blue Swirl | case 0x18: /* STB */ |
589 | 42a623c7 | Blue Swirl | case 0x1b: /* STWM */ |
590 | 42a623c7 | Blue Swirl | is_write = 1;
|
591 | 42a623c7 | Blue Swirl | break;
|
592 | 42a623c7 | Blue Swirl | |
593 | 42a623c7 | Blue Swirl | case 0x09: /* CSTWX, FSTWX, FSTWS */ |
594 | 42a623c7 | Blue Swirl | case 0x0b: /* CSTDX, FSTDX, FSTDS */ |
595 | 42a623c7 | Blue Swirl | /* Distinguish from coprocessor load ... */
|
596 | 42a623c7 | Blue Swirl | is_write = (insn >> 9) & 1; |
597 | 42a623c7 | Blue Swirl | break;
|
598 | 42a623c7 | Blue Swirl | |
599 | 42a623c7 | Blue Swirl | case 0x03: |
600 | 42a623c7 | Blue Swirl | switch ((insn >> 6) & 15) { |
601 | 42a623c7 | Blue Swirl | case 0xa: /* STWS */ |
602 | 42a623c7 | Blue Swirl | case 0x9: /* STHS */ |
603 | 42a623c7 | Blue Swirl | case 0x8: /* STBS */ |
604 | 42a623c7 | Blue Swirl | case 0xe: /* STWAS */ |
605 | 42a623c7 | Blue Swirl | case 0xc: /* STBYS */ |
606 | 42a623c7 | Blue Swirl | is_write = 1;
|
607 | 42a623c7 | Blue Swirl | } |
608 | 42a623c7 | Blue Swirl | break;
|
609 | 42a623c7 | Blue Swirl | } |
610 | 42a623c7 | Blue Swirl | |
611 | 42a623c7 | Blue Swirl | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
612 | 42a623c7 | Blue Swirl | is_write, &uc->uc_sigmask, puc); |
613 | 42a623c7 | Blue Swirl | } |
614 | 42a623c7 | Blue Swirl | |
615 | 42a623c7 | Blue Swirl | #else
|
616 | 42a623c7 | Blue Swirl | |
617 | 42a623c7 | Blue Swirl | #error host CPU specific signal handler needed
|
618 | 42a623c7 | Blue Swirl | |
619 | 42a623c7 | Blue Swirl | #endif |