memory: move core typedefs to qemu/typedefs.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
target-ppc: Fix add and subf carry generation in narrow mode
The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9aare only valid if the current word size == target_long size. This failedto take ppc64 in 32-bit (narrow) mode into account....
target-ppc: Use NARROW_MODE macro for branches
Removing conditional compilation in the process.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for tlbie
mmu-hash*: Correctly mask RPN from hash PTE
BEHAVIOUR CHANGE
At present we take the whole of word 1 of the hash PTE as the real pagenumber used to calculate the translated address. This is incorrect,because it leaves the flags from the low bits of PTE word 1 in place in the...
mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
Currently the hash mmu versionsof get_phys_page_debug() use the sameppc64_hash64_translate() function to do the translation logic as the normalmm fault handler code....
mmu-hash*: Merge translate and fault handling functions
ppc_hash{32,64}_handle_mmu_fault() is now the only caller ofppc_hash{32,64{_translate(), so this patch combines them together. Thismeans that instead of one returning a variety of non-obvious error codes...
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional pageprotection mechanism. Each virtual page has a "class" (0-31) recorded inthe PTE. The AMR register contains bits which can prohibit reads and/or...
target-ppc: Split user only code out of mmu_helper.c
mmu_helper.c is, for obvious reasons, almost entirely concerned withsoftmmu builds of qemu. However, it does contain one stub function whichis used when CONFIG_USER_ONLY=y - the user only versoin of...
target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
For softmmu builds the interface from the generic code to the targetspecific MMU implementation is through the tlb_fill() function. For ppcthis is currently in mem_helper.c, whereas it would make more sense in...
target-ppc: Use QOM method dispatch for MMU fault handling
After previous cleanups, the many scattered checks of env->mmu_model inthe ppc MMU implementation have, at least for "classic" hash MMUs beenreduced (almost) to a single switch at the top ofcpu_ppc_handle_mmu_fault()....
mmu-hash*: Don't update PTE flags when permission is denied
Currently if ppc_hash{32,64}_translate() finds a PTE matching the givenvirtual address, it will always update the PTE's R & C (Referenced andChanged) bits. This happens even if the PTE's permissions mean we are...
mmu-hash32: Remove nx from context structure
Previous cleanups have meant the nx field of the mmu_ctx_hash32 structureis now only used within ppc_hash32_translate(), and so it can be replacedby a local variable.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
mmu-hash*: Clean up permission checking
Currently checking of PTE permission bits is split messily amongstppc_hash{32,64}_pp_check(), ppc_hash{32,64}_check_prot() and their callers.This patch cleans this up to have the new functionppc_hash{32,64}_pte_prot() compute the page permissions from the SLBE (for...
mmu-hash64: Factor SLB N bit into permissions bits
Currently, for 64-bit hash mmu, the execute protection bit placed into theqemu tlb is based only on the N (No execute) bit from the PTE. However,No Execute can also be set at the segment level. We do check this on...
mmu-hash*: Clean up PTE flags update
Currently the ppc_hash{32,64}_pte_update_flags() helper functions update aPTE's referenced and changed bits as necessary to reflect the access. Itis somewhat long winded, though. This patch open codes them in their...
mmu-hash*: Clean up real address calculation
More recent 64-bit hash MMUs support multiple page sizes, and PTEs forlarge pages only include the offset of the whole large page. But the qemutlb only handles pages of the base size (4k) so we need to break up the...
mmu-hash*: Fold pte_check*() logic into caller
With previous cleanups made, the 32-bit and 64-bit pte_check*() functionsare pretty trivial and only have one call site. This patch thereforeclarifies the overall code flow by folding those functions into their...
mmu-hash32: Remove odd pointer usage from BAT code
In the code for handling BATs, the hash32_bat_size_prot() andhash32_bat_601_size_prot() functions are passed the BAT contents byreference (pointer) for no clear reason, since they only need the valueswithin....
mmu-hash32: Split BAT size logic from permissions logic
hash32_bat_size_prot() and its 601 variant, as the name suggests, returnsboth a BAT's size - needed to search for a matching BAT - and itspermissions, only relevant once a matching BAT has been located....
mmu-hash32: Clean up BAT matching logic
The code to search for a matching BAT for a virtual address is somewhatlongwinded and awkward. In particular, it relies on seperate size andvalidity information being returned from the hash32_bat_size() function...
mmu-hash32: Cleanup BAT lookup
This patch makes a general cleanup of the ppc_hash32_get_bat() function,renaming it to ppc_hash32_bat_lookup(). In particular, the new functiononly looks for a matching BAT, with the permissions check from the oldfunction moved to the caller....
mmu-hash32: Don't look up page tables on BAT permission error
Currently, on any failure translating an address with BATs, we proceed tonormal segment and page table translation. That's incorrect if theBAT error was due to permissions, rather than not finding a matching BAT....
mmu-hash*: Don't keep looking for PTEs after we find a match
The ppc hash mmu hashes each virtual address to a primary and secondarypossible hash bucket (aka PTE group or PTEG) each with 8 PTEs. Then weneed a linear search through the PTEs to find the correct one for the...
mmu-hash*: Separate PTEG searching from permissions checking
find_pte{32,64{() do several things. First they search through a PTEGooking for a PTE matching our virtual address. Then they do permissionschecking and other processing on that PTE.
This patch separates the search by VA out from the rest. The search is...
mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes
find_pte{32,64}() are not particularly well named. They only "find" a PTEwithin a given PTE group, and they also do permissions checking and otherthings.
This patch makes it somewhat close to matching the name, by folding the...
mmu-hash*: Remove permission checking from find_pte{32, 64}()
find_pte{32,64}() are poorly named, since they both find a PTE and dopermissions checking of it. This patch makes them only locate a matchingPTE, moving the permission checking and other logic to the caller. We...
mmu-hash64: Clean up ppc_hash64_htab_lookup()
This patch makes a general cleanup of the address mangling logic inppc_hash64_htab_lookup(). In particular it now avoids repeatedly switchingon the segment size. The lack of SLB and multiple segment sizes on 32-bit...
mmu-hash*: Reduce use of access_type
In ppc env->access_type is updated by e.g. integer load/stores withACCESS_INT floating point load/stores with ACCESS_FLOAT and so forth. Inhash mmu fault paths it can also b set to ACCESS_CODE for instructionfetch accesses....
mmu-hash64: Remove nx from mmu_ctx_hash64
The nx field in mmu_ctx_hash64 is used in two different functions. But itsused for slightly different things in each place, and the value is neverpropagated between them. In other words, it might as well be two local...
mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64}
The eaddr field of mmu_ctx_hash{32,64} is effectively just used to pass theeffective address from get_segment{32,64}() to find_pte{32,64}(). Justpass it as a normal parameter instead.
mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}()
After previous work, ppc_hash{32,64}_get_physical_address() are almosttrivial wrappers around get_segment{32,64}() which does nearly all the work oftranslating an address according to the hash mmu model. Therefore combine the...
mmu-hash32: Split out handling of direct store segments
At present a large chunk of ppc_hash32_translate() is taken up with anugly if selecting between direct store segments (hardly ever used) andnormal paged segments. This patch clarifies the flow of code by...
mmu-hash32: Split direct store segment handling into a helper
This further separates the unusual case handling of direct store segmentsfrom the main translation path by moving its logic into a helper function,with some tiny cleanups along the way.
mmu-hash*: Cleanup segment-level NX check
On the ppc hash mmus, no-execute can be set at the segment level (on morerecent 64-bit hash mmus it can also be set at the page level). This patchseparates out this check to make it clearer what is going on, and avoiding...
target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug()
cpu_get_phys_page_debug() is a trivial wrapper aroundget_physical_address(). But even the signature ofget_physical_address() has some things we'd like to clean up on aper-mmu basis, so this patch moves the test on mmu model out to...
target-ppc: Disentangle hash mmu helper functions
The newly separated paths for hash mmus rely on several helper functionswhich are still shared with 32-bit hash mmus: pp_check(), check_prot() andpte_update_flags(). While these don't have ugly ifdefs on the mmu type,...
target-ppc: Don't share get_pteg_offset() between 32 and 64-bit
The get_pteg_offset() helper function is currently shared between 32-bitand 64-bit hash mmus, taking a parameter for the hash pte size. In the64-bit paths, it's only called in one place, and it's a trivial...
target-ppc: Disentangle BAT code for 32-bit hash MMUs
The functions for looking up BATs (Block Address Translation - essentiallya level 0 TLB) are shared between the classic 32-bit hash MMUs and the6xx style software loaded TLB implementations.
This patch splits out a copy for the 32-bit hash MMUs, to facilitate...
target-ppc: mmu_ctx_t should not be a global type
mmu_ctx_t is currently defined in cpu.h. However it is used for temporaryinformation relating to mmu translation, and is only used in mmu_helper.cand (now) mmu-hash{32,64}.c. Furthermore it contains information which...
mmu-hash*: Add header file for definitions
Currently cpu.h contains a number of definitions relating to the 64-bithash MMU. Some are used in the MMU emulation code, but some are only usedin the spapr MMU management hcall implementations.
This patch moves these definitions (except for a few that are needed...
mmu-hash*: Add hash pte load/store helpers
On real hardware the ppc hash page table is stored in memory; accordinglyour mmu emulation code can read a hash page table in guest memory. But,when paravirtualized under PAPR, the real hash page table is in host...
target-ppc: Disentangle pte_check()
Currently support for both 32-bit and 64-bit hash MMUs share animplementation of pte_check. But there are enough differences that thismeans the shared function has several very ugly conditionals on "is_64b".
This patch cleans things up by separating out the 64-bit version...
target-ppc: Disentangle find_pte()
32-bit and 64-bit hash MMU implementations currently share a find_ptefunction. This results in a whole bunch of ugly conditionals in the sharedfunction, and not all that much actually shared code.
This patch separates out the 32-bit and 64-bit versions, putting then...
target-ppc: Disentangle get_segment()
The poorly named get_segment() function handles most of the addresstranslation logic for hash-based MMUs. It has many ugly conditionals onwhether the MMU is 32-bit or 64-bit.
This patch splits the function into 32 and 64-bit versions, using the...
target-ppc: Rework get_physical_address()
Currently get_physical_address() first checks to see if translation isenabled in the MSR, then in the translation on case switches on the mmutype. Except that for BookE MMUs, translation is always on, and so it...
target-ppc: Disentangle get_physical_address() paths
Depending on the MSR state, for 64-bit hash MMUs, get_physical_addresscan either call check_physical (which has further tests for mmu type)or get_segment64. Similarly for 32-bit hash MMUs we can either call...
target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault
cpu_ppc_handle_mmu_fault() calls get_physical_address() (whose behaviourdepends on MMU type) then, if that fails, issues an appropriate exception- which again has a number of dependencies on MMU type....
PPC/GDB: handle read and write of fpscr
Although the support of this register may be uncomplete, there are noreason to prevent the debugger from reading or writing it.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
target-ppc: Trivial cleanups in mmu_helper.c
This removes the never-used pte64_invalidate() function, and makesppcmas_tlb_check() static, since it's only used within that file.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Remove address check for logging
One LOG_MMU statement in mmu_helper.c has an odd check on the effectiveaddress being translated. I can see no reason for this; I suspect it wasa debugging hack from long ago. This patch removes it.
target-ppc: Move SLB handling into a mmu-hash64.c
As a first step to disentangling the handling for 64-bit hash MMUs fromthe rest, we move the code handling the Segment Lookaside Buffer (SLB)(which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file....
target-ppc: Remove CONFIG_PSERIES dependency in kvm.c
target-ppc/kvm.c has an #ifdef on CONFIG_PSERIES, for the handling ofKVM exits due to a PAPR hypercall from the guest. However, since commite4c8b28cde12d01ada8fe869567dc5717a2dfcb7 "ppc: express FDT dependency of...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-ppc: Fix PPC_DUMP_SPR_ACCESS build
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0conversion, insert the missing cpu_env arguments.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Make host CPU a subclass of the host's CPU model
This avoids assigning individual class fields and contributorsforgetting to add field assignments in KVM-only code.
ppc_cpu_class_find_by_pvr() requires the CPU model classes to beregistered, so defer host CPU type registration to kvm_arch_init()....
target-ppc: List alias names alongside CPU models
Revert adding a separate -cpu ? output section for aliases and list themper CPU subclass.
Requested-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Report CPU aliases for QMP
The QMP query-cpu-definitions implementation iterated over CPU classesonly, which were getting less and less as aliases were extracted.
Keep them in QMP as valid -cpu arguments even if not guaranteed stable.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Move CPU aliases out of translate_init.c
Move array of CPU aliases to cpu-models.c, alongside model definitions.This requires to zero-terminate the aliases array since ARRAY_SIZE() canno longer be used in translate_init.c then.
Suggested-by: Alexander Graf <agraf@suse.de>...
target-ppc: Turn descriptive CPU model comments into device descriptions
Fix microcontroller typo while at it.
target-ppc: Update Coding Style for CPU models
Drop the space in #if defined (TODO).
target-ppc: Split model definitions out of translate_init.c
Now that model definitions only reference their parent type, modeldefinitions are independent of the family definitions and can becompiled independently of TCG translation.
Keep all #if defined(TODO) code local to cpu-models.c....
target-ppc: Fix remaining microcontroller typos among models
controler -> controller
target-ppc: Change "POWER7" CPU alias
Let it resolve to v2.3 rather than v2.0.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add mechanism for synchronizing SPRs with KVM
Currently when runing under KVM on ppc, we synchronize a certain number ofvital SPRs to KVM through the SET_SREGS call. This leaves out quite a lotof important SPRs which are maintained in KVM. It would be helpful to...
target-ppc: Synchronize FPU state with KVM
Currently qemu does not get and put the state of the floating point andvector registers to KVM. This is obviously a problem for savevm, as wellas possibly being problematic for debugging of FP-using guests.
This patch fixes this by using new extensions to the ONE_REG interface to...
target-ppc: Convert CPU definitions
Turn the array of model definitions into a set of self-registering QOMtypes with their own class_init. Unique identifiers are obtained fromthe combination of PVR, SVR and family identifiers; this requires allalias #defines to be removed from the list. Possibly there are some more...
target-ppc: Introduce abstract CPU family types
Instead of assigning *_<family> constants, set .parent to a family type.
Introduce a POWERPC_FAMILY() macro to keep type registration close toits implementation. This macro will need tweaking later.
target-ppc: Set instruction flags on CPU family classes
target-ppc: Register all types for TARGET_PPCEMB
Don't attempt to suppress registration of CPU types, since the criteriais actually a property of the class and should thus become a field.Since we can't check a field set in a class_init function beforeregistering the type that leads to execution of that function, guard the...
target-ppc: Set remaining fields on CPU family classes
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself.
target-ppc: Turn descriptive CPU family comments into device descriptions
This gets rid of some more overly long comments that have lost most oftheir purpose now that in most cases there's only two functions left perCPU family.
The class field is inherited by the actual CPU models, so override it....
target-ppc: Extract 970 aliases
target-ppc: Extract POWER7 alias
target-ppc: Get model name from type name
We are about to drop the redundant name field along with ppc_def_t.
target-ppc: Extract MPC82xx_HiP{3, 4} aliases
target-ppc: Extract MPC52xx alias
target-ppc: Extract MPC5200/MPC5200B aliases
target-ppc: Extract MPC8240 alias
target-ppc: Extract 405GPe alias
target-ppc: Extract 604e alias
target-ppc: Extract MPC85xx aliases
target-ppc: Extract e500v1/e500v2 aliases
target-ppc: Extract MPC83xx aliases
target-ppc: Extract e300 alias
target-ppc: Extract e200 alias
target-ppc: Extract MPC82xx alias
target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
This depends on the fix for "G2leGP3" PVR.
target-ppc: Extract MPC82xx aliases to *_HiP4
target-ppc: Extract 750 aliases
target-ppc: Extract 740/750 aliases
target-ppc: Extract 603e alias
target-ppc: Extract 603r alias
target-ppc: Extract 601/601v aliases