root / hw / arm / vexpress.c @ 5a4348d1
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1 | 2055283b | Peter Maydell | /*
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2 | 2055283b | Peter Maydell | * ARM Versatile Express emulation.
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3 | 2055283b | Peter Maydell | *
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4 | 2055283b | Peter Maydell | * Copyright (c) 2010 - 2011 B Labs Ltd.
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5 | 2055283b | Peter Maydell | * Copyright (c) 2011 Linaro Limited
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6 | 2055283b | Peter Maydell | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
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7 | 2055283b | Peter Maydell | *
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8 | 2055283b | Peter Maydell | * This program is free software; you can redistribute it and/or modify
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9 | 2055283b | Peter Maydell | * it under the terms of the GNU General Public License version 2 as
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10 | 2055283b | Peter Maydell | * published by the Free Software Foundation.
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11 | 2055283b | Peter Maydell | *
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12 | 2055283b | Peter Maydell | * This program is distributed in the hope that it will be useful,
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13 | 2055283b | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2055283b | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 2055283b | Peter Maydell | * GNU General Public License for more details.
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16 | 2055283b | Peter Maydell | *
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17 | 2055283b | Peter Maydell | * You should have received a copy of the GNU General Public License along
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18 | 2055283b | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 6b620ca3 | Paolo Bonzini | *
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20 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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21 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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22 | 2055283b | Peter Maydell | */
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23 | 2055283b | Peter Maydell | |
24 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
25 | bd2be150 | Peter Maydell | #include "hw/arm/arm.h" |
26 | 0d09e41a | Paolo Bonzini | #include "hw/arm/primecell.h" |
27 | bd2be150 | Peter Maydell | #include "hw/devices.h" |
28 | 1422e32d | Paolo Bonzini | #include "net/net.h" |
29 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/boards.h" |
31 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
32 | 9c17d615 | Paolo Bonzini | #include "sysemu/blockdev.h" |
33 | 0d09e41a | Paolo Bonzini | #include "hw/block/flash.h" |
34 | c8a07b35 | Peter Maydell | #include "sysemu/device_tree.h" |
35 | c8a07b35 | Peter Maydell | #include <libfdt.h> |
36 | 2055283b | Peter Maydell | |
37 | 2055283b | Peter Maydell | #define VEXPRESS_BOARD_ID 0x8e0 |
38 | 3dc3e7dd | Francesco Lavra | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) |
39 | 3dc3e7dd | Francesco Lavra | #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) |
40 | 2055283b | Peter Maydell | |
41 | c8a07b35 | Peter Maydell | /* Number of virtio transports to create (0..8; limited by
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42 | c8a07b35 | Peter Maydell | * number of available IRQ lines).
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43 | c8a07b35 | Peter Maydell | */
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44 | c8a07b35 | Peter Maydell | #define NUM_VIRTIO_TRANSPORTS 4 |
45 | c8a07b35 | Peter Maydell | |
46 | 2558e0a6 | Peter Maydell | /* Address maps for peripherals:
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47 | 2558e0a6 | Peter Maydell | * the Versatile Express motherboard has two possible maps,
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48 | 2558e0a6 | Peter Maydell | * the "legacy" one (used for A9) and the "Cortex-A Series"
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49 | 2558e0a6 | Peter Maydell | * map (used for newer cores).
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50 | 2558e0a6 | Peter Maydell | * Individual daughterboards can also have different maps for
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51 | 2558e0a6 | Peter Maydell | * their peripherals.
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52 | 2558e0a6 | Peter Maydell | */
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53 | 2558e0a6 | Peter Maydell | |
54 | 2558e0a6 | Peter Maydell | enum {
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55 | 2558e0a6 | Peter Maydell | VE_SYSREGS, |
56 | 2558e0a6 | Peter Maydell | VE_SP810, |
57 | 2558e0a6 | Peter Maydell | VE_SERIALPCI, |
58 | 2558e0a6 | Peter Maydell | VE_PL041, |
59 | 2558e0a6 | Peter Maydell | VE_MMCI, |
60 | 2558e0a6 | Peter Maydell | VE_KMI0, |
61 | 2558e0a6 | Peter Maydell | VE_KMI1, |
62 | 2558e0a6 | Peter Maydell | VE_UART0, |
63 | 2558e0a6 | Peter Maydell | VE_UART1, |
64 | 2558e0a6 | Peter Maydell | VE_UART2, |
65 | 2558e0a6 | Peter Maydell | VE_UART3, |
66 | 2558e0a6 | Peter Maydell | VE_WDT, |
67 | 2558e0a6 | Peter Maydell | VE_TIMER01, |
68 | 2558e0a6 | Peter Maydell | VE_TIMER23, |
69 | 2558e0a6 | Peter Maydell | VE_SERIALDVI, |
70 | 2558e0a6 | Peter Maydell | VE_RTC, |
71 | 2558e0a6 | Peter Maydell | VE_COMPACTFLASH, |
72 | 2558e0a6 | Peter Maydell | VE_CLCD, |
73 | 2558e0a6 | Peter Maydell | VE_NORFLASH0, |
74 | 2558e0a6 | Peter Maydell | VE_NORFLASH1, |
75 | 8941d6ce | Peter Maydell | VE_NORFLASHALIAS, |
76 | 2558e0a6 | Peter Maydell | VE_SRAM, |
77 | 2558e0a6 | Peter Maydell | VE_VIDEORAM, |
78 | 2558e0a6 | Peter Maydell | VE_ETHERNET, |
79 | 2558e0a6 | Peter Maydell | VE_USB, |
80 | 2558e0a6 | Peter Maydell | VE_DAPROM, |
81 | c8a07b35 | Peter Maydell | VE_VIRTIO, |
82 | 2558e0a6 | Peter Maydell | }; |
83 | 2558e0a6 | Peter Maydell | |
84 | a8170e5e | Avi Kivity | static hwaddr motherboard_legacy_map[] = {
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85 | 2558e0a6 | Peter Maydell | /* CS7: 0x10000000 .. 0x10020000 */
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86 | 2558e0a6 | Peter Maydell | [VE_SYSREGS] = 0x10000000,
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87 | 2558e0a6 | Peter Maydell | [VE_SP810] = 0x10001000,
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88 | 2558e0a6 | Peter Maydell | [VE_SERIALPCI] = 0x10002000,
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89 | 2558e0a6 | Peter Maydell | [VE_PL041] = 0x10004000,
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90 | 2558e0a6 | Peter Maydell | [VE_MMCI] = 0x10005000,
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91 | 2558e0a6 | Peter Maydell | [VE_KMI0] = 0x10006000,
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92 | 2558e0a6 | Peter Maydell | [VE_KMI1] = 0x10007000,
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93 | 2558e0a6 | Peter Maydell | [VE_UART0] = 0x10009000,
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94 | 2558e0a6 | Peter Maydell | [VE_UART1] = 0x1000a000,
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95 | 2558e0a6 | Peter Maydell | [VE_UART2] = 0x1000b000,
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96 | 2558e0a6 | Peter Maydell | [VE_UART3] = 0x1000c000,
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97 | 2558e0a6 | Peter Maydell | [VE_WDT] = 0x1000f000,
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98 | 2558e0a6 | Peter Maydell | [VE_TIMER01] = 0x10011000,
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99 | 2558e0a6 | Peter Maydell | [VE_TIMER23] = 0x10012000,
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100 | c8a07b35 | Peter Maydell | [VE_VIRTIO] = 0x10013000,
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101 | 2558e0a6 | Peter Maydell | [VE_SERIALDVI] = 0x10016000,
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102 | 2558e0a6 | Peter Maydell | [VE_RTC] = 0x10017000,
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103 | 2558e0a6 | Peter Maydell | [VE_COMPACTFLASH] = 0x1001a000,
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104 | 2558e0a6 | Peter Maydell | [VE_CLCD] = 0x1001f000,
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105 | 2558e0a6 | Peter Maydell | /* CS0: 0x40000000 .. 0x44000000 */
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106 | 2558e0a6 | Peter Maydell | [VE_NORFLASH0] = 0x40000000,
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107 | 2558e0a6 | Peter Maydell | /* CS1: 0x44000000 .. 0x48000000 */
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108 | 2558e0a6 | Peter Maydell | [VE_NORFLASH1] = 0x44000000,
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109 | 2558e0a6 | Peter Maydell | /* CS2: 0x48000000 .. 0x4a000000 */
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110 | 2558e0a6 | Peter Maydell | [VE_SRAM] = 0x48000000,
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111 | 2558e0a6 | Peter Maydell | /* CS3: 0x4c000000 .. 0x50000000 */
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112 | 2558e0a6 | Peter Maydell | [VE_VIDEORAM] = 0x4c000000,
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113 | 2558e0a6 | Peter Maydell | [VE_ETHERNET] = 0x4e000000,
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114 | 2558e0a6 | Peter Maydell | [VE_USB] = 0x4f000000,
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115 | 8941d6ce | Peter Maydell | [VE_NORFLASHALIAS] = -1, /* not present */ |
116 | 2055283b | Peter Maydell | }; |
117 | 2055283b | Peter Maydell | |
118 | a8170e5e | Avi Kivity | static hwaddr motherboard_aseries_map[] = {
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119 | 8941d6ce | Peter Maydell | [VE_NORFLASHALIAS] = 0,
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120 | 661bafb3 | Francesco Lavra | /* CS0: 0x08000000 .. 0x0c000000 */
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121 | 661bafb3 | Francesco Lavra | [VE_NORFLASH0] = 0x08000000,
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122 | 961f195e | Peter Maydell | /* CS4: 0x0c000000 .. 0x10000000 */
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123 | 961f195e | Peter Maydell | [VE_NORFLASH1] = 0x0c000000,
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124 | 961f195e | Peter Maydell | /* CS5: 0x10000000 .. 0x14000000 */
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125 | 961f195e | Peter Maydell | /* CS1: 0x14000000 .. 0x18000000 */
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126 | 961f195e | Peter Maydell | [VE_SRAM] = 0x14000000,
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127 | 961f195e | Peter Maydell | /* CS2: 0x18000000 .. 0x1c000000 */
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128 | 961f195e | Peter Maydell | [VE_VIDEORAM] = 0x18000000,
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129 | 961f195e | Peter Maydell | [VE_ETHERNET] = 0x1a000000,
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130 | 961f195e | Peter Maydell | [VE_USB] = 0x1b000000,
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131 | 961f195e | Peter Maydell | /* CS3: 0x1c000000 .. 0x20000000 */
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132 | 961f195e | Peter Maydell | [VE_DAPROM] = 0x1c000000,
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133 | 961f195e | Peter Maydell | [VE_SYSREGS] = 0x1c010000,
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134 | 961f195e | Peter Maydell | [VE_SP810] = 0x1c020000,
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135 | 961f195e | Peter Maydell | [VE_SERIALPCI] = 0x1c030000,
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136 | 961f195e | Peter Maydell | [VE_PL041] = 0x1c040000,
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137 | 961f195e | Peter Maydell | [VE_MMCI] = 0x1c050000,
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138 | 961f195e | Peter Maydell | [VE_KMI0] = 0x1c060000,
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139 | 961f195e | Peter Maydell | [VE_KMI1] = 0x1c070000,
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140 | 961f195e | Peter Maydell | [VE_UART0] = 0x1c090000,
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141 | 961f195e | Peter Maydell | [VE_UART1] = 0x1c0a0000,
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142 | 961f195e | Peter Maydell | [VE_UART2] = 0x1c0b0000,
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143 | 961f195e | Peter Maydell | [VE_UART3] = 0x1c0c0000,
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144 | 961f195e | Peter Maydell | [VE_WDT] = 0x1c0f0000,
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145 | 961f195e | Peter Maydell | [VE_TIMER01] = 0x1c110000,
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146 | 961f195e | Peter Maydell | [VE_TIMER23] = 0x1c120000,
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147 | c8a07b35 | Peter Maydell | [VE_VIRTIO] = 0x1c130000,
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148 | 961f195e | Peter Maydell | [VE_SERIALDVI] = 0x1c160000,
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149 | 961f195e | Peter Maydell | [VE_RTC] = 0x1c170000,
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150 | 961f195e | Peter Maydell | [VE_COMPACTFLASH] = 0x1c1a0000,
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151 | 961f195e | Peter Maydell | [VE_CLCD] = 0x1c1f0000,
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152 | 961f195e | Peter Maydell | }; |
153 | 961f195e | Peter Maydell | |
154 | 4c3b29b8 | Peter Maydell | /* Structure defining the peculiarities of a specific daughterboard */
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155 | 4c3b29b8 | Peter Maydell | |
156 | 4c3b29b8 | Peter Maydell | typedef struct VEDBoardInfo VEDBoardInfo; |
157 | 4c3b29b8 | Peter Maydell | |
158 | 4c3b29b8 | Peter Maydell | typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, |
159 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
160 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
161 | cdef10bb | Peter Maydell | qemu_irq *pic); |
162 | 4c3b29b8 | Peter Maydell | |
163 | 4c3b29b8 | Peter Maydell | struct VEDBoardInfo {
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164 | cef04a26 | Peter Maydell | struct arm_boot_info bootinfo;
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165 | a8170e5e | Avi Kivity | const hwaddr *motherboard_map;
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166 | a8170e5e | Avi Kivity | hwaddr loader_start; |
167 | a8170e5e | Avi Kivity | const hwaddr gic_cpu_if_addr;
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168 | cdef10bb | Peter Maydell | uint32_t proc_id; |
169 | 31410948 | Peter Maydell | uint32_t num_voltage_sensors; |
170 | 31410948 | Peter Maydell | const uint32_t *voltages;
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171 | 9c7d4893 | Peter Maydell | uint32_t num_clocks; |
172 | 9c7d4893 | Peter Maydell | const uint32_t *clocks;
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173 | 4c3b29b8 | Peter Maydell | DBoardInitFn *init; |
174 | 4c3b29b8 | Peter Maydell | }; |
175 | 4c3b29b8 | Peter Maydell | |
176 | 4c3b29b8 | Peter Maydell | static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, |
177 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
178 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
179 | cdef10bb | Peter Maydell | qemu_irq *pic) |
180 | 2055283b | Peter Maydell | { |
181 | e6d17b05 | Avi Kivity | MemoryRegion *sysmem = get_system_memory(); |
182 | e6d17b05 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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183 | e6d17b05 | Avi Kivity | MemoryRegion *lowram = g_new(MemoryRegion, 1);
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184 | 4c3b29b8 | Peter Maydell | DeviceState *dev; |
185 | 2055283b | Peter Maydell | SysBusDevice *busdev; |
186 | 2055283b | Peter Maydell | int n;
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187 | 2055283b | Peter Maydell | qemu_irq cpu_irq[4];
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188 | 4c3b29b8 | Peter Maydell | ram_addr_t low_ram_size; |
189 | 2055283b | Peter Maydell | |
190 | 2055283b | Peter Maydell | if (!cpu_model) {
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191 | 2055283b | Peter Maydell | cpu_model = "cortex-a9";
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192 | 2055283b | Peter Maydell | } |
193 | 2055283b | Peter Maydell | |
194 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
195 | 64c9e297 | Andreas Färber | ARMCPU *cpu = cpu_arm_init(cpu_model); |
196 | 64c9e297 | Andreas Färber | if (!cpu) {
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197 | 2055283b | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
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198 | 2055283b | Peter Maydell | exit(1);
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199 | 2055283b | Peter Maydell | } |
200 | fe9120a5 | Peter Maydell | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); |
201 | 2055283b | Peter Maydell | } |
202 | 2055283b | Peter Maydell | |
203 | 2055283b | Peter Maydell | if (ram_size > 0x40000000) { |
204 | 2055283b | Peter Maydell | /* 1GB is the maximum the address space permits */
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205 | 4c3b29b8 | Peter Maydell | fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
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206 | 2055283b | Peter Maydell | exit(1);
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207 | 2055283b | Peter Maydell | } |
208 | 2055283b | Peter Maydell | |
209 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); |
210 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
211 | 2055283b | Peter Maydell | low_ram_size = ram_size; |
212 | 2055283b | Peter Maydell | if (low_ram_size > 0x4000000) { |
213 | 2055283b | Peter Maydell | low_ram_size = 0x4000000;
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214 | 2055283b | Peter Maydell | } |
215 | 2055283b | Peter Maydell | /* RAM is from 0x60000000 upwards. The bottom 64MB of the
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216 | 2055283b | Peter Maydell | * address space should in theory be remappable to various
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217 | 2055283b | Peter Maydell | * things including ROM or RAM; we always map the RAM there.
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218 | 2055283b | Peter Maydell | */
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219 | 2c9b15ca | Paolo Bonzini | memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); |
220 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x0, lowram);
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221 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x60000000, ram);
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222 | 2055283b | Peter Maydell | |
223 | 2055283b | Peter Maydell | /* 0x1e000000 A9MPCore (SCU) private memory region */
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224 | 2055283b | Peter Maydell | dev = qdev_create(NULL, "a9mpcore_priv"); |
225 | 2055283b | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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226 | 2055283b | Peter Maydell | qdev_init_nofail(dev); |
227 | 1356b98d | Andreas Färber | busdev = SYS_BUS_DEVICE(dev); |
228 | 96eacf64 | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x1e000000); |
229 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
230 | 2055283b | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
231 | 2055283b | Peter Maydell | } |
232 | 2055283b | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
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233 | 2055283b | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
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234 | 2055283b | Peter Maydell | * peripherals. Note that some documentation numbers
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235 | 2055283b | Peter Maydell | * external interrupts starting from 32 (because the
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236 | 2055283b | Peter Maydell | * A9MP has internal interrupts 0..31).
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237 | 2055283b | Peter Maydell | */
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238 | 2055283b | Peter Maydell | for (n = 0; n < 64; n++) { |
239 | 2055283b | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
240 | 2055283b | Peter Maydell | } |
241 | 2055283b | Peter Maydell | |
242 | 4c3b29b8 | Peter Maydell | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
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243 | 4c3b29b8 | Peter Maydell | |
244 | 4c3b29b8 | Peter Maydell | /* 0x10020000 PL111 CLCD (daughterboard) */
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245 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("pl111", 0x10020000, pic[44]); |
246 | 4c3b29b8 | Peter Maydell | |
247 | 4c3b29b8 | Peter Maydell | /* 0x10060000 AXI RAM */
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248 | 4c3b29b8 | Peter Maydell | /* 0x100e0000 PL341 Dynamic Memory Controller */
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249 | 4c3b29b8 | Peter Maydell | /* 0x100e1000 PL354 Static Memory Controller */
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250 | 4c3b29b8 | Peter Maydell | /* 0x100e2000 System Configuration Controller */
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251 | 4c3b29b8 | Peter Maydell | |
252 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("sp804", 0x100e4000, pic[48]); |
253 | 4c3b29b8 | Peter Maydell | /* 0x100e5000 SP805 Watchdog module */
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254 | 4c3b29b8 | Peter Maydell | /* 0x100e6000 BP147 TrustZone Protection Controller */
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255 | 4c3b29b8 | Peter Maydell | /* 0x100e9000 PL301 'Fast' AXI matrix */
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256 | 4c3b29b8 | Peter Maydell | /* 0x100ea000 PL301 'Slow' AXI matrix */
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257 | 4c3b29b8 | Peter Maydell | /* 0x100ec000 TrustZone Address Space Controller */
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258 | 4c3b29b8 | Peter Maydell | /* 0x10200000 CoreSight debug APB */
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259 | 4c3b29b8 | Peter Maydell | /* 0x1e00a000 PL310 L2 Cache Controller */
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260 | 4c3b29b8 | Peter Maydell | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); |
261 | 4c3b29b8 | Peter Maydell | } |
262 | 4c3b29b8 | Peter Maydell | |
263 | 31410948 | Peter Maydell | /* Voltage values for SYS_CFG_VOLT daughterboard registers;
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264 | 31410948 | Peter Maydell | * values are in microvolts.
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265 | 31410948 | Peter Maydell | */
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266 | 31410948 | Peter Maydell | static const uint32_t a9_voltages[] = { |
267 | 31410948 | Peter Maydell | 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ |
268 | 31410948 | Peter Maydell | 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ |
269 | 31410948 | Peter Maydell | 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ |
270 | 31410948 | Peter Maydell | 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ |
271 | 31410948 | Peter Maydell | 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ |
272 | 31410948 | Peter Maydell | 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ |
273 | 31410948 | Peter Maydell | }; |
274 | 31410948 | Peter Maydell | |
275 | 9c7d4893 | Peter Maydell | /* Reset values for daughterboard oscillators (in Hz) */
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276 | 9c7d4893 | Peter Maydell | static const uint32_t a9_clocks[] = { |
277 | 9c7d4893 | Peter Maydell | 45000000, /* AMBA AXI ACLK: 45MHz */ |
278 | 9c7d4893 | Peter Maydell | 23750000, /* daughterboard CLCD clock: 23.75MHz */ |
279 | 9c7d4893 | Peter Maydell | 66670000, /* Test chip reference clock: 66.67MHz */ |
280 | 9c7d4893 | Peter Maydell | }; |
281 | 9c7d4893 | Peter Maydell | |
282 | cef04a26 | Peter Maydell | static VEDBoardInfo a9_daughterboard = {
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283 | 4c3b29b8 | Peter Maydell | .motherboard_map = motherboard_legacy_map, |
284 | 4c3b29b8 | Peter Maydell | .loader_start = 0x60000000,
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285 | 96eacf64 | Peter Maydell | .gic_cpu_if_addr = 0x1e000100,
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286 | cdef10bb | Peter Maydell | .proc_id = 0x0c000191,
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287 | 31410948 | Peter Maydell | .num_voltage_sensors = ARRAY_SIZE(a9_voltages), |
288 | 31410948 | Peter Maydell | .voltages = a9_voltages, |
289 | 9c7d4893 | Peter Maydell | .num_clocks = ARRAY_SIZE(a9_clocks), |
290 | 9c7d4893 | Peter Maydell | .clocks = a9_clocks, |
291 | 4c3b29b8 | Peter Maydell | .init = a9_daughterboard_init, |
292 | 4c3b29b8 | Peter Maydell | }; |
293 | 4c3b29b8 | Peter Maydell | |
294 | 961f195e | Peter Maydell | static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, |
295 | 961f195e | Peter Maydell | ram_addr_t ram_size, |
296 | 961f195e | Peter Maydell | const char *cpu_model, |
297 | cdef10bb | Peter Maydell | qemu_irq *pic) |
298 | 961f195e | Peter Maydell | { |
299 | 961f195e | Peter Maydell | int n;
|
300 | 961f195e | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
301 | 961f195e | Peter Maydell | MemoryRegion *ram = g_new(MemoryRegion, 1);
|
302 | 961f195e | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
|
303 | 961f195e | Peter Maydell | qemu_irq cpu_irq[4];
|
304 | 961f195e | Peter Maydell | DeviceState *dev; |
305 | 961f195e | Peter Maydell | SysBusDevice *busdev; |
306 | 961f195e | Peter Maydell | |
307 | 961f195e | Peter Maydell | if (!cpu_model) {
|
308 | 961f195e | Peter Maydell | cpu_model = "cortex-a15";
|
309 | 961f195e | Peter Maydell | } |
310 | 961f195e | Peter Maydell | |
311 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
312 | 64c9e297 | Andreas Färber | ARMCPU *cpu; |
313 | 64c9e297 | Andreas Färber | |
314 | 64c9e297 | Andreas Färber | cpu = cpu_arm_init(cpu_model); |
315 | 64c9e297 | Andreas Färber | if (!cpu) {
|
316 | 961f195e | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
|
317 | 961f195e | Peter Maydell | exit(1);
|
318 | 961f195e | Peter Maydell | } |
319 | fe9120a5 | Peter Maydell | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); |
320 | 961f195e | Peter Maydell | } |
321 | 961f195e | Peter Maydell | |
322 | 25d71699 | Peter Maydell | { |
323 | 25d71699 | Peter Maydell | /* We have to use a separate 64 bit variable here to avoid the gcc
|
324 | 25d71699 | Peter Maydell | * "comparison is always false due to limited range of data type"
|
325 | 25d71699 | Peter Maydell | * warning if we are on a host where ram_addr_t is 32 bits.
|
326 | 25d71699 | Peter Maydell | */
|
327 | 25d71699 | Peter Maydell | uint64_t rsz = ram_size; |
328 | 25d71699 | Peter Maydell | if (rsz > (30ULL * 1024 * 1024 * 1024)) { |
329 | 25d71699 | Peter Maydell | fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
|
330 | 25d71699 | Peter Maydell | exit(1);
|
331 | 25d71699 | Peter Maydell | } |
332 | 961f195e | Peter Maydell | } |
333 | 961f195e | Peter Maydell | |
334 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); |
335 | 961f195e | Peter Maydell | vmstate_register_ram_global(ram); |
336 | 961f195e | Peter Maydell | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
|
337 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x80000000, ram);
|
338 | 961f195e | Peter Maydell | |
339 | 961f195e | Peter Maydell | /* 0x2c000000 A15MPCore private memory region (GIC) */
|
340 | 961f195e | Peter Maydell | dev = qdev_create(NULL, "a15mpcore_priv"); |
341 | 961f195e | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
|
342 | 961f195e | Peter Maydell | qdev_init_nofail(dev); |
343 | 1356b98d | Andreas Färber | busdev = SYS_BUS_DEVICE(dev); |
344 | 961f195e | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x2c000000); |
345 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
346 | 961f195e | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
347 | 961f195e | Peter Maydell | } |
348 | 961f195e | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
|
349 | 961f195e | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
|
350 | 961f195e | Peter Maydell | * peripherals. Note that some documentation numbers
|
351 | 961f195e | Peter Maydell | * external interrupts starting from 32 (because there
|
352 | 961f195e | Peter Maydell | * are internal interrupts 0..31).
|
353 | 961f195e | Peter Maydell | */
|
354 | 961f195e | Peter Maydell | for (n = 0; n < 64; n++) { |
355 | 961f195e | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
356 | 961f195e | Peter Maydell | } |
357 | 961f195e | Peter Maydell | |
358 | 961f195e | Peter Maydell | /* A15 daughterboard peripherals: */
|
359 | 961f195e | Peter Maydell | |
360 | 961f195e | Peter Maydell | /* 0x20000000: CoreSight interfaces: not modelled */
|
361 | 961f195e | Peter Maydell | /* 0x2a000000: PL301 AXI interconnect: not modelled */
|
362 | 961f195e | Peter Maydell | /* 0x2a420000: SCC: not modelled */
|
363 | 961f195e | Peter Maydell | /* 0x2a430000: system counter: not modelled */
|
364 | 961f195e | Peter Maydell | /* 0x2b000000: HDLCD controller: not modelled */
|
365 | 961f195e | Peter Maydell | /* 0x2b060000: SP805 watchdog: not modelled */
|
366 | 961f195e | Peter Maydell | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
|
367 | 961f195e | Peter Maydell | /* 0x2e000000: system SRAM */
|
368 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000); |
369 | 961f195e | Peter Maydell | vmstate_register_ram_global(sram); |
370 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x2e000000, sram);
|
371 | 961f195e | Peter Maydell | |
372 | 961f195e | Peter Maydell | /* 0x7ffb0000: DMA330 DMA controller: not modelled */
|
373 | 961f195e | Peter Maydell | /* 0x7ffd0000: PL354 static memory controller: not modelled */
|
374 | 961f195e | Peter Maydell | } |
375 | 961f195e | Peter Maydell | |
376 | 31410948 | Peter Maydell | static const uint32_t a15_voltages[] = { |
377 | 31410948 | Peter Maydell | 900000, /* Vcore: 0.9V : CPU core voltage */ |
378 | 31410948 | Peter Maydell | }; |
379 | 31410948 | Peter Maydell | |
380 | 9c7d4893 | Peter Maydell | static const uint32_t a15_clocks[] = { |
381 | 9c7d4893 | Peter Maydell | 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ |
382 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK1: reserved */ |
383 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK2: reserved */ |
384 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK3: reserved */ |
385 | 9c7d4893 | Peter Maydell | 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ |
386 | 9c7d4893 | Peter Maydell | 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ |
387 | 9c7d4893 | Peter Maydell | 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ |
388 | 9c7d4893 | Peter Maydell | 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ |
389 | 9c7d4893 | Peter Maydell | 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ |
390 | 9c7d4893 | Peter Maydell | }; |
391 | 9c7d4893 | Peter Maydell | |
392 | cef04a26 | Peter Maydell | static VEDBoardInfo a15_daughterboard = {
|
393 | 961f195e | Peter Maydell | .motherboard_map = motherboard_aseries_map, |
394 | 961f195e | Peter Maydell | .loader_start = 0x80000000,
|
395 | 961f195e | Peter Maydell | .gic_cpu_if_addr = 0x2c002000,
|
396 | cdef10bb | Peter Maydell | .proc_id = 0x14000237,
|
397 | 31410948 | Peter Maydell | .num_voltage_sensors = ARRAY_SIZE(a15_voltages), |
398 | 31410948 | Peter Maydell | .voltages = a15_voltages, |
399 | 9c7d4893 | Peter Maydell | .num_clocks = ARRAY_SIZE(a15_clocks), |
400 | 9c7d4893 | Peter Maydell | .clocks = a15_clocks, |
401 | 961f195e | Peter Maydell | .init = a15_daughterboard_init, |
402 | 961f195e | Peter Maydell | }; |
403 | 961f195e | Peter Maydell | |
404 | c8a07b35 | Peter Maydell | static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, |
405 | c8a07b35 | Peter Maydell | hwaddr addr, hwaddr size, uint32_t intc, |
406 | c8a07b35 | Peter Maydell | int irq)
|
407 | c8a07b35 | Peter Maydell | { |
408 | c8a07b35 | Peter Maydell | /* Add a virtio_mmio node to the device tree blob:
|
409 | c8a07b35 | Peter Maydell | * virtio_mmio@ADDRESS {
|
410 | c8a07b35 | Peter Maydell | * compatible = "virtio,mmio";
|
411 | c8a07b35 | Peter Maydell | * reg = <ADDRESS, SIZE>;
|
412 | c8a07b35 | Peter Maydell | * interrupt-parent = <&intc>;
|
413 | c8a07b35 | Peter Maydell | * interrupts = <0, irq, 1>;
|
414 | c8a07b35 | Peter Maydell | * }
|
415 | c8a07b35 | Peter Maydell | * (Note that the format of the interrupts property is dependent on the
|
416 | c8a07b35 | Peter Maydell | * interrupt controller that interrupt-parent points to; these are for
|
417 | c8a07b35 | Peter Maydell | * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
|
418 | c8a07b35 | Peter Maydell | */
|
419 | c8a07b35 | Peter Maydell | int rc;
|
420 | c8a07b35 | Peter Maydell | char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); |
421 | c8a07b35 | Peter Maydell | |
422 | 5a4348d1 | Peter Crosthwaite | rc = qemu_fdt_add_subnode(fdt, nodename); |
423 | 5a4348d1 | Peter Crosthwaite | rc |= qemu_fdt_setprop_string(fdt, nodename, |
424 | 5a4348d1 | Peter Crosthwaite | "compatible", "virtio,mmio"); |
425 | 5a4348d1 | Peter Crosthwaite | rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
|
426 | 5a4348d1 | Peter Crosthwaite | acells, addr, scells, size); |
427 | 5a4348d1 | Peter Crosthwaite | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
|
428 | 5a4348d1 | Peter Crosthwaite | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); |
429 | c8a07b35 | Peter Maydell | g_free(nodename); |
430 | c8a07b35 | Peter Maydell | if (rc) {
|
431 | c8a07b35 | Peter Maydell | return -1; |
432 | c8a07b35 | Peter Maydell | } |
433 | c8a07b35 | Peter Maydell | return 0; |
434 | c8a07b35 | Peter Maydell | } |
435 | c8a07b35 | Peter Maydell | |
436 | c8a07b35 | Peter Maydell | static uint32_t find_int_controller(void *fdt) |
437 | c8a07b35 | Peter Maydell | { |
438 | c8a07b35 | Peter Maydell | /* Find the FDT node corresponding to the interrupt controller
|
439 | c8a07b35 | Peter Maydell | * for virtio-mmio devices. We do this by scanning the fdt for
|
440 | c8a07b35 | Peter Maydell | * a node with the right compatibility, since we know there is
|
441 | c8a07b35 | Peter Maydell | * only one GIC on a vexpress board.
|
442 | c8a07b35 | Peter Maydell | * We return the phandle of the node, or 0 if none was found.
|
443 | c8a07b35 | Peter Maydell | */
|
444 | c8a07b35 | Peter Maydell | const char *compat = "arm,cortex-a9-gic"; |
445 | c8a07b35 | Peter Maydell | int offset;
|
446 | c8a07b35 | Peter Maydell | |
447 | c8a07b35 | Peter Maydell | offset = fdt_node_offset_by_compatible(fdt, -1, compat);
|
448 | c8a07b35 | Peter Maydell | if (offset >= 0) { |
449 | c8a07b35 | Peter Maydell | return fdt_get_phandle(fdt, offset);
|
450 | c8a07b35 | Peter Maydell | } |
451 | c8a07b35 | Peter Maydell | return 0; |
452 | c8a07b35 | Peter Maydell | } |
453 | c8a07b35 | Peter Maydell | |
454 | c8a07b35 | Peter Maydell | static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) |
455 | c8a07b35 | Peter Maydell | { |
456 | c8a07b35 | Peter Maydell | uint32_t acells, scells, intc; |
457 | c8a07b35 | Peter Maydell | const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; |
458 | c8a07b35 | Peter Maydell | |
459 | 5a4348d1 | Peter Crosthwaite | acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); |
460 | 5a4348d1 | Peter Crosthwaite | scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); |
461 | c8a07b35 | Peter Maydell | intc = find_int_controller(fdt); |
462 | c8a07b35 | Peter Maydell | if (!intc) {
|
463 | c8a07b35 | Peter Maydell | /* Not fatal, we just won't provide virtio. This will
|
464 | c8a07b35 | Peter Maydell | * happen with older device tree blobs.
|
465 | c8a07b35 | Peter Maydell | */
|
466 | c8a07b35 | Peter Maydell | fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
|
467 | c8a07b35 | Peter Maydell | "dtb; will not include virtio-mmio devices in the dtb.\n");
|
468 | c8a07b35 | Peter Maydell | } else {
|
469 | c8a07b35 | Peter Maydell | int i;
|
470 | c8a07b35 | Peter Maydell | const hwaddr *map = daughterboard->motherboard_map;
|
471 | c8a07b35 | Peter Maydell | |
472 | c8a07b35 | Peter Maydell | /* We iterate backwards here because adding nodes
|
473 | c8a07b35 | Peter Maydell | * to the dtb puts them in last-first.
|
474 | c8a07b35 | Peter Maydell | */
|
475 | c8a07b35 | Peter Maydell | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
476 | c8a07b35 | Peter Maydell | add_virtio_mmio_node(fdt, acells, scells, |
477 | c8a07b35 | Peter Maydell | map[VE_VIRTIO] + 0x200 * i,
|
478 | c8a07b35 | Peter Maydell | 0x200, intc, 40 + i); |
479 | c8a07b35 | Peter Maydell | } |
480 | c8a07b35 | Peter Maydell | } |
481 | c8a07b35 | Peter Maydell | } |
482 | c8a07b35 | Peter Maydell | |
483 | b8433303 | Roy Franz | |
484 | b8433303 | Roy Franz | /* Open code a private version of pflash registration since we
|
485 | b8433303 | Roy Franz | * need to set non-default device width for VExpress platform.
|
486 | b8433303 | Roy Franz | */
|
487 | b8433303 | Roy Franz | static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, |
488 | b8433303 | Roy Franz | DriveInfo *di) |
489 | b8433303 | Roy Franz | { |
490 | b8433303 | Roy Franz | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); |
491 | b8433303 | Roy Franz | |
492 | b8433303 | Roy Franz | if (di && qdev_prop_set_drive(dev, "drive", di->bdrv)) { |
493 | b8433303 | Roy Franz | abort(); |
494 | b8433303 | Roy Franz | } |
495 | b8433303 | Roy Franz | |
496 | b8433303 | Roy Franz | qdev_prop_set_uint32(dev, "num-blocks",
|
497 | b8433303 | Roy Franz | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); |
498 | b8433303 | Roy Franz | qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
|
499 | b8433303 | Roy Franz | qdev_prop_set_uint8(dev, "width", 4); |
500 | b8433303 | Roy Franz | qdev_prop_set_uint8(dev, "device-width", 2); |
501 | b8433303 | Roy Franz | qdev_prop_set_uint8(dev, "big-endian", 0); |
502 | 0163a2dc | Roy Franz | qdev_prop_set_uint16(dev, "id0", 0x89); |
503 | 0163a2dc | Roy Franz | qdev_prop_set_uint16(dev, "id1", 0x18); |
504 | b8433303 | Roy Franz | qdev_prop_set_uint16(dev, "id2", 0x00); |
505 | 0163a2dc | Roy Franz | qdev_prop_set_uint16(dev, "id3", 0x00); |
506 | b8433303 | Roy Franz | qdev_prop_set_string(dev, "name", name);
|
507 | b8433303 | Roy Franz | qdev_init_nofail(dev); |
508 | b8433303 | Roy Franz | |
509 | b8433303 | Roy Franz | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
510 | b8433303 | Roy Franz | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); |
511 | b8433303 | Roy Franz | } |
512 | b8433303 | Roy Franz | |
513 | cef04a26 | Peter Maydell | static void vexpress_common_init(VEDBoardInfo *daughterboard, |
514 | f3cdbc32 | Peter Maydell | QEMUMachineInitArgs *args) |
515 | 4c3b29b8 | Peter Maydell | { |
516 | 4c3b29b8 | Peter Maydell | DeviceState *dev, *sysctl, *pl041; |
517 | 4c3b29b8 | Peter Maydell | qemu_irq pic[64];
|
518 | 4c3b29b8 | Peter Maydell | uint32_t sys_id; |
519 | 3dc3e7dd | Francesco Lavra | DriveInfo *dinfo; |
520 | 8941d6ce | Peter Maydell | pflash_t *pflash0; |
521 | 4c3b29b8 | Peter Maydell | ram_addr_t vram_size, sram_size; |
522 | 4c3b29b8 | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
523 | 4c3b29b8 | Peter Maydell | MemoryRegion *vram = g_new(MemoryRegion, 1);
|
524 | 4c3b29b8 | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
|
525 | 8941d6ce | Peter Maydell | MemoryRegion *flashalias = g_new(MemoryRegion, 1);
|
526 | 8941d6ce | Peter Maydell | MemoryRegion *flash0mem; |
527 | a8170e5e | Avi Kivity | const hwaddr *map = daughterboard->motherboard_map;
|
528 | 31410948 | Peter Maydell | int i;
|
529 | 4c3b29b8 | Peter Maydell | |
530 | cdef10bb | Peter Maydell | daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic); |
531 | 4c3b29b8 | Peter Maydell | |
532 | 2558e0a6 | Peter Maydell | /* Motherboard peripherals: the wiring is the same but the
|
533 | 2558e0a6 | Peter Maydell | * addresses vary between the legacy and A-Series memory maps.
|
534 | 2558e0a6 | Peter Maydell | */
|
535 | 2558e0a6 | Peter Maydell | |
536 | 2055283b | Peter Maydell | sys_id = 0x1190f500;
|
537 | 2055283b | Peter Maydell | |
538 | 2055283b | Peter Maydell | sysctl = qdev_create(NULL, "realview_sysctl"); |
539 | 2055283b | Peter Maydell | qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
|
540 | cdef10bb | Peter Maydell | qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
|
541 | 31410948 | Peter Maydell | qdev_prop_set_uint32(sysctl, "len-db-voltage",
|
542 | 31410948 | Peter Maydell | daughterboard->num_voltage_sensors); |
543 | 31410948 | Peter Maydell | for (i = 0; i < daughterboard->num_voltage_sensors; i++) { |
544 | 31410948 | Peter Maydell | char *propname = g_strdup_printf("db-voltage[%d]", i); |
545 | 31410948 | Peter Maydell | qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); |
546 | 31410948 | Peter Maydell | g_free(propname); |
547 | 31410948 | Peter Maydell | } |
548 | 9c7d4893 | Peter Maydell | qdev_prop_set_uint32(sysctl, "len-db-clock",
|
549 | 9c7d4893 | Peter Maydell | daughterboard->num_clocks); |
550 | 9c7d4893 | Peter Maydell | for (i = 0; i < daughterboard->num_clocks; i++) { |
551 | 9c7d4893 | Peter Maydell | char *propname = g_strdup_printf("db-clock[%d]", i); |
552 | 9c7d4893 | Peter Maydell | qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); |
553 | 9c7d4893 | Peter Maydell | g_free(propname); |
554 | 9c7d4893 | Peter Maydell | } |
555 | 7a65c8cc | Peter Maydell | qdev_init_nofail(sysctl); |
556 | 1356b98d | Andreas Färber | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
|
557 | 2558e0a6 | Peter Maydell | |
558 | 2558e0a6 | Peter Maydell | /* VE_SP810: not modelled */
|
559 | 2558e0a6 | Peter Maydell | /* VE_SERIALPCI: not modelled */
|
560 | 2055283b | Peter Maydell | |
561 | 03a0e944 | Peter Maydell | pl041 = qdev_create(NULL, "pl041"); |
562 | 03a0e944 | Peter Maydell | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
563 | 03a0e944 | Peter Maydell | qdev_init_nofail(pl041); |
564 | 1356b98d | Andreas Färber | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
|
565 | 1356b98d | Andreas Färber | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); |
566 | 2055283b | Peter Maydell | |
567 | 2558e0a6 | Peter Maydell | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
568 | 2055283b | Peter Maydell | /* Wire up MMC card detect and read-only signals */
|
569 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 0,
|
570 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); |
571 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 1,
|
572 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); |
573 | 2055283b | Peter Maydell | |
574 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
575 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); |
576 | 2055283b | Peter Maydell | |
577 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
578 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); |
579 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); |
580 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); |
581 | 2055283b | Peter Maydell | |
582 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
583 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); |
584 | 2055283b | Peter Maydell | |
585 | 2558e0a6 | Peter Maydell | /* VE_SERIALDVI: not modelled */
|
586 | 2055283b | Peter Maydell | |
587 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
588 | 2055283b | Peter Maydell | |
589 | 2558e0a6 | Peter Maydell | /* VE_COMPACTFLASH: not modelled */
|
590 | 2055283b | Peter Maydell | |
591 | b7206878 | Peter Maydell | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
592 | 2055283b | Peter Maydell | |
593 | 3dc3e7dd | Francesco Lavra | dinfo = drive_get_next(IF_PFLASH); |
594 | b8433303 | Roy Franz | pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
|
595 | b8433303 | Roy Franz | dinfo); |
596 | 8941d6ce | Peter Maydell | if (!pflash0) {
|
597 | 3dc3e7dd | Francesco Lavra | fprintf(stderr, "vexpress: error registering flash 0.\n");
|
598 | 3dc3e7dd | Francesco Lavra | exit(1);
|
599 | 3dc3e7dd | Francesco Lavra | } |
600 | 3dc3e7dd | Francesco Lavra | |
601 | 8941d6ce | Peter Maydell | if (map[VE_NORFLASHALIAS] != -1) { |
602 | 8941d6ce | Peter Maydell | /* Map flash 0 as an alias into low memory */
|
603 | 8941d6ce | Peter Maydell | flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
|
604 | 8941d6ce | Peter Maydell | memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", |
605 | 8941d6ce | Peter Maydell | flash0mem, 0, VEXPRESS_FLASH_SIZE);
|
606 | 8941d6ce | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); |
607 | 8941d6ce | Peter Maydell | } |
608 | 8941d6ce | Peter Maydell | |
609 | 3dc3e7dd | Francesco Lavra | dinfo = drive_get_next(IF_PFLASH); |
610 | b8433303 | Roy Franz | if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", |
611 | b8433303 | Roy Franz | dinfo)) { |
612 | 3dc3e7dd | Francesco Lavra | fprintf(stderr, "vexpress: error registering flash 1.\n");
|
613 | 3dc3e7dd | Francesco Lavra | exit(1);
|
614 | 3dc3e7dd | Francesco Lavra | } |
615 | 2558e0a6 | Peter Maydell | |
616 | 2055283b | Peter Maydell | sram_size = 0x2000000;
|
617 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size); |
618 | c5705a77 | Avi Kivity | vmstate_register_ram_global(sram); |
619 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
620 | 2055283b | Peter Maydell | |
621 | 2055283b | Peter Maydell | vram_size = 0x800000;
|
622 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size); |
623 | c5705a77 | Avi Kivity | vmstate_register_ram_global(vram); |
624 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
625 | 2055283b | Peter Maydell | |
626 | 2055283b | Peter Maydell | /* 0x4e000000 LAN9118 Ethernet */
|
627 | a005d073 | Stefan Hajnoczi | if (nd_table[0].used) { |
628 | 2558e0a6 | Peter Maydell | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
629 | 2055283b | Peter Maydell | } |
630 | 2055283b | Peter Maydell | |
631 | 2558e0a6 | Peter Maydell | /* VE_USB: not modelled */
|
632 | 2558e0a6 | Peter Maydell | |
633 | 2558e0a6 | Peter Maydell | /* VE_DAPROM: not modelled */
|
634 | 2055283b | Peter Maydell | |
635 | c8a07b35 | Peter Maydell | /* Create mmio transports, so the user can create virtio backends
|
636 | c8a07b35 | Peter Maydell | * (which will be automatically plugged in to the transports). If
|
637 | c8a07b35 | Peter Maydell | * no backend is created the transport will just sit harmlessly idle.
|
638 | c8a07b35 | Peter Maydell | */
|
639 | c8a07b35 | Peter Maydell | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { |
640 | c8a07b35 | Peter Maydell | sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, |
641 | c8a07b35 | Peter Maydell | pic[40 + i]);
|
642 | c8a07b35 | Peter Maydell | } |
643 | c8a07b35 | Peter Maydell | |
644 | cef04a26 | Peter Maydell | daughterboard->bootinfo.ram_size = args->ram_size; |
645 | cef04a26 | Peter Maydell | daughterboard->bootinfo.kernel_filename = args->kernel_filename; |
646 | cef04a26 | Peter Maydell | daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline; |
647 | cef04a26 | Peter Maydell | daughterboard->bootinfo.initrd_filename = args->initrd_filename; |
648 | cef04a26 | Peter Maydell | daughterboard->bootinfo.nb_cpus = smp_cpus; |
649 | cef04a26 | Peter Maydell | daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; |
650 | cef04a26 | Peter Maydell | daughterboard->bootinfo.loader_start = daughterboard->loader_start; |
651 | cef04a26 | Peter Maydell | daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; |
652 | cef04a26 | Peter Maydell | daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
|
653 | cef04a26 | Peter Maydell | daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; |
654 | c8a07b35 | Peter Maydell | daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; |
655 | cef04a26 | Peter Maydell | arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); |
656 | 2055283b | Peter Maydell | } |
657 | 2055283b | Peter Maydell | |
658 | 5f072e1f | Eduardo Habkost | static void vexpress_a9_init(QEMUMachineInitArgs *args) |
659 | 4c3b29b8 | Peter Maydell | { |
660 | f3cdbc32 | Peter Maydell | vexpress_common_init(&a9_daughterboard, args); |
661 | 4c3b29b8 | Peter Maydell | } |
662 | 2055283b | Peter Maydell | |
663 | 5f072e1f | Eduardo Habkost | static void vexpress_a15_init(QEMUMachineInitArgs *args) |
664 | 961f195e | Peter Maydell | { |
665 | f3cdbc32 | Peter Maydell | vexpress_common_init(&a15_daughterboard, args); |
666 | 961f195e | Peter Maydell | } |
667 | 961f195e | Peter Maydell | |
668 | 2055283b | Peter Maydell | static QEMUMachine vexpress_a9_machine = {
|
669 | 2055283b | Peter Maydell | .name = "vexpress-a9",
|
670 | 2055283b | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A9",
|
671 | 2055283b | Peter Maydell | .init = vexpress_a9_init, |
672 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
673 | 2055283b | Peter Maydell | .max_cpus = 4,
|
674 | 2055283b | Peter Maydell | }; |
675 | 2055283b | Peter Maydell | |
676 | 961f195e | Peter Maydell | static QEMUMachine vexpress_a15_machine = {
|
677 | 961f195e | Peter Maydell | .name = "vexpress-a15",
|
678 | 961f195e | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A15",
|
679 | 961f195e | Peter Maydell | .init = vexpress_a15_init, |
680 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
681 | 961f195e | Peter Maydell | .max_cpus = 4,
|
682 | 961f195e | Peter Maydell | }; |
683 | 961f195e | Peter Maydell | |
684 | 2055283b | Peter Maydell | static void vexpress_machine_init(void) |
685 | 2055283b | Peter Maydell | { |
686 | 2055283b | Peter Maydell | qemu_register_machine(&vexpress_a9_machine); |
687 | 961f195e | Peter Maydell | qemu_register_machine(&vexpress_a15_machine); |
688 | 2055283b | Peter Maydell | } |
689 | 2055283b | Peter Maydell | |
690 | 2055283b | Peter Maydell | machine_init(vexpress_machine_init); |