Revision 5a5012ec target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
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/* Define a implementation number of 1. |
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Define a major version 1, minor version 0. */ |
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#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
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#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
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struct mips_def_t {
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| ... | ... | |
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int32_t CP0_Config7; |
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int32_t SYNCI_Step; |
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int32_t CCRes; |
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int32_t Status_rw_bitmask; |
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int32_t CP1_fcr0; |
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}; |
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|
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0,
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.Status_rw_bitmask = 0x3278FF17,
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}, |
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{
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.name = "4KEcR1", |
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0, |
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}, |
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{
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.name = "4KEc", |
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0,
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.Status_rw_bitmask = 0x3278FF17,
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}, |
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{
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.name = "24Kc", |
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0,
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.Status_rw_bitmask = 0x3278FF17,
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}, |
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{
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.name = "24Kf", |
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0, |
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.Status_rw_bitmask = 0x3678FF17, |
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
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}, |
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#else |
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{
|
| ... | ... | |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 16, |
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.CCRes = 2, |
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.CP1_fcr0 = MIPS_FCR0, |
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.Status_rw_bitmask = 0x3678FFFF, |
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | |
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(0x4 << FCR0_PRID) | (0x0 << FCR0_REV), |
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}, |
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#endif |
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}; |
| ... | ... | |
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env->CP0_Config7 = def->CP0_Config7; |
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env->SYNCI_Step = def->SYNCI_Step; |
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env->CCRes = def->CCRes; |
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env->Status_rw_bitmask = def->Status_rw_bitmask; |
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env->fcr0 = def->CP1_fcr0; |
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#if defined (MIPS_USES_R4K_TLB) |
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env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
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